From: Hongyu Wang <hongyu.wang@intel.com>
To: gcc-patches@gcc.gnu.org
Cc: ubizjak@gmail.com, hongtao.liu@intel.com
Subject: [PATCH 16/17] [APX NDD] Support APX NDD for cmove insns
Date: Tue, 5 Dec 2023 10:29:47 +0800 [thread overview]
Message-ID: <20231205022948.504790-17-hongyu.wang@intel.com> (raw)
In-Reply-To: <20231205022948.504790-1-hongyu.wang@intel.com>
gcc/ChangeLog:
* config/i386/i386.md (*mov<mode>cc_noc): Extend with new constraints
to support NDD.
(*movsicc_noc_zext): Likewise.
(*movsicc_noc_zext_1): Likewise.
(*movqicc_noc): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-ndd-cmov.c: New test.
---
gcc/config/i386/i386.md | 48 ++++++++++++--------
gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c | 16 +++++++
2 files changed, 45 insertions(+), 19 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0af7e82deee..853f53c2bb9 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -24412,47 +24412,56 @@ (define_split
(neg:SWI (ltu:SWI (reg:CCC FLAGS_REG) (const_int 0))))])
(define_insn "*mov<mode>cc_noc"
- [(set (match_operand:SWI248 0 "register_operand" "=r,r")
+ [(set (match_operand:SWI248 0 "register_operand" "=r,r,r,r")
(if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:SWI248 2 "nonimmediate_operand" "rm,0")
- (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))]
+ (match_operand:SWI248 2 "nonimmediate_operand" "rm,0,rm,r")
+ (match_operand:SWI248 3 "nonimmediate_operand" "0,rm,r,rm")))]
"TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
+ cmov%O2%c1\t{%3, %0|%0, %3}
+ cmov%O2%C1\t{%2, %3, %0|%0, %3, %2}
+ cmov%O2%c1\t{%3, %2, %0|%0, %2, %3}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "<MODE>")])
(define_insn "*movsicc_noc_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm,0"))
+ (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm,r"))
(zero_extend:DI
- (match_operand:SI 3 "nonimmediate_operand" "0,rm"))))]
+ (match_operand:SI 3 "nonimmediate_operand" "0,rm,r,rm"))))]
"TARGET_64BIT
&& TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %k0|%k0, %2}
- cmov%O2%c1\t{%3, %k0|%k0, %3}"
- [(set_attr "type" "icmov")
+ cmov%O2%c1\t{%3, %k0|%k0, %3}
+ cmov%O2%C1\t{%2, %3, %k0|%k0, %3, %2}
+ cmov%O2%c1\t{%3, %2, %k0|%k0, %2, %3}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "SI")])
(define_insn "*movsicc_noc_zext_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r")
(zero_extend:DI
(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:SI 2 "nonimmediate_operand" "rm,0")
- (match_operand:SI 3 "nonimmediate_operand" "0,rm"))))]
+ (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm,r")
+ (match_operand:SI 3 "nonimmediate_operand" "0,rm,r,rm"))))]
"TARGET_64BIT
&& TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %k0|%k0, %2}
- cmov%O2%c1\t{%3, %k0|%k0, %3}"
- [(set_attr "type" "icmov")
+ cmov%O2%c1\t{%3, %k0|%k0, %3}
+ cmov%O2%C1\t{%2, %3, %k0|%k0, %3, %2}
+ cmov%O2%c1\t{%3, %2, %k0|%k0, %2, %3}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "SI")])
@@ -24477,14 +24486,15 @@ (define_split
})
(define_insn "*movqicc_noc"
- [(set (match_operand:QI 0 "register_operand" "=r,r")
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:QI 2 "register_operand" "r,0")
- (match_operand:QI 3 "register_operand" "0,r")))]
+ (match_operand:QI 2 "register_operand" "r,0,r")
+ (match_operand:QI 3 "register_operand" "0,r,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
"#"
- [(set_attr "type" "icmov")
+ [(set_attr "isa" "*,*,apx_ndd")
+ (set_attr "type" "icmov")
(set_attr "mode" "QI")])
(define_split
diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c b/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c
new file mode 100644
index 00000000000..459dc965342
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -m64 -mapxf" } */
+/* { dg-final { scan-assembler-times "cmove\[^\n\r]*, %eax" 1 } } */
+/* { dg-final { scan-assembler-times "cmovge\[^\n\r]*, %eax" 1 } } */
+
+unsigned int c[4];
+
+unsigned long long foo1 (int a, unsigned int b)
+{
+ return a ? b : c[1];
+}
+
+unsigned int foo3 (int a, int b, unsigned int c, unsigned int d)
+{
+ return a < b ? c : d;
+}
--
2.31.1
next prev parent reply other threads:[~2023-12-05 2:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 2:29 [PATCH v2 00/17] Support Intel APX NDD Hongyu Wang
2023-12-05 2:29 ` [PATCH 01/17] [APX NDD] Support Intel APX NDD for legacy add insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 02/17] [APX NDD] Restrict TImode register usage when NDD enabled Hongyu Wang
2023-12-05 10:46 ` Uros Bizjak
2023-12-06 1:24 ` Hongyu Wang
2023-12-06 6:55 ` Uros Bizjak
2023-12-05 2:29 ` [PATCH 03/17] [APX NDD] Support APX NDD for optimization patterns of add Hongyu Wang
2023-12-05 11:20 ` Uros Bizjak
2023-12-05 2:29 ` [PATCH 04/17] [APX NDD] Disable seg_prefixed memory usage for NDD add Hongyu Wang
2023-12-05 2:29 ` [PATCH 05/17] [APX NDD] Support APX NDD for adc insns Hongyu Wang
2023-12-05 11:25 ` Uros Bizjak
2023-12-05 2:29 ` [PATCH 06/17] [APX NDD] Support APX NDD for sub insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 07/17] [APX NDD] Support APX NDD for sbb insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 08/17] [APX NDD] Support APX NDD for neg insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 09/17] [APX NDD] Support APX NDD for not insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 10/17] [APX NDD] Support APX NDD for and insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 11/17] [APX NDD] Support APX NDD for or/xor insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 12/17] [APX NDD] Support APX NDD for left shift insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 13/17] [APX NDD] Support APX NDD for right " Hongyu Wang
2023-12-05 2:29 ` [PATCH 14/17] [APX NDD] Support APX NDD for rotate insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 15/17] [APX NDD] Support APX NDD for shld/shrd insns Hongyu Wang
2023-12-05 2:29 ` Hongyu Wang [this message]
2023-12-05 2:29 ` [PATCH 17/17] [APX NDD] Support TImode shift for NDD Hongyu Wang
2023-12-05 3:48 ` [PATCH v2 00/17] Support Intel APX NDD Hongtao Liu
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