From: Uros Bizjak <ubizjak@gmail.com>
To: Hongyu Wang <hongyu.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com,
Kong Lingling <lingling.kong@intel.com>
Subject: Re: [PATCH 05/17] [APX NDD] Support APX NDD for adc insns
Date: Tue, 5 Dec 2023 12:25:48 +0100 [thread overview]
Message-ID: <CAFULd4b9=YkXEM9dv5wXgXSOYTy8TWvvaAg1GY1BYwAKubG7tA@mail.gmail.com> (raw)
In-Reply-To: <20231205022948.504790-6-hongyu.wang@intel.com>
On Tue, Dec 5, 2023 at 3:29 AM Hongyu Wang <hongyu.wang@intel.com> wrote:
>
> From: Kong Lingling <lingling.kong@intel.com>
>
> Legacy adc patterns are commonly adopted to TImode add, when extending TImode
> add to NDD version, operands[0] and operands[1] can be different, so extra move
> should be emitted if those patterns have optimization when adding const0_rtx.
>
> NDD instructions will automatically zero-extend dest register to 64bit, so for
> zext patterns it can adopt all NDD form that have memory src input.
>
> gcc/ChangeLog:
>
> * config/i386/i386.md (*add<dwi>3_doubleword): Add ndd constraints, and
> move operands[1] to operands[0] when they are not equal.
> (*add<dwi>3_doubleword_cc_overflow_1): Likewise.
> (*add<dwi>3_doubleword_zext): Add ndd constraints.
> (*addv<dwi>4_doubleword): Likewise.
> (*addv<dwi>4_doubleword_1): Likewise.
> (addv<mode>4_overflow_1): Likewise.
> (*addv<mode>4_overflow_2): Likewise.
> (@add<mode>3_carry): Likewise.
> (*add<mode>3_carry_0): Likewise.
> (*addsi3_carry_zext): Likewise.
> (addcarry<mode>): Likewise.
> (addcarry<mode>_0): Likewise.
> (*addcarry<mode>_1): Likewise.
> (*add<mode>3_eq): Likewise.
> (*add<mode>3_ne): Likewise.
> (*addsi3_carry_zext_0): Likewise, and use nonimmediate_operand for
> operands[1] to accept memory input for NDD alternative.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/apx-ndd-adc.c: New test.
> ---
> gcc/config/i386/i386.md | 191 ++++++++++++--------
> gcc/testsuite/gcc.target/i386/apx-ndd-adc.c | 15 ++
> 2 files changed, 134 insertions(+), 72 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-adc.c
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 6b316e698bb..358a3857f89 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -6291,12 +6291,12 @@ (define_expand "add<mode>3"
> TARGET_APX_NDD); DONE;")
>
> (define_insn_and_split "*add<dwi>3_doubleword"
> - [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
> + [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,r,r")
> (plus:<DWI>
> - (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
> - (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o")))
> + (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r")
> + (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r<di>,r")))
> (clobber (reg:CC FLAGS_REG))]
If we relax the requirement for TImode register pair, then =&r output
should be used here (and in other TImode instructions) for apx_ndd
ISA.
Uros.
next prev parent reply other threads:[~2023-12-05 11:26 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 2:29 [PATCH v2 00/17] Support Intel APX NDD Hongyu Wang
2023-12-05 2:29 ` [PATCH 01/17] [APX NDD] Support Intel APX NDD for legacy add insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 02/17] [APX NDD] Restrict TImode register usage when NDD enabled Hongyu Wang
2023-12-05 10:46 ` Uros Bizjak
2023-12-06 1:24 ` Hongyu Wang
2023-12-06 6:55 ` Uros Bizjak
2023-12-05 2:29 ` [PATCH 03/17] [APX NDD] Support APX NDD for optimization patterns of add Hongyu Wang
2023-12-05 11:20 ` Uros Bizjak
2023-12-05 2:29 ` [PATCH 04/17] [APX NDD] Disable seg_prefixed memory usage for NDD add Hongyu Wang
2023-12-05 2:29 ` [PATCH 05/17] [APX NDD] Support APX NDD for adc insns Hongyu Wang
2023-12-05 11:25 ` Uros Bizjak [this message]
2023-12-05 2:29 ` [PATCH 06/17] [APX NDD] Support APX NDD for sub insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 07/17] [APX NDD] Support APX NDD for sbb insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 08/17] [APX NDD] Support APX NDD for neg insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 09/17] [APX NDD] Support APX NDD for not insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 10/17] [APX NDD] Support APX NDD for and insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 11/17] [APX NDD] Support APX NDD for or/xor insn Hongyu Wang
2023-12-05 2:29 ` [PATCH 12/17] [APX NDD] Support APX NDD for left shift insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 13/17] [APX NDD] Support APX NDD for right " Hongyu Wang
2023-12-05 2:29 ` [PATCH 14/17] [APX NDD] Support APX NDD for rotate insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 15/17] [APX NDD] Support APX NDD for shld/shrd insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 16/17] [APX NDD] Support APX NDD for cmove insns Hongyu Wang
2023-12-05 2:29 ` [PATCH 17/17] [APX NDD] Support TImode shift for NDD Hongyu Wang
2023-12-05 3:48 ` [PATCH v2 00/17] Support Intel APX NDD Hongtao Liu
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