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From: Uros Bizjak <ubizjak@gmail.com>
To: Hongyu Wang <wwwhhhyyy333@gmail.com>
Cc: Hongyu Wang <hongyu.wang@intel.com>,
	gcc-patches@gcc.gnu.org, hongtao.liu@intel.com
Subject: Re: [PATCH 02/17] [APX NDD] Restrict TImode register usage when NDD enabled
Date: Wed, 6 Dec 2023 07:55:16 +0100	[thread overview]
Message-ID: <CAFULd4YFCwQ0mKf4yAGPieCBnEmBPmK3UPn7ADws-tQ=rNyf_g@mail.gmail.com> (raw)
In-Reply-To: <CA+OydWmKHYP=sRiBi18SYTwT1BTBYzMjLABu6iSF7r4xxOsKGw@mail.gmail.com>

On Wed, Dec 6, 2023 at 2:31 AM Hongyu Wang <wwwhhhyyy333@gmail.com> wrote:
>
> Uros Bizjak <ubizjak@gmail.com> 于2023年12月5日周二 18:46写道:
>
> >
> > On Tue, Dec 5, 2023 at 3:29 AM Hongyu Wang <hongyu.wang@intel.com> wrote:
> > >
> > > Under APX NDD, previous TImode allocation will have issue that it was
> > > originally allocated using continuous pair, like rax:rdi, rdi:rdx.
> > >
> > > This will cause issue for all TImode NDD patterns. For NDD we will not
> > > assume the arithmetic operations like add have dependency between dest
> > > and src1, then write to 1st highpart rdi will be overrided by the 2nd
> > > lowpart rdi if 2nd lowpart rdi have different src as input, then the write
> > > to 1st highpart rdi will missed and cause miscompliation.
> > >
> > > To resolve this, under TARGET_APX_NDD we'd only allow register with even
> > > regno to be allocated with TImode, then TImode registers will be allocated
> > > with non-overlapping pairs.
> >
> > Perhaps you could use earlyclobber with __doubleword instructions:
> >
> > (define_insn_and_split "*add<dwi>3_doubleword"
> >   [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
> >     (plus:<DWI>
> >       (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
> >       (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o")))
> >    (clobber (reg:CC FLAGS_REG))]
> >
> > For the above pattern, you can add earlyclobbered &r output
> > alternative that guarantees that output won't be allocated to any of
> > the input registers.
> >
>
> Yes, it does resolve the dest/src overlapping issue we met, thanks!
> I tried it and no fails in gcc-testsuite and spec. Suppose for
> different src1/src2 RA can handle them correctly.

Yes, and when memory input operand is used in doubleword patterns, you
need earlyclobber anyway, otherwise nothing prevents the compiler from
clobbering address registers. When addr registers are dead, the
compiler can (and will) allocate output register to the same regno as
address register.

Uros,

> Will update in V3 patches with the changes of get_attr_isa (insn) == ISA_APX_NDD

  reply	other threads:[~2023-12-06  6:55 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-05  2:29 [PATCH v2 00/17] Support Intel APX NDD Hongyu Wang
2023-12-05  2:29 ` [PATCH 01/17] [APX NDD] Support Intel APX NDD for legacy add insn Hongyu Wang
2023-12-05  2:29 ` [PATCH 02/17] [APX NDD] Restrict TImode register usage when NDD enabled Hongyu Wang
2023-12-05 10:46   ` Uros Bizjak
2023-12-06  1:24     ` Hongyu Wang
2023-12-06  6:55       ` Uros Bizjak [this message]
2023-12-05  2:29 ` [PATCH 03/17] [APX NDD] Support APX NDD for optimization patterns of add Hongyu Wang
2023-12-05 11:20   ` Uros Bizjak
2023-12-05  2:29 ` [PATCH 04/17] [APX NDD] Disable seg_prefixed memory usage for NDD add Hongyu Wang
2023-12-05  2:29 ` [PATCH 05/17] [APX NDD] Support APX NDD for adc insns Hongyu Wang
2023-12-05 11:25   ` Uros Bizjak
2023-12-05  2:29 ` [PATCH 06/17] [APX NDD] Support APX NDD for sub insns Hongyu Wang
2023-12-05  2:29 ` [PATCH 07/17] [APX NDD] Support APX NDD for sbb insn Hongyu Wang
2023-12-05  2:29 ` [PATCH 08/17] [APX NDD] Support APX NDD for neg insn Hongyu Wang
2023-12-05  2:29 ` [PATCH 09/17] [APX NDD] Support APX NDD for not insn Hongyu Wang
2023-12-05  2:29 ` [PATCH 10/17] [APX NDD] Support APX NDD for and insn Hongyu Wang
2023-12-05  2:29 ` [PATCH 11/17] [APX NDD] Support APX NDD for or/xor insn Hongyu Wang
2023-12-05  2:29 ` [PATCH 12/17] [APX NDD] Support APX NDD for left shift insns Hongyu Wang
2023-12-05  2:29 ` [PATCH 13/17] [APX NDD] Support APX NDD for right " Hongyu Wang
2023-12-05  2:29 ` [PATCH 14/17] [APX NDD] Support APX NDD for rotate insns Hongyu Wang
2023-12-05  2:29 ` [PATCH 15/17] [APX NDD] Support APX NDD for shld/shrd insns Hongyu Wang
2023-12-05  2:29 ` [PATCH 16/17] [APX NDD] Support APX NDD for cmove insns Hongyu Wang
2023-12-05  2:29 ` [PATCH 17/17] [APX NDD] Support TImode shift for NDD Hongyu Wang
2023-12-05  3:48 ` [PATCH v2 00/17] Support Intel APX NDD Hongtao Liu

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