From: will schmidt <will_schmidt@vnet.ibm.com>
To: GCC Patches <gcc-patches@gcc.gnu.org>
Cc: David Edelsohn <dje.gcc@gmail.com>,
Segher Boessenkool <segher@kernel.crashing.org>,
"Kewen.Lin" <linkw@linux.ibm.com>
Subject: [PATCH, rs6000, v2] Cleanup some vstrir define_expand naming inconsistencies
Date: Tue, 19 Jul 2022 15:14:52 -0500 [thread overview]
Message-ID: <31dc528de363088ba74e82ca0fbca06e3dc5ac58.camel@vnet.ibm.com> (raw)
In-Reply-To: <6da1e35def9d282bcf87483e78cf578fff604723.camel@vnet.ibm.com>
[PATCH, rs6000, v2] Cleanup some vstrir define_expand naming inconsistencies
Hi,
This cleans up some of the naming around the vstrir and vstril
instruction definitions, with some cosmetic changes for consistency.
No functional changes.
Regtested just in case, no regressions.
[V2]
Used 'direct' instead of 'internal', and cosmetically reworked
the changelog.
OK for trunk?
Thanks,
gcc/
* config/rs6000/altivec.md:
(vstrir_code_<mode>): Rename to...
(vstrir_direct_<mode>): ... this.
(vstrir_p_code_<mode>): Rename to...
(vstrir_p_direct_<mode>): ... this.
(vstril_code_<mode>): Rename to...
(vstril_direct_<mode>): ... this.
(vstril_p_code_<mode>): Rename to...
(vstril_p_direct_<mode>): ... this.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index efc8ae35c2e7..2c4940f2e21c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -884,44 +884,44 @@ (define_expand "vstrir_<mode>"
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
UNSPEC_VSTRIR))]
"TARGET_POWER10"
{
if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vstrir_code_<mode> (operands[0], operands[1]));
+ emit_insn (gen_vstrir_direct_<mode> (operands[0], operands[1]));
else
- emit_insn (gen_vstril_code_<mode> (operands[0], operands[1]));
+ emit_insn (gen_vstril_direct_<mode> (operands[0], operands[1]));
DONE;
})
-(define_insn "vstrir_code_<mode>"
+(define_insn "vstrir_direct_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
(unspec:VIshort
[(match_operand:VIshort 1 "altivec_register_operand" "v")]
UNSPEC_VSTRIR))]
"TARGET_POWER10"
"vstri<wd>r %0,%1"
[(set_attr "type" "vecsimple")])
-;; This expands into same code as vstrir_<mode> followed by condition logic
+;; This expands into same code as vstrir<mode> followed by condition logic
;; so that a single vstribr. or vstrihr. or vstribl. or vstrihl. instruction
;; can, for example, satisfy the needs of a vec_strir () function paired
;; with a vec_strir_p () function if both take the same incoming arguments.
(define_expand "vstrir_p_<mode>"
[(match_operand:SI 0 "gpc_reg_operand")
(match_operand:VIshort 1 "altivec_register_operand")]
"TARGET_POWER10"
{
rtx scratch = gen_reg_rtx (<MODE>mode);
if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vstrir_p_code_<mode> (scratch, operands[1]));
+ emit_insn (gen_vstrir_p_direct_<mode> (scratch, operands[1]));
else
- emit_insn (gen_vstril_p_code_<mode> (scratch, operands[1]));
+ emit_insn (gen_vstril_p_direct_<mode> (scratch, operands[1]));
emit_insn (gen_cr6_test_for_zero (operands[0]));
DONE;
})
-(define_insn "vstrir_p_code_<mode>"
+(define_insn "vstrir_p_direct_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
(unspec:VIshort
[(match_operand:VIshort 1 "altivec_register_operand" "v")]
UNSPEC_VSTRIR))
(set (reg:CC CR6_REGNO)
@@ -936,17 +936,17 @@ (define_expand "vstril_<mode>"
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
UNSPEC_VSTRIR))]
"TARGET_POWER10"
{
if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vstril_code_<mode> (operands[0], operands[1]));
+ emit_insn (gen_vstril_direct_<mode> (operands[0], operands[1]));
else
- emit_insn (gen_vstrir_code_<mode> (operands[0], operands[1]));
+ emit_insn (gen_vstrir_direct_<mode> (operands[0], operands[1]));
DONE;
})
-(define_insn "vstril_code_<mode>"
+(define_insn "vstril_direct_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
(unspec:VIshort
[(match_operand:VIshort 1 "altivec_register_operand" "v")]
UNSPEC_VSTRIL))]
"TARGET_POWER10"
@@ -962,18 +962,18 @@ (define_expand "vstril_p_<mode>"
(match_operand:VIshort 1 "altivec_register_operand")]
"TARGET_POWER10"
{
rtx scratch = gen_reg_rtx (<MODE>mode);
if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vstril_p_code_<mode> (scratch, operands[1]));
+ emit_insn (gen_vstril_p_direct_<mode> (scratch, operands[1]));
else
- emit_insn (gen_vstrir_p_code_<mode> (scratch, operands[1]));
+ emit_insn (gen_vstrir_p_direct_<mode> (scratch, operands[1]));
emit_insn (gen_cr6_test_for_zero (operands[0]));
DONE;
})
-(define_insn "vstril_p_code_<mode>"
+(define_insn "vstril_p_direct_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand" "=v")
(unspec:VIshort
[(match_operand:VIshort 1 "altivec_register_operand" "v")]
UNSPEC_VSTRIL))
(set (reg:CC CR6_REGNO)
next prev parent reply other threads:[~2022-07-19 20:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 18:18 [PATCH, rs6000] " will schmidt
2022-07-13 19:39 ` Segher Boessenkool
2022-07-13 21:14 ` will schmidt
2022-07-13 21:26 ` Segher Boessenkool
2022-07-19 20:14 ` will schmidt [this message]
2022-07-20 22:15 ` [PATCH, rs6000, v2] " Segher Boessenkool
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