From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: Richard Biener <rguenther@suse.de>
Cc: gcc-patches@gcc.gnu.org, Richard.Sandiford@arm.com
Subject: Re: [PATCH 1/3] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE
Date: Thu, 1 Feb 2024 17:01:40 +0000 [thread overview]
Message-ID: <359e8112-65c9-40b1-9566-aa31165c05e8@arm.com> (raw)
In-Reply-To: <n61p6q9n-pqp5-9o94-3n33-9988p61056r2@fhfr.qr>
On 01/02/2024 07:19, Richard Biener wrote:
> On Wed, 31 Jan 2024, Andre Vieira (lists) wrote:
>
>
> The patch didn't come with a testcase so it's really hard to tell
> what goes wrong now and how it is fixed ...
My bad! I had a testcase locally but never added it...
However... now I look at it and ran it past Richard S, the codegen isn't
'wrong', but it does have the potential to lead to some pretty slow
codegen, especially for inbranch simdclones where it transforms the SVE
predicate into an Advanced SIMD vector by inserting the elements one at
a time...
An example of which can be seen if you do:
gcc -O3 -march=armv8-a+sve -msve-vector-bits=128 -fopenmp-simd t.c -S
with the following t.c:
#pragma omp declare simd simdlen(4) inbranch
int __attribute__ ((const)) fn5(int);
void fn4 (int *a, int *b, int n)
{
for (int i = 0; i < n; ++i)
b[i] = fn5(a[i]);
}
Now I do have to say, for our main usecase of libmvec we won't have any
'inbranch' Advanced SIMD clones, so we avoid that issue... But of course
that doesn't mean user-code will.
I'm gonna remove this patch and run another test regression to see if it
catches anything weird, but if not then I guess we do have the option to
not use this patch and aim to solve the costing or codegen issue in
GCC-15. We don't currently do any simdclone costing and I don't have a
clear suggestion for how given openmp has no mechanism that I know off
to expose the speedup of a simdclone over it's scalar variant, so how
would we 'compare' a simdclone call with extra overhead of argument
preparation vs scalar, though at least we could prefer a call to a
different simdclone with less argument preparation. Anyways I digress.
Other tests, these require aarch64-autovec-preference=2 so that also has
me worried less...
gcc -O3 -march=armv8-a+sve -msve-vector-bits=128 --param
aarch64-autovec-preference=2 -fopenmp-simd t.c -S
t.c:
#pragma omp declare simd simdlen(2) notinbranch
float __attribute__ ((const)) fn1(double);
void fn0 (float *a, float *b, int n)
{
for (int i = 0; i < n; ++i)
b[i] = fn1((double) a[i]);
}
#pragma omp declare simd simdlen(2) notinbranch
float __attribute__ ((const)) fn3(float);
void fn2 (float *a, double *b, int n)
{
for (int i = 0; i < n; ++i)
b[i] = (double) fn3(a[i]);
}
> Richard.
>
>>>
>>> That said, I wonder how we end up mixing things up in the first place.
>>>
>>> Richard.
>>
>
next prev parent reply other threads:[~2024-02-01 17:01 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-30 14:31 [PATCH 0/3] vect, aarch64: Add SVE support for simdclones Andre Vieira
2024-01-30 14:31 ` [PATCH 1/3] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE Andre Vieira
2024-01-31 12:11 ` Richard Biener
2024-01-31 12:13 ` Richard Biener
2024-01-31 13:52 ` Andre Vieira (lists)
2024-01-31 13:58 ` Richard Biener
2024-01-31 14:03 ` Richard Biener
2024-01-31 16:13 ` Andre Vieira (lists)
2024-01-31 14:35 ` Andre Vieira (lists)
2024-01-31 14:35 ` Richard Biener
2024-01-31 16:36 ` Andre Vieira (lists)
2024-02-01 7:19 ` Richard Biener
2024-02-01 17:01 ` Andre Vieira (lists) [this message]
2024-02-05 9:56 ` Richard Biener
2024-02-26 16:56 ` Andre Vieira (lists)
2024-02-27 8:47 ` Richard Biener
2024-02-28 17:25 ` Andre Vieira (lists)
2024-02-29 7:26 ` Richard Biener
2024-02-01 7:59 ` Richard Sandiford
2024-01-30 14:31 ` [PATCH 2/3] vect: disable multiple calls of poly simdclones Andre Vieira
2024-01-31 12:13 ` Richard Biener
2024-01-30 14:31 ` [PATCH 3/3] aarch64: Add SVE support for simd clones [PR 96342] Andre Vieira
2024-02-01 21:59 ` Richard Sandiford
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