Re: [PATCH 1/3] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE

[Richard Biener <rguenther@suse.de>]

On Wed, 31 Jan 2024, Andre Vieira (lists) wrote:

> 
> 
> On 31/01/2024 13:58, Richard Biener wrote:
> > On Wed, 31 Jan 2024, Andre Vieira (lists) wrote:
> > 
> >>
> >>
> >> On 31/01/2024 12:13, Richard Biener wrote:
> >>> On Wed, 31 Jan 2024, Richard Biener wrote:
> >>>
> >>>> On Tue, 30 Jan 2024, Andre Vieira wrote:
> >>>>
> >>>>>
> >>>>> This patch adds stmt_vec_info to TARGET_SIMD_CLONE_USABLE to make sure
> >>>>> the
> >>>>> target can reject a simd_clone based on the vector mode it is using.
> >>>>> This is needed because for VLS SVE vectorization the vectorizer accepts
> >>>>> Advanced SIMD simd clones when vectorizing using SVE types because the
> >>>>> simdlens
> >>>>> might match.  This will cause type errors later on.
> >>>>>
> >>>>> Other targets do not currently need to use this argument.
> >>>>
> >>>> Can you instead pass down the mode?
> >>>
> >>> Thinking about that again the cgraph_simd_clone info in the clone
> >>> should have sufficient information to disambiguate.  If it doesn't
> >>> then we should amend it.
> >>>
> >>> Richard.
> >>
> >> Hi Richard,
> >>
> >> Thanks for the review, I don't think cgraph_simd_clone_info is the right
> >> place
> >> to pass down this information, since this is information about the caller
> >> rather than the simdclone itself. What we are trying to achieve here is
> >> making
> >> the vectorizer being able to accept or reject simdclones based on the ISA
> >> we
> >> are vectorizing for. To distinguish between SVE and Advanced SIMD ISAs we
> >> use
> >> modes, I am also not sure that's ideal but it is what we currently use. So
> >> to
> >> answer your earlier question, yes I can also pass down mode if that's
> >> preferable.
> > 
> > Note cgraph_simd_clone_info has simdlen and we seem to check elsewhere
> > whether that's POLY or constant.  I wonder how aarch64_sve_mode_p
> > comes into play here which in the end classifies VLS SVE modes as
> > non-SVE?
> > 
> 
> Using -msve-vector-bits=128
> (gdb) p TYPE_MODE (STMT_VINFO_VECTYPE (stmt_vinfo))
> $4 = E_VNx4SImode
> (gdb) p  TYPE_SIZE (STMT_VINFO_VECTYPE (stmt_vinfo))
> $5 = (tree) 0xfffff741c1b0
> (gdb) p debug (TYPE_SIZE (STMT_VINFO_VECTYPE (stmt_vinfo)))
> 128
> (gdb) p aarch64_sve_mode_p (TYPE_MODE (STMT_VINFO_VECTYPE (stmt_vinfo)))
> $5 = true
> 
> and for reference without vls codegen:
> (gdb) p TYPE_MODE (STMT_VINFO_VECTYPE (stmt_vinfo))
> $1 = E_VNx4SImode
> (gdb) p  debug (TYPE_SIZE (STMT_VINFO_VECTYPE (stmt_vinfo)))
> POLY_INT_CST [128, 128]
> 
> Having said that I believe that the USABLE targethook implementation for
> aarch64 should also block other uses, like an Advanced SIMD mode being used as
> input for a SVE VLS SIMDCLONE. The reason being that for instance 'half'
> registers like VNx2SI are packed differently from V2SI.
> 
> We could teach the vectorizer to support these of course, but that requires
> more work and is not extremely useful just yet. I'll add the extra check that
> to the patch once we agree on how to pass down the information we need. Happy
> to use either mode, or stmt_vec_info and extract the mode from it like it does
> now.

As said, please pass down 'mode'.  But I wonder how to document it,
which mode is that supposed to be?  Any of result or any argument
mode that happens to be a vector?  I think that we might be able
to mix Advanced SIMD modes and SVE modes with -msve-vector-bits=128
in the same loop?

Are the simd clones you don't want to use with -msve-vector-bits=128
having constant simdlen?  If so why do you generate them in the first
place?

That said, I wonder how we end up mixing things up in the first place.

Richard.