From: Richard Sandiford <richard.sandiford@arm.com>
To: "Andre Vieira \(lists\)" <andre.simoesdiasvieira@arm.com>
Cc: Richard Biener <rguenther@suse.de>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/3] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE
Date: Thu, 01 Feb 2024 07:59:05 +0000 [thread overview]
Message-ID: <mptil3862eu.fsf@arm.com> (raw)
In-Reply-To: <e0448c57-8071-49b0-a551-c3831cf68d63@arm.com> (Andre Vieira's message of "Wed, 31 Jan 2024 16:36:42 +0000")
"Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com> writes:
> [...] The question at hand
> here is, what can the vectorizer use for a specific loop. If we are
> using Advanced SIMD modes then it needs to call an Advanced SIMD clone,
> and if we are using SVE modes then it needs to call an SVE clone. At
> least until we support the ABI conversion, because like I said for an
> unpacked argument they behave differently.
Probably also worth noting that multi-byte elements are laid out
differently for big-endian. E.g. V4SI is loaded as a 128-bit integer
whereas VNx4SI is loaded as an array of 4 32-bit integers, with the
first 32-bit integer going in the least significant bits of the register.
So it would only be possible to use Advanced SIMD clones for SVE modes
and vice versa for little-endian, or if the elements are all bytes,
or if we add some reverses to the inputs and outputs.
Richard
next prev parent reply other threads:[~2024-02-01 7:59 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-30 14:31 [PATCH 0/3] vect, aarch64: Add SVE support for simdclones Andre Vieira
2024-01-30 14:31 ` [PATCH 1/3] vect: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE Andre Vieira
2024-01-31 12:11 ` Richard Biener
2024-01-31 12:13 ` Richard Biener
2024-01-31 13:52 ` Andre Vieira (lists)
2024-01-31 13:58 ` Richard Biener
2024-01-31 14:03 ` Richard Biener
2024-01-31 16:13 ` Andre Vieira (lists)
2024-01-31 14:35 ` Andre Vieira (lists)
2024-01-31 14:35 ` Richard Biener
2024-01-31 16:36 ` Andre Vieira (lists)
2024-02-01 7:19 ` Richard Biener
2024-02-01 17:01 ` Andre Vieira (lists)
2024-02-05 9:56 ` Richard Biener
2024-02-26 16:56 ` Andre Vieira (lists)
2024-02-27 8:47 ` Richard Biener
2024-02-28 17:25 ` Andre Vieira (lists)
2024-02-29 7:26 ` Richard Biener
2024-02-01 7:59 ` Richard Sandiford [this message]
2024-01-30 14:31 ` [PATCH 2/3] vect: disable multiple calls of poly simdclones Andre Vieira
2024-01-31 12:13 ` Richard Biener
2024-01-30 14:31 ` [PATCH 3/3] aarch64: Add SVE support for simd clones [PR 96342] Andre Vieira
2024-02-01 21:59 ` Richard Sandiford
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