* [PATCH] RISC-V: Add v_uimm_operand
@ 2023-05-11 22:00 钟居哲
2023-05-11 22:31 ` Palmer Dabbelt
0 siblings, 1 reply; 3+ messages in thread
From: 钟居哲 @ 2023-05-11 22:00 UTC (permalink / raw)
To: gcc-patches; +Cc: palmer, Jeff Law
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>> ;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR related.
>> (define_predicate "v_uimm_operand"
>> (match_operand 0 "csr_operand"))
To make name consistent, it should be "vector_xxxx", so I suggest it to be "vector_scalar_shift_operand".
Thanks.
juzhe.zhong@rivai.ai
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Add v_uimm_operand
2023-05-11 22:00 [PATCH] RISC-V: Add v_uimm_operand 钟居哲
@ 2023-05-11 22:31 ` Palmer Dabbelt
2023-05-11 22:32 ` 钟居哲
0 siblings, 1 reply; 3+ messages in thread
From: Palmer Dabbelt @ 2023-05-11 22:31 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, jeffreyalaw
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zhong@rivai.ai wrote:
>>> ;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR related.
>>> (define_predicate "v_uimm_operand"
>>> (match_operand 0 "csr_operand"))
> To make name consistent, it should be "vector_xxxx", so I suggest it to be "vector_scalar_shift_operand".
Makes sense, I sent a v2.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Re: [PATCH] RISC-V: Add v_uimm_operand
2023-05-11 22:31 ` Palmer Dabbelt
@ 2023-05-11 22:32 ` 钟居哲
0 siblings, 0 replies; 3+ messages in thread
From: 钟居哲 @ 2023-05-11 22:32 UTC (permalink / raw)
To: palmer; +Cc: gcc-patches, Jeff Law
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LGTM
juzhe.zhong@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-12 06:31
To: juzhe.zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add v_uimm_operand
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zhong@rivai.ai wrote:
>>> ;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR related.
>>> (define_predicate "v_uimm_operand"
>>> (match_operand 0 "csr_operand"))
> To make name consistent, it should be "vector_xxxx", so I suggest it to be "vector_scalar_shift_operand".
Makes sense, I sent a v2.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-05-11 22:32 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2023-05-11 22:00 [PATCH] RISC-V: Add v_uimm_operand 钟居哲
2023-05-11 22:31 ` Palmer Dabbelt
2023-05-11 22:32 ` 钟居哲
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