[PATCH v2] RISC-V: Libitm add RISC-V support.

[PATCH v2] RISC-V: Libitm add RISC-V support.

[Xiongchuan Tan]

libitm/ChangeLog:

        * configure.tgt: Add riscv support.
        * config/riscv/asm.h: New file.
        * config/riscv/sjlj.S: New file.
        * config/riscv/target.h: New file.
---
v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

 libitm/config/riscv/asm.h    |  52 +++++++++++++
 libitm/config/riscv/sjlj.S   | 144 +++++++++++++++++++++++++++++++++++
 libitm/config/riscv/target.h |  50 ++++++++++++
 libitm/configure.tgt         |   2 +
 4 files changed, 248 insertions(+)
 create mode 100644 libitm/config/riscv/asm.h
 create mode 100644 libitm/config/riscv/sjlj.S
 create mode 100644 libitm/config/riscv/target.h

diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h
new file mode 100644
index 0000000..6ba5e2c
--- /dev/null
+++ b/libitm/config/riscv/asm.h
@@ -0,0 +1,52 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _RV_ASM_H
+#define _RV_ASM_H
+
+#if __riscv_xlen == 64
+#  define GPR_L ld
+#  define GPR_S sd
+#  define SZ_GPR 8
+#elif __riscv_xlen == 32
+#  define GPR_L lw
+#  define GPR_S sw
+#  define SZ_GPR 4
+#else
+#  error Unsupported XLEN (must be 64-bit or 32-bit).
+#endif
+
+#if defined(__riscv_flen) && __riscv_flen == 64
+#  define FPR_L fld
+#  define FPR_S fsd
+#  define SZ_FPR 8
+#elif defined(__riscv_flen) && __riscv_flen == 32
+#  define FPR_L flw
+#  define FPR_S fsw
+#  define SZ_FPR 4
+#else
+#  define SZ_FPR 0
+#endif
+
+#endif  /* _RV_ASM_H */
diff --git a/libitm/config/riscv/sjlj.S b/libitm/config/riscv/sjlj.S
new file mode 100644
index 0000000..6f25cb5
--- /dev/null
+++ b/libitm/config/riscv/sjlj.S
@@ -0,0 +1,144 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "asmcfi.h"
+#include "asm.h"
+
+	.text
+	.align	2
+	.global	_ITM_beginTransaction
+	.type	_ITM_beginTransaction, @function
+
+_ITM_beginTransaction:
+	cfi_startproc
+    mv a1, sp
+	addi sp, sp, -(14*SZ_GPR+12*SZ_FPR)
+	cfi_adjust_cfa_offset(14*SZ_GPR+12*SZ_FPR)
+
+	/* Return Address */
+	GPR_S ra, 0*SZ_GPR(sp)
+	cfi_rel_offset(ra, 0*SZ_GPR)
+
+	/* Caller's sp */
+	GPR_S a1, 1*SZ_GPR(sp)
+
+	/* Caller's s0/fp */
+	GPR_S fp, 2*SZ_GPR(sp)
+	cfi_rel_offset(fp, 2*SZ_GPR)
+
+	/* Callee-saved registers */
+	GPR_S s1, 3*SZ_GPR(sp)
+	GPR_S s2, 4*SZ_GPR(sp)
+	GPR_S s3, 5*SZ_GPR(sp)
+	GPR_S s4, 6*SZ_GPR(sp)
+	GPR_S s5, 7*SZ_GPR(sp)
+	GPR_S s6, 8*SZ_GPR(sp)
+	GPR_S s7, 9*SZ_GPR(sp)
+	GPR_S s8, 10*SZ_GPR(sp)
+	GPR_S s9, 11*SZ_GPR(sp)
+	GPR_S s10, 12*SZ_GPR(sp)
+	GPR_S s11, 13*SZ_GPR(sp)
+
+#if defined(__riscv_flen)
+	/* Callee-saved floating-point registers */
+	FPR_S fs0, 0*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs1, 1*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs2, 2*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs3, 3*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs4, 4*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs5, 5*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs6, 6*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs7, 7*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs8, 8*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs9, 9*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs10, 10*SZ_FPR+14*SZ_GPR(sp)
+	FPR_S fs11, 11*SZ_FPR+14*SZ_GPR(sp)
+#endif
+	mv fp, sp
+
+	/* Invoke GTM_begin_transaction with the struct we've just built.  */
+	mv a1, sp
+	jal ra, GTM_begin_transaction
+
+	/* Return; we don't need to restore any of the call-saved regs.  */
+	GPR_L ra, 0*SZ_GPR(sp)
+	cfi_restore(ra)
+	GPR_L fp, 2*SZ_GPR(sp)
+	cfi_restore(fp)
+
+	addi sp, sp, 14*SZ_GPR+12*SZ_FPR
+	cfi_adjust_cfa_offset(-(14*SZ_GPR+12*SZ_FPR))
+
+	ret
+	cfi_endproc
+	.size	_ITM_beginTransaction, . - _ITM_beginTransaction
+
+	.align	2
+	.global	GTM_longjmp
+	.hidden	GTM_longjmp
+	.type	GTM_longjmp, @function
+
+GTM_longjmp:
+	/* The first parameter becomes the return value (a0).
+	   The third parameter is ignored for now.  */
+    cfi_startproc
+	GPR_L s1, 3*SZ_GPR(a1)
+	GPR_L s2, 4*SZ_GPR(a1)
+	GPR_L s3, 5*SZ_GPR(a1)
+	GPR_L s4, 6*SZ_GPR(a1)
+	GPR_L s5, 7*SZ_GPR(a1)
+	GPR_L s6, 8*SZ_GPR(a1)
+	GPR_L s7, 9*SZ_GPR(a1)
+	GPR_L s8, 10*SZ_GPR(a1)
+	GPR_L s9, 11*SZ_GPR(a1)
+	GPR_L s10, 12*SZ_GPR(a1)
+	GPR_L s11, 13*SZ_GPR(a1)
+
+#if defined(__riscv_flen)
+	FPR_L fs0, 0*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs1, 1*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs2, 2*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs3, 3*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs4, 4*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs5, 5*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs6, 6*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs7, 7*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs8, 8*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs9, 9*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs10, 10*SZ_FPR+14*SZ_GPR(a1)
+	FPR_L fs11, 11*SZ_FPR+14*SZ_GPR(a1)
+#endif
+
+	GPR_L ra, 0*SZ_GPR(a1)
+	GPR_L fp, 2*SZ_GPR(a1)
+	GPR_L a3, 1*SZ_GPR(a1)
+	cfi_def_cfa(a1, 0)
+	mv sp, a3
+	jr ra
+	cfi_endproc
+	.size	GTM_longjmp, . - GTM_longjmp
+
+#ifdef __linux__
+.section .note.GNU-stack, "", @progbits
+#endif
diff --git a/libitm/config/riscv/target.h b/libitm/config/riscv/target.h
new file mode 100644
index 0000000..16ee3f1
--- /dev/null
+++ b/libitm/config/riscv/target.h
@@ -0,0 +1,50 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+namespace GTM HIDDEN {
+
+typedef struct gtm_jmpbuf
+  {
+    long int pc;
+    void *cfa;
+    long int s[12]; /* Saved registers, s0 is fp */
+
+    /* FP saved registers */
+#if defined(__riscv_flen) && __riscv_flen == 64
+    double fs[12];
+#elif defined(__riscv_flen) && __riscv_flen == 32
+    float fs[12];
+#endif
+  } gtm_jmpbuf;
+
+/* ??? The size of one line in hardware caches (in bytes). */
+#define HW_CACHELINE_SIZE 64
+
+static inline void
+cpu_relax (void)
+{
+    __asm__ volatile ("" : : : "memory");
+}
+
+} // namespace GTM
diff --git a/libitm/configure.tgt b/libitm/configure.tgt
index 4c0e78c..635c1d4 100644
--- a/libitm/configure.tgt
+++ b/libitm/configure.tgt
@@ -82,6 +82,8 @@ EOF
 
   loongarch*)   ARCH=loongarch ;;
 
+  riscv*)		ARCH=riscv ;;
+
   sh*)		ARCH=sh ;;
 
   sparc)
-- 
2.38.1

Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

[Jeff Law]

On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote:
> libitm/ChangeLog:
>
>          * configure.tgt: Add riscv support.
>          * config/riscv/asm.h: New file.
>          * config/riscv/sjlj.S: New file.
>          * config/riscv/target.h: New file.
> ---
> v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)
>
>   libitm/config/riscv/asm.h    |  52 +++++++++++++
>   libitm/config/riscv/sjlj.S   | 144 +++++++++++++++++++++++++++++++++++
>   libitm/config/riscv/target.h |  50 ++++++++++++
>   libitm/configure.tgt         |   2 +
>   4 files changed, 248 insertions(+)
>   create mode 100644 libitm/config/riscv/asm.h
>   create mode 100644 libitm/config/riscv/sjlj.S
>   create mode 100644 libitm/config/riscv/target.h

Not objecting or even reviewing....  But hasn't transactional memory 
largely fallen out of favor these days?  Intel has pulled it and I think 
IBM did as well.    Should we be investing in extending libitm at all?


jeff

Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

[Palmer Dabbelt]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 2269 bytes --]

On Thu, 27 Oct 2022 16:05:19 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>
> On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote:
>> libitm/ChangeLog:
>>
>>          * configure.tgt: Add riscv support.
>>          * config/riscv/asm.h: New file.
>>          * config/riscv/sjlj.S: New file.
>>          * config/riscv/target.h: New file.
>> ---
>> v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
>> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)
>>
>>   libitm/config/riscv/asm.h    |  52 +++++++++++++
>>   libitm/config/riscv/sjlj.S   | 144 +++++++++++++++++++++++++++++++++++
>>   libitm/config/riscv/target.h |  50 ++++++++++++
>>   libitm/configure.tgt         |   2 +
>>   4 files changed, 248 insertions(+)
>>   create mode 100644 libitm/config/riscv/asm.h
>>   create mode 100644 libitm/config/riscv/sjlj.S
>>   create mode 100644 libitm/config/riscv/target.h
>
> Not objecting or even reviewing....  But hasn't transactional memory
> largely fallen out of favor these days?  Intel has pulled it and I think
> IBM did as well.    Should we be investing in extending libitm at all?

I think we didn't get the memo: https://github.com/riscv/riscv-isa-manual/pull/906

The code looks fine to me, so

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

though I don't have an opinion on whether libitm should be taking ports 
to new targets, I'd never even heard of it before.

Some minor comments:

> +_ITM_beginTransaction:
> +       cfi_startproc
> +    mv a1, sp
> +       addi sp, sp, -(14*SZ_GPR+12*SZ_FPR)
> +       cfi_adjust_cfa_offset(14*SZ_GPR+12*SZ_FPR)

Many of the ABIs require 16-byte stack alignment.

Also: it doesn't hurt anything to use the extra stack, but we only 
stricly need space for the FPRs if we're going to bother saving them.

> +/* ??? The size of one line in hardware caches (in bytes). */
> +#define HW_CACHELINE_SIZE 64

Maybe we should have a placeholder libc/vdso routine for the cache line 
size?  The specs are sort of just a suggestion for that sort of thing.

> +static inline void
> +cpu_relax (void)
> +{
> +    __asm__ volatile ("" : : : "memory");
> +}

We have Zihintpause now, but that's a pretty minor optimization.

Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

[Xi Ruoyao]

On Thu, 2022-10-27 at 17:44 -0700, Palmer Dabbelt wrote:
> though I don't have an opinion on whether libitm should be taking ports 
> to new targets, I'd never even heard of it before.

I asked this question to myself when I reviewed LoongArch libitm port. 
But I remember one maintainer of Deepin (a distro) has complained that
some packages were depending on libitm (and/or libvtv).

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

[Jeff Law]

On 10/27/22 22:23, Xi Ruoyao via Gcc-patches wrote:
> On Thu, 2022-10-27 at 17:44 -0700, Palmer Dabbelt wrote:
>> though I don't have an opinion on whether libitm should be taking ports
>> to new targets, I'd never even heard of it before.
> I asked this question to myself when I reviewed LoongArch libitm port.
> But I remember one maintainer of Deepin (a distro) has complained that
> some packages were depending on libitm (and/or libvtv).+++

I thought libitm had generic code to work if the target didn't provide 
an implementation.  But looking more closely I see that is not the 
case.  So yea, I guess cobbling together the most straightforward 
implementation as possible makes sense.


Jeff