[PATCH 1/2] Improve do_store_flag for single bit when there is no non-zero bits

[PATCH 1/2] Improve do_store_flag for single bit when there is no non-zero bits

[Andrew Pinski]

In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
turn off the bit tracking part of CCP so we would lose out
what TER was able to do before hand. This moves around the
TER code so that it is used instead of just the nonzerobits.
It also makes it easier to remove the TER part of the code
later on too.

OK? Bootstrapped and tested on x86_64-linux-gnu.

Note it reintroduces PR 110117 (which was accidently fixed after
r14-1534-g908e5ab5c11c). The next patch in series will fix that.

gcc/ChangeLog:

	* expr.cc (do_store_flag): Rearrange the
	TER code so that it overrides the nonzero bits
	info if we had `a & POW2`.
---
 gcc/expr.cc | 28 +++++++++++-----------------
 1 file changed, 11 insertions(+), 17 deletions(-)

diff --git a/gcc/expr.cc b/gcc/expr.cc
index 58f5fe76372..ca008cd453e 100644
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -13164,38 +13164,32 @@ do_store_flag (sepops ops, rtx target, machine_mode mode)
       && (TYPE_PRECISION (ops->type) != 1 || TYPE_UNSIGNED (ops->type)))
     {
       wide_int nz = tree_nonzero_bits (arg0);
+      gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR);
+      /* If the defining statement was (x & POW2), then use that instead of
+	 the non-zero bits.  */
+      if (srcstmt && integer_pow2p (gimple_assign_rhs2 (srcstmt)))
+	{
+	  nz = wi::to_wide (gimple_assign_rhs2 (srcstmt));
+	  arg0 = gimple_assign_rhs1 (srcstmt);
+	}
 
       if (wi::popcount (nz) == 1
 	  && (integer_zerop (arg1)
 	      || wi::to_wide (arg1) == nz))
 	{
-	  tree op0;
-	  int bitnum;
-	  gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR);
-	  /* If the defining statement was (x & POW2), then remove the and
-	     as we are going to add it back. */
-	  if (srcstmt
-	      && integer_pow2p (gimple_assign_rhs2 (srcstmt)))
-	    {
-	      op0 = gimple_assign_rhs1 (srcstmt);
-	      bitnum = tree_log2 (gimple_assign_rhs2 (srcstmt));
-	    }
-	  else
-	    {
-	      op0 = arg0;
-	      bitnum = wi::exact_log2 (nz);
-	    }
+	  int bitnum = wi::exact_log2 (nz);
 	  enum tree_code tcode = EQ_EXPR;
 	  if ((code == NE) ^ !integer_zerop (arg1))
 	    tcode = NE_EXPR;
 
 	  type = lang_hooks.types.type_for_mode (mode, unsignedp);
 	  return expand_single_bit_test (loc, tcode,
-					 op0,
+					 arg0,
 					 bitnum, type, target, mode);
 	}
     }
 
+
   if (! get_subtarget (target)
       || GET_MODE (subtarget) != operand_mode)
     subtarget = 0;
-- 
2.31.1

[PATCH 2/2] Handle const_int in expand_single_bit_test

[Andrew Pinski]

After expanding directly to rtl instead of
creating a tree, we could end up with
a const_int which is not ready to be handled
by extract_bit_field.
So need to the constant folding here instead.

OK? bootstrapped and tested on x86_64-linux-gnu with no regressions.

	PR middle-end/110117

gcc/ChangeLog:

	* expr.cc (expand_single_bit_test): Handle
	const_int from expand_expr.

gcc/testsuite/ChangeLog:

	* gcc.dg/pr110117-1.c: New test.
	* gcc.dg/pr110117-2.c: New test.
---
 gcc/expr.cc                       | 10 +++++++---
 gcc/testsuite/gcc.dg/pr110117-1.c | 31 +++++++++++++++++++++++++++++++
 gcc/testsuite/gcc.dg/pr110117-2.c |  7 +++++++
 3 files changed, 45 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/pr110117-1.c
 create mode 100644 gcc/testsuite/gcc.dg/pr110117-2.c

diff --git a/gcc/expr.cc b/gcc/expr.cc
index ca008cd453e..868d812eb1a 100644
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -12958,12 +12958,16 @@ expand_single_bit_test (location_t loc, enum tree_code code,
 
   rtx inner0 = expand_expr (inner, NULL_RTX, VOIDmode, EXPAND_NORMAL);
 
+  if (CONST_SCALAR_INT_P (inner0))
+    {
+      wide_int t = rtx_mode_t (inner0, operand_mode);
+      bool setp = (wi::lrshift(t, bitnum) & 1) != 0;
+      return (setp ^ (code == EQ_EXPR)) ? const1_rtx : const0_rtx;
+    }
   int bitpos = bitnum;
 
-  scalar_int_mode imode = as_a <scalar_int_mode>(GET_MODE (inner0));
-
   if (BYTES_BIG_ENDIAN)
-    bitpos = GET_MODE_BITSIZE (imode) - 1 - bitpos;
+    bitpos = GET_MODE_BITSIZE (operand_mode) - 1 - bitpos;
 
   inner0 = extract_bit_field (inner0, 1, bitpos, 1, target,
 			      operand_mode, mode, 0, NULL);
diff --git a/gcc/testsuite/gcc.dg/pr110117-1.c b/gcc/testsuite/gcc.dg/pr110117-1.c
new file mode 100644
index 00000000000..fd9a9e3268e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr110117-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -ftree-vrp -fno-tree-ccp -fno-tree-forwprop" } */
+int a, b, d;
+unsigned c;
+int main() {
+  char e = -10;
+  int f = 1, g = 0;
+  if (a) {
+    char h = e;
+  i:
+    c = ~h - (-g & f || e);
+    int j = b % c;
+    g = j % 9;
+    if (c) {
+      if (d)
+        e = 0;
+      while (!g)
+        ;
+      int k = 0;
+    l:
+      if (k)
+        goto i;
+    }
+  }
+  if (e > -10) {
+    if (g)
+      f = 0;
+    goto l;
+  }
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/pr110117-2.c b/gcc/testsuite/gcc.dg/pr110117-2.c
new file mode 100644
index 00000000000..2e353258084
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr110117-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -fno-tree-dominator-opts -fno-tree-vrp -fno-tree-ccp -fno-tree-forwprop -fno-tree-fre -fno-tree-copy-prop" } */
+int f()
+{
+  int t = 0;
+  return (t & 1) != 0;
+}
-- 
2.31.1

Re: [PATCH 1/2] Improve do_store_flag for single bit when there is no non-zero bits

[Jeff Law]

On 6/4/23 23:53, Andrew Pinski via Gcc-patches wrote:
> In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
> turn off the bit tracking part of CCP so we would lose out
> what TER was able to do before hand. This moves around the
> TER code so that it is used instead of just the nonzerobits.
> It also makes it easier to remove the TER part of the code
> later on too.
Given that we want to kill TER, that seems like a good idea :-)

> 
> OK? Bootstrapped and tested on x86_64-linux-gnu.
> 
> Note it reintroduces PR 110117 (which was accidently fixed after
> r14-1534-g908e5ab5c11c). The next patch in series will fix that.
> 
> gcc/ChangeLog:
> 
> 	* expr.cc (do_store_flag): Rearrange the
> 	TER code so that it overrides the nonzero bits
> 	info if we had `a & POW2`.
OK.
jeff

Re: [PATCH 2/2] Handle const_int in expand_single_bit_test

[Jeff Law]

On 6/4/23 23:53, Andrew Pinski via Gcc-patches wrote:
> After expanding directly to rtl instead of
> creating a tree, we could end up with
> a const_int which is not ready to be handled
> by extract_bit_field.
> So need to the constant folding here instead.
> 
> OK? bootstrapped and tested on x86_64-linux-gnu with no regressions.
> 
> 	PR middle-end/110117
> 
> gcc/ChangeLog:
> 
> 	* expr.cc (expand_single_bit_test): Handle
> 	const_int from expand_expr.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.dg/pr110117-1.c: New test.
> 	* gcc.dg/pr110117-2.c: New test.
> ---
>   gcc/expr.cc                       | 10 +++++++---
>   gcc/testsuite/gcc.dg/pr110117-1.c | 31 +++++++++++++++++++++++++++++++
>   gcc/testsuite/gcc.dg/pr110117-2.c |  7 +++++++
>   3 files changed, 45 insertions(+), 3 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.dg/pr110117-1.c
>   create mode 100644 gcc/testsuite/gcc.dg/pr110117-2.c
> 
> diff --git a/gcc/expr.cc b/gcc/expr.cc
> index ca008cd453e..868d812eb1a 100644
> --- a/gcc/expr.cc
> +++ b/gcc/expr.cc
> @@ -12958,12 +12958,16 @@ expand_single_bit_test (location_t loc, enum tree_code code,
>   
>     rtx inner0 = expand_expr (inner, NULL_RTX, VOIDmode, EXPAND_NORMAL);
>   
> +  if (CONST_SCALAR_INT_P (inner0))
> +    {
> +      wide_int t = rtx_mode_t (inner0, operand_mode);
> +      bool setp = (wi::lrshift(t, bitnum) & 1) != 0;
Formatting nit.  Space before the open paren for wi::lrshift's args.

OK with that change.
jeff