Re: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1

[钟居哲 <juzhe.zhong@rivai.ai>]

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I think the revert patch exposes latent bug, Li Pan will look into it.



juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2024-04-23 03:55
To: pan2.li; gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc
Subject: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1
Hi Pan,
 
I was running the testsuite for this and noticed an ICE scroll by when 
this patch is applied to cacc55a4c0be8d0bc7417b6a28924eadbbe428e3 for 
rv64gcv:
 
FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  (internal 
compiler error: in extract_insn, at recog.cc:2812)
 
I'll send the full list of new failures once the runs finish.
 
Thanks,
Patrick
 
On 4/22/24 06:47, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> After we reverted below 2 commits, the reference to attr need some
> adjustment as the group_overlap is no longer available.
>
> * RISC-V: Robostify the W43, W86, W87 constraint enabled attribute
> * RISC-V: Rename vconstraint into group_overlap
>
> The below tests are passed for this patch.
>
> * The rv64gcv fully regression tests.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md:
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>   gcc/config/riscv/vector-crypto.md | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
> index 519c6a10d94..23dc549e5b8 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -322,7 +322,7 @@ (define_insn "@pred_vwsll<mode>_scalar"
>     "vwsll.v%o4\t%0,%3,%4%p1"
>     [(set_attr "type" "vwsll")
>      (set_attr "mode" "<V_DOUBLE_TRUNC>")
> -   (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
> +   (set_attr "vconstraint" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,no,no")])
>   
>   ;; vbrev.v vbrev8.v vrev8.v
>   (define_insn "@pred_v<rev><mode>"