* [PATCH] RISC-V: Reorder VSETVL PASS location
@ 2023-01-18 3:03 juzhe.zhong
2023-01-22 19:36 ` Jeff Law
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-01-18 3:03 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder VSETVL PASS.
---
gcc/config/riscv/riscv-passes.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-passes.def b/gcc/config/riscv/riscv-passes.def
index d2d48f231aa..614b767dc8a 100644
--- a/gcc/config/riscv/riscv-passes.def
+++ b/gcc/config/riscv/riscv-passes.def
@@ -18,4 +18,4 @@
<http://www.gnu.org/licenses/>. */
INSERT_PASS_AFTER (pass_rtl_store_motion, 1, pass_shorten_memrefs);
-INSERT_PASS_BEFORE (pass_sched2, 1, pass_vsetvl);
+INSERT_PASS_BEFORE (pass_fast_rtl_dce, 1, pass_vsetvl);
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Reorder VSETVL PASS location
2023-01-18 3:03 [PATCH] RISC-V: Reorder VSETVL PASS location juzhe.zhong
@ 2023-01-22 19:36 ` Jeff Law
2023-01-27 9:40 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: Jeff Law @ 2023-01-22 19:36 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, palmer
On 1/17/23 20:03, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder VSETVL PASS.
It'd be useful to know the motivation here, I could easily see someone
in the future finding a case where the location of the vsetvl gets
influenced by some dead code that would have been removed by the DCE
pass. Then they're going to want to know the motivation behind the
current pass placement.
So, OK after adding a comment describing why the pass is placed where it is.
Jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Reorder VSETVL PASS location
2023-01-22 19:36 ` Jeff Law
@ 2023-01-27 9:40 ` Kito Cheng
0 siblings, 0 replies; 3+ messages in thread
From: Kito Cheng @ 2023-01-27 9:40 UTC (permalink / raw)
To: Jeff Law; +Cc: juzhe.zhong, gcc-patches, palmer
[-- Attachment #1: Type: text/plain, Size: 735 bytes --]
Added more comments and committed, thanks!
On Mon, Jan 23, 2023 at 3:36 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 1/17/23 20:03, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder
> VSETVL PASS.
> It'd be useful to know the motivation here, I could easily see someone
> in the future finding a case where the location of the vsetvl gets
> influenced by some dead code that would have been removed by the DCE
> pass. Then they're going to want to know the motivation behind the
> current pass placement.
>
> So, OK after adding a comment describing why the pass is placed where it
> is.
>
> Jeff
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-01-27 9:41 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2023-01-18 3:03 [PATCH] RISC-V: Reorder VSETVL PASS location juzhe.zhong
2023-01-22 19:36 ` Jeff Law
2023-01-27 9:40 ` Kito Cheng
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