[PATCH 0/3] [RISCV] Improve bswap for ZBB

[PATCH 0/3] [RISCV] Improve bswap for ZBB

[apinski]

From: Andrew Pinski <apinski@marvell.com>

Just some improvements for bswap and ZBB including a testsuite change that will
allow more testing to happen.

Thanks,
Andrew Pinski


Andrew Pinski (3):
  Fix PR 106600: __builtin_bswap32 is not hooked up for ZBB for 32bit
  Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB
    enabled
  Fix PR 106690: enable effective_target_bswap for RISCV targets with
    ZBB enabled by default

 gcc/config/riscv/bitmanip.md                  | 26 ++++++++++++++++++-
 .../gcc.target/riscv/zbb_32_bswap-1.c         | 11 ++++++++
 .../gcc.target/riscv/zbb_32_bswap-2.c         | 12 +++++++++
 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c  | 11 ++++++++
 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c  | 12 +++++++++
 gcc/testsuite/lib/target-supports.exp         |  7 +++++
 6 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c

-- 
2.17.1

[PATCH 1/3] Fix PR 106600: __builtin_bswap32 is not hooked up for ZBB for 32bit

[apinski]

From: Andrew Pinski <apinski@marvell.com>

The problem here is the bswap<mode>2 pattern had a check for TARGET_64BIT
but then used the X iterator. Since the X iterator is either SI or DI depending
on the setting TARGET_64BIT, there is no reason for the TARGET_64BIT.

OK? Built and tested on both riscv32-linux-gnu and riscv64-linux-gnu.

Thanks,
Andrew Pinski

gcc/ChangeLog:

	PR target/106600
	* config/riscv/bitmanip.md (bswap<mode>2): Remove
	condition on TARGET_64BIT as X is already conditional there.

gcc/testsuite/ChangeLog:

	PR target/106600
	* gcc.target/riscv/zbb_32_bswap-1.c: New test.
	* gcc.target/riscv/zbb_bswap-1.c: New test.

Change-Id: Iba3187e5620b0f291f7c38aab597f367b47a22c5
---
 gcc/config/riscv/bitmanip.md                    |  2 +-
 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c | 11 +++++++++++
 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c    | 11 +++++++++++
 3 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d1570ce8508..c7ba667f87a 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -272,7 +272,7 @@ (define_insn "rotlsi3_sext"
 (define_insn "bswap<mode>2"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bswap:X (match_operand:X 1 "register_operand" "r")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_ZBB"
   "rev8\t%0,%1"
   [(set_attr "type" "bitmanip")])
 
diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
new file mode 100644
index 00000000000..3ff7d9de409
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+  return __builtin_bswap32(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c
new file mode 100644
index 00000000000..20feded0df2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+  return __builtin_bswap32(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+
-- 
2.17.1

[PATCH 2/3] Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled

[apinski]

From: Andrew Pinski <apinski@marvell.com>

The default expansion for bswap16 is two extractions (shift/and)
followed by an insertation (ior) and then a zero extend. This can be improved
with ZBB enabled to just full byteswap followed by a (logical) shift right.
This patch adds a new pattern for this which does that.

OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu.

gcc/ChangeLog:

	PR target/106601
	* config/riscv/bitmanip.md (bswaphi2): New pattern.

gcc/testsuite/ChangeLog:

	PR target/106601
	* gcc.target/riscv/zbb_32_bswap-2.c: New test.
	* gcc.target/riscv/zbb_bswap-2.c: New test.

Change-Id: If61362c14664cf8685da17779217033689878f86
---
 gcc/config/riscv/bitmanip.md                  | 24 +++++++++++++++++++
 .../gcc.target/riscv/zbb_32_bswap-2.c         | 12 ++++++++++
 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c  | 12 ++++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index c7ba667f87a..c4383285d81 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -276,6 +276,30 @@ (define_insn "bswap<mode>2"
   "rev8\t%0,%1"
   [(set_attr "type" "bitmanip")])
 
+;; HI bswap can be emulated using SI/DI bswap followed
+;; by a logical shift right
+;; SI bswap for TARGET_64BIT is already similarly in
+;; the common code.
+(define_expand "bswaphi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+        (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
+  "TARGET_ZBB"
+{
+  rtx tmp = gen_reg_rtx (word_mode);
+  rtx newop1 = gen_lowpart (word_mode, operands[1]);
+  if (TARGET_64BIT)
+    emit_insn (gen_bswapdi2 (tmp, newop1));
+  else
+    emit_insn (gen_bswapsi2 (tmp, newop1));
+  rtx tmp1 = gen_reg_rtx (word_mode);
+  if (TARGET_64BIT)
+    emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16)));
+  else
+    emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16)));
+  emit_move_insn (operands[0], gen_lowpart (HImode, tmp1));
+  DONE;
+})
+
 (define_insn "<bitmanip_optab><mode>3"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
new file mode 100644
index 00000000000..679b34c4e41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+  return __builtin_bswap16(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+/* { dg-final { scan-assembler "srli" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
new file mode 100644
index 00000000000..c358f6683f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+  return __builtin_bswap16(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+/* { dg-final { scan-assembler "srli" } } */
+
-- 
2.17.1

[PATCH 3/3] Fix PR 106690: enable effective_target_bswap for RISCV targets with ZBB enabled by default

[apinski]

From: Andrew Pinski <apinski@marvell.com>

While looking for testcases to quickly test, I Noticed that
check_effective_target_bswap was not enabled for riscv when
ZBB is enabled. This patch checks if ZBB is enabled when
targeting RISCV* for bswap.

OK? Ran the testsuite for riscv32-linux-gnu both with and without ZBB enabled.

PR testsuite/106690
gcc/testsuite/ChangeLog:

	* lib/target-supports.exp (check_effective_target_bswap):
	Return true if riscv and ZBB ISA extension is enabled.

Change-Id: I521c91e7fc1a54faa0c8399b685248690022278b
---
 gcc/testsuite/lib/target-supports.exp | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 04a2a8e8659..0f1e1af31e9 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8646,6 +8646,13 @@ proc check_effective_target_bswap { } {
 	     || [istarget powerpc*-*-*]
 	     || [istarget rs6000-*-*]
 	     || [istarget s390*-*-*]
+	     || ([istarget riscv*-*-*]
+	         && [check_no_compiler_messages_nocache riscv_zbb object {
+		     #if __riscv_zbb  <= 0
+		     #error ZBB is not enabled
+		     #endif
+		     int i;
+		 } ""])
 	     || ([istarget arm*-*-*]
 		 && [check_no_compiler_messages_nocache arm_v6_or_later object {
 		     #if __ARM_ARCH < 6
-- 
2.17.1

Re: [PATCH 0/3] [RISCV] Improve bswap for ZBB

[Kito Cheng]

Hi Andrew:

LGTM, Just checked what's clang gen, and saw LLVM already did the same
optimization, thanks for improving the code gen!


On Sun, Aug 21, 2022 at 1:15 AM apinski--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Andrew Pinski <apinski@marvell.com>
>
> Just some improvements for bswap and ZBB including a testsuite change that will
> allow more testing to happen.
>
> Thanks,
> Andrew Pinski
>
>
> Andrew Pinski (3):
>   Fix PR 106600: __builtin_bswap32 is not hooked up for ZBB for 32bit
>   Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB
>     enabled
>   Fix PR 106690: enable effective_target_bswap for RISCV targets with
>     ZBB enabled by default
>
>  gcc/config/riscv/bitmanip.md                  | 26 ++++++++++++++++++-
>  .../gcc.target/riscv/zbb_32_bswap-1.c         | 11 ++++++++
>  .../gcc.target/riscv/zbb_32_bswap-2.c         | 12 +++++++++
>  gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c  | 11 ++++++++
>  gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c  | 12 +++++++++
>  gcc/testsuite/lib/target-supports.exp         |  7 +++++
>  6 files changed, 78 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
>
> --
> 2.17.1
>