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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Alexander Monakov <amonakov@ispras.ru>
Cc: gcc-patches@gcc.gnu.org, Vineet Gupta <vineetg@rivosinc.com>,
	 Kito Cheng <kito.cheng@gmail.com>,
	Jojo R <rjiejie@linux.alibaba.com>,
	 Jeff Law <jlaw@ventanamicro.com>
Subject: Re: [PATCH] riscv: implement TARGET_MODE_REP_EXTENDED
Date: Wed, 9 Nov 2022 00:45:48 +0100	[thread overview]
Message-ID: <CAAeLtUCESGy=xZVjPP5wvFA2RqKChc4LHib3xXOGrmhVde8R=Q@mail.gmail.com> (raw)
In-Reply-To: <4bc6d821-21d3-764c-269a-8f822257dd33@ispras.ru>

On Mon, 7 Nov 2022 at 14:55, Alexander Monakov <amonakov@ispras.ru> wrote:
>
>
>
> On Sat, 5 Nov 2022, Philipp Tomsich wrote:
>
> > Alexander,
> >
> > I had missed your comment until now.
>
> Please make sure to read replies from Jeff and Palmer as well (their responses
> went to gcc-patches with empty Cc list):
> https://inbox.sourceware.org/gcc-patches/ba895f78-7f47-0f4-5bfe-e21893c4bcb@ispras.ru/T/#m7b7e5708b82de3b05ba8007ae6544891a03bdc42
>
> For now let me respond to some of the more prominent points:
>
> > > I think this leads to a counter-intuitive requirement that a hand-written
> > > inline asm must sign-extend its output operands that are bound to either
> > > signed or unsigned 32-bit lvalues. Will compiler users be aware of that?
> >
> > I am not sure if I fully understand your concern, as the mode of the
> > asm-output will be derived from the variable type.
> > So "asm (... : "=r" (a))" will take DI/SI/HI/QImode depending on the type
> > of a.
>
> Yes. The problem arises when 'a' later undergoes conversion to a wider type.
>
> > The concern, as far as I understand would be the case where the
> > assembly-sequence leaves an incompatible extension in the register.
>
> Existing documentation like the psABI does not constrain compiler users in any
> way, so their inline asm snippets are free to leave garbage in upper bits. Thus
> there's no "incompatibility" to speak of.
>
> To give a specific example that will be problematic if you go far enough down
> the road of matching MIPS64 behavior:
>
> long f(void)
> {
>     int x;
>     asm("" : "=r"(x));
>     return x;
> }
>
> here GCC (unlike LLVM) omits sign extension of 'x', assuming that asm output
> must have been sign-extended to 64 bits by the programmer.

In fact, with the proposed patch (but also without it), GCC will sign-extend:
f:
  sext.w a0,a0
  ret
  .size f, .-f

To make sure that this is not just an extension to promote the int to
long for the function return, I next added another empty asm to
consume 'x'.
This clearly shows that the extension is performed to postprocess the
output of the asm-statement:

f:
  # ./asm2.c:4:     asm("" : "=r"(x));
  sext.w a0,a0 # x, x
  # ./asm2.c:5:     asm("" : : "r"(x));
  # ./asm2.c:7: }
  ret

Thanks,
Philipp.

  reply	other threads:[~2022-11-08 23:46 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-05 21:44 Philipp Tomsich
2022-09-06 11:39 ` Alexander Monakov
2022-09-16 23:48   ` Jeff Law
2022-09-17  7:59     ` Palmer Dabbelt
2022-11-04 23:00   ` Philipp Tomsich
2022-11-05  6:16     ` [PATCH] [PHIOPT] Add A ? B + CST : B match and simplify optimizations Zhongyunde
2022-11-05  6:34       ` Andrew Pinski
2022-11-05  9:03         ` Zhongyunde
2022-11-08 14:58           ` Richard Biener
2022-11-08 15:51             ` 钟云德
2022-11-09  8:00               ` Richard Biener
2022-11-07 13:55     ` [PATCH] riscv: implement TARGET_MODE_REP_EXTENDED Alexander Monakov
2022-11-08 23:45       ` Philipp Tomsich [this message]
2022-11-09 17:21         ` Alexander Monakov
2022-11-20 16:09     ` Jeff Law
2022-11-21 13:49       ` Alexander Monakov
2022-11-21 14:56         ` Jeff Law
2022-11-21 15:33           ` Alexander Monakov

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