Re: [x86 PATCH] PR target/31985: Improve memory operand use with doubleword add.

[Uros Bizjak <ubizjak@gmail.com>]

On Fri, Jun 16, 2023 at 12:04 AM Roger Sayle <roger@nextmovesoftware.com> wrote:
>
>
> Hi Uros,
>
> > On the 7th June 2023, Uros Bizkak wrote:
> > The register allocator considers the instruction-to-be-split as one instruction, so it
> > can allocate output register to match an input register (or a register that forms an
> > input address), So, you have to either add an early clobber to the output, or
> > somehow prevent output to clobber registers in the second pattern.
>
> This implements your suggestion of adding an early clobber to the output, a
> one character ('&') change from the previous version of this patch.  Retested
> with make bootstrap and make -k check, with and without -m32, to confirm
> there are no issues, and this still fixes the pr31985.c test case.
>
> As you've suggested, I'm also working on improving STV in this area.
>
> Ok for mainline?
>
>
> 2023-06-15  Roger Sayle  <roger@nextmovesoftware.com>
>             Uros Bizjak  <ubizjak@gmail.com>
>
> gcc/ChangeLog
>         PR target/31985
>         * config/i386/i386.md (*add<dwi>3_doubleword_concat): New
>         define_insn_and_split combine *add<dwi>3_doubleword with a
>         *concat<mode><dwi>3 for more efficient lowering after reload.
>
> gcc/testsuite/ChangeLog
>         PR target/31985
>         * gcc.target/i386/pr31985.c: New test case.

OK with a small change below.

Thanks,
Uros.

+(define_insn_and_split "*add<dwi>3_doubleword_concat"
+  [(set (match_operand:<DWI> 0 "register_operand" "=&r")
+ (plus:<DWI>
+  (any_or_plus:<DWI>
+    (ashift:<DWI>
+      (zero_extend:<DWI>
+ (match_operand:DWIH 2 "nonimmediate_operand" "rm"))
+      (match_operand:<DWI> 3 "const_int_operand"))

The above mode should be QImode, all shifts have QImode on x86.

+    (zero_extend:<DWI>
+      (match_operand:DWIH 4 "nonimmediate_operand" "rm")))
+  (match_operand:<DWI> 1 "register_operand" "0")))
+   (clobber (reg:CC FLAGS_REG))]
+  "INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
+  "#"
+  "&& reload_completed"
+  [(parallel [(set (reg:CCC FLAGS_REG)
+   (compare:CCC
+     (plus:DWIH (match_dup 1) (match_dup 4))
+     (match_dup 1)))
+      (set (match_dup 0)
+   (plus:DWIH (match_dup 1) (match_dup 4)))])
+   (parallel [(set (match_dup 5)
+   (plus:DWIH
+     (plus:DWIH
+       (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+       (match_dup 6))
+     (match_dup 2)))
+      (clobber (reg:CC FLAGS_REG))])]
+ "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[5]);")
+

> Roger
> --
>