* [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
@ 2023-03-27 11:04 Christoph Muellner
2023-03-27 11:55 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: Christoph Muellner @ 2023-03-27 11:04 UTC (permalink / raw)
To: gcc-patches, Kito Cheng, Jim Wilson, Palmer Dabbelt,
Andrew Waterman, Philipp Tomsich, JuzheZhong, Jojo R
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds missing mode specifiers for XTheadMemPair INSNs.
gcc/ChangeLog:
PR target/109296
* config/riscv/thead.md: Add missing mode specifiers.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/thead.md | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 63c4af6f77d..0623607d3dc 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -321,10 +321,10 @@ (define_insn "*th_mempair_store_<GPR:mode>2"
;; MEMPAIR load DI extended signed SI
(define_insn "*th_mempair_load_extendsidi2"
- [(set (match_operand 0 "register_operand" "=r")
- (sign_extend:DI (match_operand 1 "memory_operand" "m")))
- (set (match_operand 2 "register_operand" "=r")
- (sign_extend:DI (match_operand 3 "memory_operand" "m")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI (match_operand:SI 1 "memory_operand" "m")))
+ (set (match_operand:DI 2 "register_operand" "=r")
+ (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
"TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
&& th_mempair_operands_p (operands, true, SImode)"
{ return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
@@ -334,10 +334,10 @@ (define_insn "*th_mempair_load_extendsidi2"
;; MEMPAIR load DI extended unsigned SI
(define_insn "*th_mempair_load_zero_extendsidi2"
- [(set (match_operand 0 "register_operand" "=r")
- (zero_extend:DI (match_operand 1 "memory_operand" "m")))
- (set (match_operand 2 "register_operand" "=r")
- (zero_extend:DI (match_operand 3 "memory_operand" "m")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:SI 1 "memory_operand" "m")))
+ (set (match_operand:DI 2 "register_operand" "=r")
+ (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
"TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
&& th_mempair_operands_p (operands, true, SImode)"
{ return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
--
2.39.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
2023-03-27 11:04 [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair Christoph Muellner
@ 2023-03-27 11:55 ` Kito Cheng
2023-03-27 12:19 ` Philipp Tomsich
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2023-03-27 11:55 UTC (permalink / raw)
To: Christoph Muellner
Cc: gcc-patches, Jim Wilson, Palmer Dabbelt, Andrew Waterman,
Philipp Tomsich, JuzheZhong, Jojo R
[-- Attachment #1: Type: text/plain, Size: 2490 bytes --]
OK for trunk, thanks :)
On Mon, Mar 27, 2023 at 7:04 PM Christoph Muellner <
christoph.muellner@vrull.eu> wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This patch adds missing mode specifiers for XTheadMemPair INSNs.
>
> gcc/ChangeLog:
> PR target/109296
> * config/riscv/thead.md: Add missing mode specifiers.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> gcc/config/riscv/thead.md | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 63c4af6f77d..0623607d3dc 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -321,10 +321,10 @@ (define_insn "*th_mempair_store_<GPR:mode>2"
>
> ;; MEMPAIR load DI extended signed SI
> (define_insn "*th_mempair_load_extendsidi2"
> - [(set (match_operand 0 "register_operand" "=r")
> - (sign_extend:DI (match_operand 1 "memory_operand" "m")))
> - (set (match_operand 2 "register_operand" "=r")
> - (sign_extend:DI (match_operand 3 "memory_operand" "m")))]
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (sign_extend:DI (match_operand:SI 1 "memory_operand" "m")))
> + (set (match_operand:DI 2 "register_operand" "=r")
> + (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
> && th_mempair_operands_p (operands, true, SImode)"
> { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
> @@ -334,10 +334,10 @@ (define_insn "*th_mempair_load_extendsidi2"
>
> ;; MEMPAIR load DI extended unsigned SI
> (define_insn "*th_mempair_load_zero_extendsidi2"
> - [(set (match_operand 0 "register_operand" "=r")
> - (zero_extend:DI (match_operand 1 "memory_operand" "m")))
> - (set (match_operand 2 "register_operand" "=r")
> - (zero_extend:DI (match_operand 3 "memory_operand" "m")))]
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (zero_extend:DI (match_operand:SI 1 "memory_operand" "m")))
> + (set (match_operand:DI 2 "register_operand" "=r")
> + (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
> && th_mempair_operands_p (operands, true, SImode)"
> { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
> --
> 2.39.2
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
2023-03-27 11:55 ` Kito Cheng
@ 2023-03-27 12:19 ` Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2023-03-27 12:19 UTC (permalink / raw)
To: Kito Cheng
Cc: Christoph Muellner, gcc-patches, Jim Wilson, Palmer Dabbelt,
Andrew Waterman, JuzheZhong, Jojo R
Applied to master, thanks!
Philipp.
On Mon, 27 Mar 2023 at 19:55, Kito Cheng <kito.cheng@sifive.com> wrote:
>
> OK for trunk, thanks :)
>
> On Mon, Mar 27, 2023 at 7:04 PM Christoph Muellner <christoph.muellner@vrull.eu> wrote:
>>
>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>>
>> This patch adds missing mode specifiers for XTheadMemPair INSNs.
>>
>> gcc/ChangeLog:
>> PR target/109296
>> * config/riscv/thead.md: Add missing mode specifiers.
>>
>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>> ---
>> gcc/config/riscv/thead.md | 16 ++++++++--------
>> 1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
>> index 63c4af6f77d..0623607d3dc 100644
>> --- a/gcc/config/riscv/thead.md
>> +++ b/gcc/config/riscv/thead.md
>> @@ -321,10 +321,10 @@ (define_insn "*th_mempair_store_<GPR:mode>2"
>>
>> ;; MEMPAIR load DI extended signed SI
>> (define_insn "*th_mempair_load_extendsidi2"
>> - [(set (match_operand 0 "register_operand" "=r")
>> - (sign_extend:DI (match_operand 1 "memory_operand" "m")))
>> - (set (match_operand 2 "register_operand" "=r")
>> - (sign_extend:DI (match_operand 3 "memory_operand" "m")))]
>> + [(set (match_operand:DI 0 "register_operand" "=r")
>> + (sign_extend:DI (match_operand:SI 1 "memory_operand" "m")))
>> + (set (match_operand:DI 2 "register_operand" "=r")
>> + (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
>> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
>> && th_mempair_operands_p (operands, true, SImode)"
>> { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
>> @@ -334,10 +334,10 @@ (define_insn "*th_mempair_load_extendsidi2"
>>
>> ;; MEMPAIR load DI extended unsigned SI
>> (define_insn "*th_mempair_load_zero_extendsidi2"
>> - [(set (match_operand 0 "register_operand" "=r")
>> - (zero_extend:DI (match_operand 1 "memory_operand" "m")))
>> - (set (match_operand 2 "register_operand" "=r")
>> - (zero_extend:DI (match_operand 3 "memory_operand" "m")))]
>> + [(set (match_operand:DI 0 "register_operand" "=r")
>> + (zero_extend:DI (match_operand:SI 1 "memory_operand" "m")))
>> + (set (match_operand:DI 2 "register_operand" "=r")
>> + (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
>> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
>> && th_mempair_operands_p (operands, true, SImode)"
>> { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-03-27 11:04 [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair Christoph Muellner
2023-03-27 11:55 ` Kito Cheng
2023-03-27 12:19 ` Philipp Tomsich
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