public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
From: Hongtao Liu <crazylht@gmail.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: liuhongt <hongtao.liu@intel.com>,
	 "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] Extend 64-bit vector bit_op patterns with ?r alternative
Date: Thu, 14 Jul 2022 17:32:43 +0800	[thread overview]
Message-ID: <CAMZc-bxn9qW-ph9MUS=WXyb1TeGx_48h-A7x+mFvkuP4TqUQ6g@mail.gmail.com> (raw)
In-Reply-To: <CAFULd4YSZW+Qu3vUBY=wj3_VP33XZXreXVAz2_s-TOdwaMh1bw@mail.gmail.com>

On Thu, Jul 14, 2022 at 3:22 PM Uros Bizjak via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> On Thu, Jul 14, 2022 at 7:33 AM liuhongt <hongtao.liu@intel.com> wrote:
> >
> > And split it to GPR-version instruction after reload.
> >
> > > ?r was introduced under the assumption that we want vector values
> > > mostly in vector registers. Currently there are no instructions with
> > > memory or immediate operand, so that made sense at the time. Let's
> > > keep ?r until logic instructions with mem/imm operands are introduced.
> > > So, for the patch that adds 64-bit vector logic in GPR, I would advise
> > > to first introduce only register operands. mem/imm operands should be
> > Update patch to add ?r to 64-bit bit_op patterns.
> >
> > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> > No big imact on SPEC2017(Most same binary).
>
> The problem with your approach is with the combine pass, where combine
> first tries to recognize the combined instruction without clobber,
> before re-recognizing instruction with added clobber. So, if a forward
> propagation happens, the combine will *always* choose the insn variant
> without GPR.
Thank you for the explanation, I really did not know this point.
>
> So, the solution with VI_16_32 is to always expand with a clobbered
> version that is split to either SImode or V16QImode. With 64-bit
> instructions, we have two additional complications. First, we have a
> native MMX instruction, and we have to split to it after reload, and
> second, we have a builtin that expects vector insn.
>
> To solve the first issue, we should change the mode of
> "*mmx<code><mode>" to V1DImode and split your new _gpr version with
> clobber to it for !GENERAL_REG_P operands.
>
> The second issue could be solved by emitting V1DImode instructions
> directly from the expander. Please note there are several expanders
> that expect non-clobbered logic insn in certain mode to be available,
> so the situation can become quite annoying...
Yes. It looks like it would add a lot of code complexity, I'll hold
the patch for now.
>
> Uros.



-- 
BR,
Hongtao

  reply	other threads:[~2022-07-14  9:32 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-11  1:15 [PATCH] Allocate general register(memory/immediate) for 16/32/64-bit vector bit_op patterns liuhongt
2022-07-11  8:02 ` Uros Bizjak
2022-07-12  6:37   ` Hongtao Liu
2022-07-12  7:15     ` Uros Bizjak
2022-07-14  5:33       ` [PATCH] Extend 64-bit vector bit_op patterns with ?r alternative liuhongt
2022-07-14  7:22         ` Uros Bizjak
2022-07-14  9:32           ` Hongtao Liu [this message]
2022-07-14  9:46             ` Uros Bizjak
2022-07-18  1:59               ` [PATCH] Extend 16/32-bit vector bit_op patterns with (m, 0, i)(vertical) alternative liuhongt
2022-07-18  6:28                 ` [PATCH] Extend 16/32-bit vector bit_op patterns with (m,0,i)(vertical) alternative Uros Bizjak
2022-07-19  6:07                   ` [PATCH V2] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative liuhongt
2022-07-19  6:34                     ` Uros Bizjak
2022-07-19  6:56                       ` Hongtao Liu
2022-07-19  9:37                         ` Uros Bizjak
2022-07-20  2:37                           ` Hongtao Liu
2022-07-20  6:14                             ` Uros Bizjak
2022-07-20  6:18                               ` Uros Bizjak
2022-07-20  6:54                                 ` Hongtao Liu
2022-07-20  7:18                                   ` Uros Bizjak
2022-07-20  7:22                                     ` Hongtao Liu
2022-07-21  5:18                                       ` [PATCH V3] " liuhongt
2022-07-21  5:55                                         ` Uros Bizjak

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAMZc-bxn9qW-ph9MUS=WXyb1TeGx_48h-A7x+mFvkuP4TqUQ6g@mail.gmail.com' \
    --to=crazylht@gmail.com \
    --cc=gcc-patches@gcc.gnu.org \
    --cc=hongtao.liu@intel.com \
    --cc=ubizjak@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).