From: Uros Bizjak <ubizjak@gmail.com>
To: liuhongt <hongtao.liu@intel.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH V3] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative.
Date: Thu, 21 Jul 2022 07:55:06 +0200 [thread overview]
Message-ID: <CAFULd4ZpmSrsBGa6Vt1LscP_Jm09HPgrA6FgTVqV9eORdhJR_g@mail.gmail.com> (raw)
In-Reply-To: <20220721051841.13832-1-hongtao.liu@intel.com>
On Thu, Jul 21, 2022 at 7:19 AM liuhongt <hongtao.liu@intel.com> wrote:
>
> And split it after reload.
>
> gcc/ChangeLog:
>
> PR target/106038
> * config/i386/mmx.md (<code><mode>3): New define_expand, it's
> original "<code><mode>3".
> (*<code><mode>3): New define_insn, it's original
> "<code><mode>3" be extended to handle memory and immediate
> operand with ix86_binary_operator_ok. Also adjust define_split
> after it.
> (mmxinsnmode): New mode attribute.
> (*mov<mode>_imm): Refactor with mmxinsnmode.
> * config/i386/predicates.md
> (register_or_x86_64_const_vector_operand): New predicate.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr106038-1.c: New test.
OK.
Thanks,
Uros.
> ---
> gcc/config/i386/mmx.md | 70 ++++++++++++----------
> gcc/config/i386/predicates.md | 4 ++
> gcc/testsuite/gcc.target/i386/pr106038-1.c | 27 +++++++++
> 3 files changed, 70 insertions(+), 31 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr106038-1.c
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index 3294c1e6274..dda4b43f5c1 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -86,6 +86,14 @@ (define_mode_attr mmxvecsize
> [(V8QI "b") (V4QI "b") (V2QI "b")
> (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")])
>
> +;; Mapping to same size integral mode.
> +(define_mode_attr mmxinsnmode
> + [(V8QI "DI") (V4QI "SI") (V2QI "HI")
> + (V4HI "DI") (V2HI "SI")
> + (V2SI "DI")
> + (V4HF "DI") (V2HF "SI")
> + (V2SF "DI")])
> +
> (define_mode_attr mmxdoublemode
> [(V8QI "V8HI") (V4HI "V4SI")])
>
> @@ -350,22 +358,7 @@ (define_insn_and_split "*mov<mode>_imm"
> HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[1],
> <MODE>mode);
> operands[1] = GEN_INT (val);
> - machine_mode mode;
> - switch (GET_MODE_SIZE (<MODE>mode))
> - {
> - case 2:
> - mode = HImode;
> - break;
> - case 4:
> - mode = SImode;
> - break;
> - case 8:
> - mode = DImode;
> - break;
> - default:
> - gcc_unreachable ();
> - }
> - operands[0] = lowpart_subreg (mode, operands[0], <MODE>mode);
> + operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
> })
>
> ;; For TARGET_64BIT we always round up to 8 bytes.
> @@ -2974,33 +2967,48 @@ (define_insn "*mmx_<code><mode>3"
> (set_attr "type" "mmxadd,sselog,sselog,sselog")
> (set_attr "mode" "DI,TI,TI,TI")])
>
> -(define_insn "<code><mode>3"
> - [(set (match_operand:VI_16_32 0 "register_operand" "=?r,x,x,v")
> +(define_expand "<code><mode>3"
> + [(set (match_operand:VI_16_32 0 "nonimmediate_operand")
> (any_logic:VI_16_32
> - (match_operand:VI_16_32 1 "register_operand" "%0,0,x,v")
> - (match_operand:VI_16_32 2 "register_operand" "r,x,x,v")))
> - (clobber (reg:CC FLAGS_REG))]
> + (match_operand:VI_16_32 1 "nonimmediate_operand")
> + (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand")))]
> ""
> + "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
> +
> +(define_insn "*<code><mode>3"
> + [(set (match_operand:VI_16_32 0 "nonimmediate_operand" "=?r,m,x,x,v")
> + (any_logic:VI_16_32
> + (match_operand:VI_16_32 1 "nonimmediate_operand" "%0,0,0,x,v")
> + (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand" "r,i,x,x,v")))
> + (clobber (reg:CC FLAGS_REG))]
> + "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> "#"
> - [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
> - (set_attr "type" "alu,sselog,sselog,sselog")
> - (set_attr "mode" "SI,TI,TI,TI")])
> + [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl")
> + (set_attr "type" "alu,alu,sselog,sselog,sselog")
> + (set_attr "mode" "SI,SI,TI,TI,TI")])
>
> (define_split
> - [(set (match_operand:VI_16_32 0 "general_reg_operand")
> + [(set (match_operand:VI_16_32 0 "nonimmediate_gr_operand")
> (any_logic:VI_16_32
> - (match_operand:VI_16_32 1 "general_reg_operand")
> - (match_operand:VI_16_32 2 "general_reg_operand")))
> + (match_operand:VI_16_32 1 "nonimmediate_gr_operand")
> + (match_operand:VI_16_32 2 "reg_or_const_vector_operand")))
> (clobber (reg:CC FLAGS_REG))]
> "reload_completed"
> [(parallel
> [(set (match_dup 0)
> - (any_logic:SI (match_dup 1) (match_dup 2)))
> + (any_logic:<mmxinsnmode> (match_dup 1) (match_dup 2)))
> (clobber (reg:CC FLAGS_REG))])]
> {
> - operands[2] = lowpart_subreg (SImode, operands[2], <MODE>mode);
> - operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
> - operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
> + if (!register_operand (operands[2], <MODE>mode))
> + {
> + HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[2],
> + <MODE>mode);
> + operands[2] = GEN_INT (val);
> + }
> + else
> + operands[2] = lowpart_subreg (<mmxinsnmode>mode, operands[2], <MODE>mode);
> + operands[1] = lowpart_subreg (<mmxinsnmode>mode, operands[1], <MODE>mode);
> + operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
> })
>
> (define_split
> diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
> index c71c453cceb..73dfd46bf90 100644
> --- a/gcc/config/i386/predicates.md
> +++ b/gcc/config/i386/predicates.md
> @@ -1205,6 +1205,10 @@ (define_predicate "x86_64_const_vector_operand"
> return trunc_int_for_mode (val, SImode) == val;
> })
>
> +(define_predicate "nonimmediate_or_x86_64_const_vector_operand"
> + (ior (match_operand 0 "nonimmediate_operand")
> + (match_operand 0 "x86_64_const_vector_operand")))
> +
> ;; Return true when OP is nonimmediate or standard SSE constant.
> (define_predicate "nonimmediate_or_sse_const_operand"
> (ior (match_operand 0 "nonimmediate_operand")
> diff --git a/gcc/testsuite/gcc.target/i386/pr106038-1.c b/gcc/testsuite/gcc.target/i386/pr106038-1.c
> new file mode 100644
> index 00000000000..bb52385c8a5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr106038-1.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-msse2 -O2" } */
> +/* { dg-final { scan-assembler-not "xmm" } } */
> +
> +void
> +foo3 (char* a, char* __restrict b)
> +{
> + a[0] &= 1;
> + a[1] &= 2;
> + a[2] &= 3;
> + a[3] &= 3;
> +}
> +
> +void
> +foo4 (char* a, char* __restrict b)
> +{
> + a[0] &= 1;
> + a[1] &= 2;
> +}
> +
> +
> +void
> +foo1 (short* a, short* __restrict b)
> +{
> + a[0] &= 1;
> + a[1] &= 2;
> +}
> --
> 2.18.1
>
prev parent reply other threads:[~2022-07-21 5:55 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-11 1:15 [PATCH] Allocate general register(memory/immediate) for 16/32/64-bit vector bit_op patterns liuhongt
2022-07-11 8:02 ` Uros Bizjak
2022-07-12 6:37 ` Hongtao Liu
2022-07-12 7:15 ` Uros Bizjak
2022-07-14 5:33 ` [PATCH] Extend 64-bit vector bit_op patterns with ?r alternative liuhongt
2022-07-14 7:22 ` Uros Bizjak
2022-07-14 9:32 ` Hongtao Liu
2022-07-14 9:46 ` Uros Bizjak
2022-07-18 1:59 ` [PATCH] Extend 16/32-bit vector bit_op patterns with (m, 0, i)(vertical) alternative liuhongt
2022-07-18 6:28 ` [PATCH] Extend 16/32-bit vector bit_op patterns with (m,0,i)(vertical) alternative Uros Bizjak
2022-07-19 6:07 ` [PATCH V2] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative liuhongt
2022-07-19 6:34 ` Uros Bizjak
2022-07-19 6:56 ` Hongtao Liu
2022-07-19 9:37 ` Uros Bizjak
2022-07-20 2:37 ` Hongtao Liu
2022-07-20 6:14 ` Uros Bizjak
2022-07-20 6:18 ` Uros Bizjak
2022-07-20 6:54 ` Hongtao Liu
2022-07-20 7:18 ` Uros Bizjak
2022-07-20 7:22 ` Hongtao Liu
2022-07-21 5:18 ` [PATCH V3] " liuhongt
2022-07-21 5:55 ` Uros Bizjak [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAFULd4ZpmSrsBGa6Vt1LscP_Jm09HPgrA6FgTVqV9eORdhJR_g@mail.gmail.com \
--to=ubizjak@gmail.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=hongtao.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).