From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
To: Andrea Corallo <Andrea.Corallo@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,
Andrea Corallo <Andrea.Corallo@arm.com>
Subject: RE: [PATCH 03/23] arm: improve tests and fix vnegq*
Date: Fri, 20 Jan 2023 17:47:44 +0000 [thread overview]
Message-ID: <PAXPR08MB69267E3CAC996BA10B91D12093C59@PAXPR08MB6926.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <20230120163948.752531-4-andrea.corallo@arm.com>
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, January 20, 2023 4:39 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
> Subject: [PATCH 03/23] arm: improve tests and fix vnegq*
>
> gcc/ChangeLog:
>
> * config/arm/mve.md (mve_vnegq_f<mode>,
> mve_vnegq_s<mode>):
> Fix spacing.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Improve test.
Ok as before.
Thanks,
Kyrill
> * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise.
> * gcc.target/arm/simd/mve-vneg.c: Update test.
> * gcc.target/arm/simd/mve-vshr.c: Likewise
> ---
> gcc/config/arm/mve.md | 4 +--
> .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 30 ++++++++++++++++-
> .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 30 ++++++++++++++++-
> .../arm/mve/intrinsics/vnegq_m_f16.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_m_f32.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_m_s16.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_m_s32.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_m_s8.c | 33 +++++++++++++++++--
> .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 28 +++++++++++++---
> .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 28 +++++++++++++---
> .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 24 ++++++++++++--
> .../arm/mve/intrinsics/vnegq_x_f16.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_x_f32.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_x_s16.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_x_s32.c | 33 +++++++++++++++++--
> .../arm/mve/intrinsics/vnegq_x_s8.c | 33 +++++++++++++++++--
> gcc/testsuite/gcc.target/arm/simd/mve-vneg.c | 4 +--
> gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 2 +-
> 18 files changed, 433 insertions(+), 47 deletions(-)
>
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 854371f7e11..0a243486bdb 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -252,7 +252,7 @@ (define_insn "mve_vnegq_f<mode>"
> (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> - "vneg.f%#<V_sz_elem> %q0, %q1"
> + "vneg.f%#<V_sz_elem>\t%q0, %q1"
> [(set_attr "type" "mve_move")
> ])
>
> @@ -401,7 +401,7 @@ (define_insn "mve_vnegq_s<mode>"
> (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
> ]
> "TARGET_HAVE_MVE"
> - "vneg.s%#<V_sz_elem> %q0, %q1"
> + "vneg.s%#<V_sz_elem>\t%q0, %q1"
> [(set_attr "type" "mve_move")
> ])
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
> index 9572c140d7e..9853cf6e6dd 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
> @@ -1,13 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float16x8_t
> foo (float16x8_t a)
> {
> return vnegq_f16 (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.f16" } } */
> +
> +/*
> +**foo1:
> +** ...
> +** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> +float16x8_t
> +foo1 (float16x8_t a)
> +{
> + return vnegq (a);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
> index be73cc0c5f5..489cfc760ba 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
> @@ -1,13 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float32x4_t
> foo (float32x4_t a)
> {
> return vnegq_f32 (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.f32" } } */
> +
> +/*
> +**foo1:
> +** ...
> +** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> +float32x4_t
> +foo1 (float32x4_t a)
> +{
> + return vnegq (a);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
> index 0d917b80cd7..c8b307ea50e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float16x8_t
> foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
> {
> return vnegq_m_f16 (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.f16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float16x8_t
> foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
> {
> return vnegq_m (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
> index f1c0e9a99b0..a530a05e644 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float32x4_t
> foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
> {
> return vnegq_m_f32 (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.f32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float32x4_t
> foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
> {
> return vnegq_m (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
> index 9a945ee62a3..46d6e794dbe 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int16x8_t
> foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
> {
> return vnegq_m_s16 (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.s16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int16x8_t
> foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
> {
> return vnegq_m (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
> index 811f1df0565..5fb1f5c2a4c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
> {
> return vnegq_m_s32 (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
> {
> return vnegq_m (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
> index 430ebc73783..868a9680858 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int8x16_t
> foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
> {
> return vnegq_m_s8 (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.s8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int8x16_t
> foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
> {
> return vnegq_m (inactive, a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
> index a47f9b3423e..3b518c8e0f5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
> @@ -1,21 +1,41 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int16x8_t
> foo (int16x8_t a)
> {
> return vnegq_s16 (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.s16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int16x8_t
> foo1 (int16x8_t a)
> {
> return vnegq (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.s16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
> index 50401f53bd7..f8682575892 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
> @@ -1,21 +1,41 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo (int32x4_t a)
> {
> return vnegq_s32 (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo1 (int32x4_t a)
> {
> return vnegq (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
> index fd5de3dab56..1be5901740e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int8x16_t
> foo (int8x16_t a)
> {
> return vnegq_s8 (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.s8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int8x16_t
> foo1 (int8x16_t a)
> {
> return vnegq (a);
> }
>
> -/* { dg-final { scan-assembler "vneg.s8" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
> index e7af36691dc..c10d6d2aebf 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float16x8_t
> foo (float16x8_t a, mve_pred16_t p)
> {
> return vnegq_x_f16 (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.f16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float16x8_t
> foo1 (float16x8_t a, mve_pred16_t p)
> {
> return vnegq_x (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
> index d9c3818855a..0ee5ecc8262 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float32x4_t
> foo (float32x4_t a, mve_pred16_t p)
> {
> return vnegq_x_f32 (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.f32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> float32x4_t
> foo1 (float32x4_t a, mve_pred16_t p)
> {
> return vnegq_x (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
> index 16f1fa452ce..d774a055d72 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int16x8_t
> foo (int16x8_t a, mve_pred16_t p)
> {
> return vnegq_x_s16 (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.s16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int16x8_t
> foo1 (int16x8_t a, mve_pred16_t p)
> {
> return vnegq_x (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
> index d74683c6f24..77bf1a67cfe 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo (int32x4_t a, mve_pred16_t p)
> {
> return vnegq_x_s32 (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo1 (int32x4_t a, mve_pred16_t p)
> {
> return vnegq_x (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
> index eda4c7fcf7e..ca44512e37a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
> @@ -1,22 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int8x16_t
> foo (int8x16_t a, mve_pred16_t p)
> {
> return vnegq_x_s8 (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vnegt.s8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|)
> +** ...
> +*/
> int8x16_t
> foo1 (int8x16_t a, mve_pred16_t p)
> {
> return vnegq_x (a, p);
> }
>
> -/* { dg-final { scan-assembler "vpst" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
> b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
> index 7945a060e25..1379cae579f 100644
> --- a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
> @@ -45,8 +45,8 @@ FUNC(f, float, 16, 8, -, vneg)
>
> /* MVE has only 128-bit vectors, so we can vectorize only half of the
> functions above. */
> -/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 } } */
> -/* { dg-final { scan-assembler-times {vneg.f[0-9]+ q[0-9]+, q[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {vneg.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */
> /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 8 } } */
> /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 8 } } */
> /* { dg-final { scan-assembler-not {orr\tr[0-9]+, r[0-9]+, r[0-9]+} } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> index d4258e9fefe..8c7adef9ed8 100644
> --- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
> @@ -58,7 +58,7 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
> /* Vector right shifts use vneg and left shifts. */
> /* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> /* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
> -/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */
>
>
> /* Shift by immediate. */
> --
> 2.25.1
next prev parent reply other threads:[~2023-01-20 17:48 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 16:39 [PATCH 00/23] arm: rework MVE testsuite and rework backend where necessary (3rd chunck) Andrea Corallo
2023-01-20 16:39 ` [PATCH 01/23] arm: improve tests and fix vclsq* Andrea Corallo
2023-01-20 17:44 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 02/23] arm: improve tests and fix vclzq* Andrea Corallo
2023-01-20 17:46 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 03/23] arm: improve tests and fix vnegq* Andrea Corallo
2023-01-20 17:47 ` Kyrylo Tkachov [this message]
2023-01-20 16:39 ` [PATCH 04/23] arm: improve tests for vmulhq* Andrea Corallo
2023-01-20 17:48 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 05/23] arm: improve tests for vmullbq* Andrea Corallo
2023-01-20 17:51 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 06/23] arm: improve tests for vmulltq* Andrea Corallo
2023-01-20 17:52 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 07/23] arm: improve tests for vcaddq* Andrea Corallo
2023-01-20 17:52 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 08/23] arm: improve tests for vcmlaq* Andrea Corallo
2023-01-20 17:53 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 09/23] arm: improve tests for vcmulq* Andrea Corallo
2023-01-20 17:59 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 10/23] arm: improve tests and fix vqabsq* Andrea Corallo
2023-01-20 18:01 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 11/23] arm: improve tests for vqdmladhq* Andrea Corallo
2023-01-20 18:03 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 12/23] arm: improve tests for vqdmladhxq* Andrea Corallo
2023-01-20 18:04 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 13/23] arm: improve tests for vqrdmladhq* Andrea Corallo
2023-01-20 18:04 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 14/23] arm: improve tests for vqrdmladhxq* Andrea Corallo
2023-01-20 18:05 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 15/23] arm: improve tests for vqrdmlashq* Andrea Corallo
2023-01-20 18:06 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 16/23] arm: improve tests for vqdmlsdhq* Andrea Corallo
2023-01-20 18:06 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 17/23] arm: improve tests for vqdmlsdhxq* Andrea Corallo
2023-01-20 18:07 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 18/23] arm: improve tests for vqrdmlsdhq* Andrea Corallo
2023-01-20 18:07 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 19/23] arm: improve tests for vqrdmlsdhxq* Andrea Corallo
2023-01-20 18:08 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 20/23] arm: improve tests for vqrdmulhq* Andrea Corallo
2023-01-20 18:08 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 21/23] arm: improve tests and fix vqnegq* Andrea Corallo
2023-01-20 18:08 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 22/23] arm: improve tests for vld2q* Andrea Corallo
2023-01-20 18:09 ` Kyrylo Tkachov
2023-01-20 16:39 ` [PATCH 23/23] arm: fix missing extern "C" in MVE tests Andrea Corallo
2023-01-20 18:10 ` Kyrylo Tkachov
2023-01-25 13:53 ` Andrea Corallo
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