* [PATCH] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
@ 2022-11-13 20:48 Philipp Tomsich
2022-11-15 17:36 ` Jeff Law
0 siblings, 1 reply; 3+ messages in thread
From: Philipp Tomsich @ 2022-11-13 20:48 UTC (permalink / raw)
To: gcc-patches
Cc: Jeff Law, Palmer Dabbelt, Christoph Muellner, Kito Cheng,
Vineet Gupta, Philipp Tomsich
We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
by splitting it into a zero-extraction (bext) and an xori. This both
avoids burning a register on a temporary and generates a sequence that
clearly captures 'extract bit, then invert bit'.
This change improves the previously generated
srl a0,a0,a1
not a0,a0
andi a0,a0,1
into
bext a0,a0,a1
xori a0,a0,1
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add split covering
"(a & (1 << BIT_NO)) ? 0 : 1".
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext.c: Add testcases.
* gcc.target/riscv/zbs-bexti.c: Add testcases.
---
gcc/config/riscv/bitmanip.md | 13 +++++++++++++
gcc/testsuite/gcc.target/riscv/zbs-bext.c | 10 ++++++++--
gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 10 ++++++++--
3 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 8222c600ca5..7a8f4e35880 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -677,3 +677,16 @@
"TARGET_ZBS"
[(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))])
+
+;; Split for "(a & (1 << BIT_NO)) ? 0 : 1":
+;; We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1",
+;; so we don't have to use a temporary. Instead we extract the bit and then
+;; invert bit 0 ("a ^ 1") only.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
+ (subreg:QI (match_operand:X 2 "register_operand") 0)))
+ (const_int 1)))]
+ "TARGET_ZBS"
+ [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
index 8de9c5a167c..a8aadb60390 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
@@ -23,16 +23,22 @@ long bext64_1(long a, char bitno)
long bext64_2(long a, char bitno)
{
- return (a & (1UL << bitno)) ? 0 : -1;
+ return (a & (1UL << bitno)) ? 0 : 1;
}
long bext64_3(long a, char bitno)
+{
+ return (a & (1UL << bitno)) ? 0 : -1;
+}
+
+long bext64_4(long a, char bitno)
{
return (a & (1UL << bitno)) ? -1 : 0;
}
/* { dg-final { scan-assembler-times "bexti\t" 1 } } */
-/* { dg-final { scan-assembler-times "bext\t" 4 } } */
+/* { dg-final { scan-assembler-times "bext\t" 5 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
/* { dg-final { scan-assembler-times "addi\t" 1 } } */
/* { dg-final { scan-assembler-times "neg\t" 1 } } */
/* { dg-final { scan-assembler-not "andi" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
index 30b69c9bc3e..c15098eb6cc 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
@@ -12,14 +12,20 @@ long bexti64_1(long a, char bitno)
long bexti64_2(long a, char bitno)
{
- return (a & (1UL << BIT_NO)) ? 0 : -1;
+ return (a & (1UL << BIT_NO)) ? 0 : 1;
}
long bexti64_3(long a, char bitno)
+{
+ return (a & (1UL << BIT_NO)) ? 0 : -1;
+}
+
+long bexti64_4(long a, char bitno)
{
return (a & (1UL << BIT_NO)) ? -1 : 0;
}
-/* { dg-final { scan-assembler-times "bexti\t" 3 } } */
+/* { dg-final { scan-assembler-times "bexti\t" 4 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
/* { dg-final { scan-assembler-times "addi\t" 1 } } */
/* { dg-final { scan-assembler-times "neg\t" 1 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
2022-11-13 20:48 [PATCH] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori Philipp Tomsich
@ 2022-11-15 17:36 ` Jeff Law
2022-11-16 20:01 ` Philipp Tomsich
0 siblings, 1 reply; 3+ messages in thread
From: Jeff Law @ 2022-11-15 17:36 UTC (permalink / raw)
To: Philipp Tomsich, gcc-patches
Cc: Jeff Law, Palmer Dabbelt, Christoph Muellner, Kito Cheng, Vineet Gupta
On 11/13/22 13:48, Philipp Tomsich wrote:
> We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
> by splitting it into a zero-extraction (bext) and an xori. This both
> avoids burning a register on a temporary and generates a sequence that
> clearly captures 'extract bit, then invert bit'.
>
> This change improves the previously generated
> srl a0,a0,a1
> not a0,a0
> andi a0,a0,1
> into
> bext a0,a0,a1
> xori a0,a0,1
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> gcc/ChangeLog:
>
> * config/riscv/bitmanip.md: Add split covering
> "(a & (1 << BIT_NO)) ? 0 : 1".
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zbs-bext.c: Add testcases.
> * gcc.target/riscv/zbs-bexti.c: Add testcases.
OK. Not terribly happy with the SUBREG, but I can guess that's an
artifact of other patterns which require that operand to be QImode.
Jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
2022-11-15 17:36 ` Jeff Law
@ 2022-11-16 20:01 ` Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2022-11-16 20:01 UTC (permalink / raw)
To: Jeff Law
Cc: gcc-patches, Jeff Law, Palmer Dabbelt, Christoph Muellner,
Kito Cheng, Vineet Gupta
[-- Attachment #1: Type: text/plain, Size: 1118 bytes --]
Applied to master. Thanks!
Philipp.
On Tue, 15 Nov 2022 at 18:36, Jeff Law <jeffreyalaw@gmail.com> wrote:
>
> On 11/13/22 13:48, Philipp Tomsich wrote:
> > We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
> > by splitting it into a zero-extraction (bext) and an xori. This both
> > avoids burning a register on a temporary and generates a sequence that
> > clearly captures 'extract bit, then invert bit'.
> >
> > This change improves the previously generated
> > srl a0,a0,a1
> > not a0,a0
> > andi a0,a0,1
> > into
> > bext a0,a0,a1
> > xori a0,a0,1
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/bitmanip.md: Add split covering
> > "(a & (1 << BIT_NO)) ? 0 : 1".
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/zbs-bext.c: Add testcases.
> > * gcc.target/riscv/zbs-bexti.c: Add testcases.
>
> OK. Not terribly happy with the SUBREG, but I can guess that's an
> artifact of other patterns which require that operand to be QImode.
>
>
> Jeff
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-11-13 20:48 [PATCH] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori Philipp Tomsich
2022-11-15 17:36 ` Jeff Law
2022-11-16 20:01 ` Philipp Tomsich
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