public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
* [PATCH v3, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions
@ 2022-09-07  7:44 HAO CHEN GUI
  2022-09-21  5:32 ` Ping " HAO CHEN GUI
  2022-10-20  9:27 ` Kewen.Lin
  0 siblings, 2 replies; 3+ messages in thread
From: HAO CHEN GUI @ 2022-09-07  7:44 UTC (permalink / raw)
  To: gcc-patches; +Cc: Segher Boessenkool, David, Kewen.Lin, Peter Bergner

Hi,

  For scalar extract/insert instructions, exponent field can be stored in a
32-bit register. So this patch changes the mode of exponent field from DI to
SI. The instructions using DI registers can be invoked with -mpowerpc64 in a
32-bit environment. The patch changes insn condition from TARGET_64BIT to
TARGET_POWERPC64 for those instructions.

  This patch also changes prototypes of relevant built-ins and effective
target of test cases.

  Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
Is this okay for trunk? Any recommendations? Thanks a lot.

ChangeLog
2022-09-07  Haochen Gui  <guihaoc@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-builtins.def
	(__builtin_vsx_scalar_extract_exp): Set return type to const unsigned
	int.
	(__builtin_vsx_scalar_extract_sig): Set return type to const unsigned
	long long.
	(__builtin_vsx_scalar_insert_exp): Set type of second argument to
	unsigned int.
	(__builtin_vsx_scalar_insert_exp_dp): Likewise.
	* config/rs6000/vsx.md (xsxexpdp): Set mode of first operand to
	SImode.  Remove TARGET_64BIT from insn condition.
	(xsxsigdp): Change insn condition from TARGET_64BIT to TARGET_POWERPC64.
	(xsiexpdp): Change insn condition from TARGET_64BIT to
	TARGET_POWERPC64.  Set mode of third operand to SImode.
	(xsiexpdpf): Set mode of third operand to SImode.  Remove TARGET_64BIT
	from insn condition.

gcc/testsuite/
	* gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Change effective
	target from lp64 to has_arch_ppc64.
	* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise.

patch.diff
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index f76f54793d7..ca2a1d7657e 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2847,17 +2847,17 @@
   pure vsc __builtin_vsx_lxvl (const void *, signed long);
     LXVL lxvl {}

-  const signed long __builtin_vsx_scalar_extract_exp (double);
+  const unsigned int __builtin_vsx_scalar_extract_exp (double);
     VSEEDP xsxexpdp {}

-  const signed long __builtin_vsx_scalar_extract_sig (double);
+  const unsigned long long __builtin_vsx_scalar_extract_sig (double);
     VSESDP xsxsigdp {}

   const double __builtin_vsx_scalar_insert_exp (unsigned long long, \
-                                                unsigned long long);
+						unsigned int);
     VSIEDP xsiexpdp {}

-  const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
+  const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned int);
     VSIEDPF xsiexpdpf {}

   pure vsc __builtin_vsx_xl_len_r (void *, signed long);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e226a93bbe5..9d3a2340a79 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5095,10 +5095,10 @@ (define_insn "xsxexpqp_<mode>"

 ;; VSX Scalar Extract Exponent Double-Precision
 (define_insn "xsxexpdp"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec:SI [(match_operand:DF 1 "vsx_register_operand" "wa")]
 	 UNSPEC_VSX_SXEXPDP))]
-  "TARGET_P9_VECTOR && TARGET_64BIT"
+  "TARGET_P9_VECTOR"
   "xsxexpdp %0,%x1"
   [(set_attr "type" "integer")])

@@ -5116,7 +5116,7 @@ (define_insn "xsxsigdp"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
 	 UNSPEC_VSX_SXSIG))]
-  "TARGET_P9_VECTOR && TARGET_64BIT"
+  "TARGET_P9_VECTOR && TARGET_POWERPC64"
   "xsxsigdp %0,%x1"
   [(set_attr "type" "integer")])

@@ -5145,9 +5145,9 @@ (define_insn "xsiexpqp_<mode>"
 (define_insn "xsiexpdp"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:DI 1 "register_operand" "r")
-		    (match_operand:DI 2 "register_operand" "r")]
+		    (match_operand:SI 2 "register_operand" "r")]
 	 UNSPEC_VSX_SIEXPDP))]
-  "TARGET_P9_VECTOR && TARGET_64BIT"
+  "TARGET_P9_VECTOR && TARGET_POWERPC64"
   "xsiexpdp %x0,%1,%2"
   [(set_attr "type" "fpsimple")])

@@ -5155,9 +5155,9 @@ (define_insn "xsiexpdp"
 (define_insn "xsiexpdpf"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:DF 1 "register_operand" "r")
-		    (match_operand:DI 2 "register_operand" "r")]
+		    (match_operand:SI 2 "register_operand" "r")]
 	 UNSPEC_VSX_SIEXPDP))]
-  "TARGET_P9_VECTOR && TARGET_64BIT"
+  "TARGET_P9_VECTOR"
   "xsiexpdp %x0,%1,%2"
   [(set_attr "type" "fpsimple")])

diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
index 35bf1b240f3..9f327a4be6c 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
@@ -1,7 +1,7 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-do compile } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
index b9dd7d61aae..136471a35b3 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
@@ -1,7 +1,7 @@
-/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target p9vector_hw } */
+/* { dg-do run } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target p9vector_hw } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
index 637080652b7..3be7eb13566 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
@@ -1,7 +1,7 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-do compile } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
index c85072da138..b96a745157d 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
@@ -1,7 +1,7 @@
-/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target p9vector_hw } */
+/* { dg-do run } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target p9vector_hw } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
index d8243258a67..074c23f4530 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
@@ -1,7 +1,7 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-do compile } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
index 384fc9cc675..6260e577c7d 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
@@ -1,7 +1,7 @@
-/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target p9vector_hw } */
+/* { dg-do run } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target p9vector_hw } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
index 0e004224277..f024d390a5d 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
@@ -1,7 +1,7 @@
-/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target p9vector_hw } */
+/* { dg-do run } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target p9vector_hw } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
index 3ecbe3318e8..a65dce901df 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
@@ -1,7 +1,7 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-do compile } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */

 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Ping [PATCH v3, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions
  2022-09-07  7:44 [PATCH v3, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions HAO CHEN GUI
@ 2022-09-21  5:32 ` HAO CHEN GUI
  2022-10-20  9:27 ` Kewen.Lin
  1 sibling, 0 replies; 3+ messages in thread
From: HAO CHEN GUI @ 2022-09-21  5:32 UTC (permalink / raw)
  To: gcc-patches; +Cc: Segher Boessenkool, David, Kewen.Lin, Peter Bergner

Hi,
     Gentle ping this:
https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601196.html
Thanks.

On 7/9/2022 下午 3:44, HAO CHEN GUI wrote:
> Hi,
> 
>   For scalar extract/insert instructions, exponent field can be stored in a
> 32-bit register. So this patch changes the mode of exponent field from DI to
> SI. The instructions using DI registers can be invoked with -mpowerpc64 in a
> 32-bit environment. The patch changes insn condition from TARGET_64BIT to
> TARGET_POWERPC64 for those instructions.
> 
>   This patch also changes prototypes of relevant built-ins and effective
> target of test cases.
> 
>   Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk? Any recommendations? Thanks a lot.
> 
> ChangeLog
> 2022-09-07  Haochen Gui  <guihaoc@linux.ibm.com>
> 
> gcc/
> 	* config/rs6000/rs6000-builtins.def
> 	(__builtin_vsx_scalar_extract_exp): Set return type to const unsigned
> 	int.
> 	(__builtin_vsx_scalar_extract_sig): Set return type to const unsigned
> 	long long.
> 	(__builtin_vsx_scalar_insert_exp): Set type of second argument to
> 	unsigned int.
> 	(__builtin_vsx_scalar_insert_exp_dp): Likewise.
> 	* config/rs6000/vsx.md (xsxexpdp): Set mode of first operand to
> 	SImode.  Remove TARGET_64BIT from insn condition.
> 	(xsxsigdp): Change insn condition from TARGET_64BIT to TARGET_POWERPC64.
> 	(xsiexpdp): Change insn condition from TARGET_64BIT to
> 	TARGET_POWERPC64.  Set mode of third operand to SImode.
> 	(xsiexpdpf): Set mode of third operand to SImode.  Remove TARGET_64BIT
> 	from insn condition.
> 
> gcc/testsuite/
> 	* gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Change effective
> 	target from lp64 to has_arch_ppc64.
> 	* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise.
> 
> patch.diff
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index f76f54793d7..ca2a1d7657e 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2847,17 +2847,17 @@
>    pure vsc __builtin_vsx_lxvl (const void *, signed long);
>      LXVL lxvl {}
> 
> -  const signed long __builtin_vsx_scalar_extract_exp (double);
> +  const unsigned int __builtin_vsx_scalar_extract_exp (double);
>      VSEEDP xsxexpdp {}
> 
> -  const signed long __builtin_vsx_scalar_extract_sig (double);
> +  const unsigned long long __builtin_vsx_scalar_extract_sig (double);
>      VSESDP xsxsigdp {}
> 
>    const double __builtin_vsx_scalar_insert_exp (unsigned long long, \
> -                                                unsigned long long);
> +						unsigned int);
>      VSIEDP xsiexpdp {}
> 
> -  const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
> +  const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned int);
>      VSIEDPF xsiexpdpf {}
> 
>    pure vsc __builtin_vsx_xl_len_r (void *, signed long);
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index e226a93bbe5..9d3a2340a79 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -5095,10 +5095,10 @@ (define_insn "xsxexpqp_<mode>"
> 
>  ;; VSX Scalar Extract Exponent Double-Precision
>  (define_insn "xsxexpdp"
> -  [(set (match_operand:DI 0 "register_operand" "=r")
> -	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(unspec:SI [(match_operand:DF 1 "vsx_register_operand" "wa")]
>  	 UNSPEC_VSX_SXEXPDP))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR"
>    "xsxexpdp %0,%x1"
>    [(set_attr "type" "integer")])
> 
> @@ -5116,7 +5116,7 @@ (define_insn "xsxsigdp"
>    [(set (match_operand:DI 0 "register_operand" "=r")
>  	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
>  	 UNSPEC_VSX_SXSIG))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR && TARGET_POWERPC64"
>    "xsxsigdp %0,%x1"
>    [(set_attr "type" "integer")])
> 
> @@ -5145,9 +5145,9 @@ (define_insn "xsiexpqp_<mode>"
>  (define_insn "xsiexpdp"
>    [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
>  	(unspec:DF [(match_operand:DI 1 "register_operand" "r")
> -		    (match_operand:DI 2 "register_operand" "r")]
> +		    (match_operand:SI 2 "register_operand" "r")]
>  	 UNSPEC_VSX_SIEXPDP))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR && TARGET_POWERPC64"
>    "xsiexpdp %x0,%1,%2"
>    [(set_attr "type" "fpsimple")])
> 
> @@ -5155,9 +5155,9 @@ (define_insn "xsiexpdp"
>  (define_insn "xsiexpdpf"
>    [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
>  	(unspec:DF [(match_operand:DF 1 "register_operand" "r")
> -		    (match_operand:DI 2 "register_operand" "r")]
> +		    (match_operand:SI 2 "register_operand" "r")]
>  	 UNSPEC_VSX_SIEXPDP))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR"
>    "xsiexpdp %x0,%1,%2"
>    [(set_attr "type" "fpsimple")])
> 
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
> index 35bf1b240f3..9f327a4be6c 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
> index b9dd7d61aae..136471a35b3 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
> index 637080652b7..3be7eb13566 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
> index c85072da138..b96a745157d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> index d8243258a67..074c23f4530 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> index 384fc9cc675..6260e577c7d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> index 0e004224277..f024d390a5d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> index 3ecbe3318e8..a65dce901df 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v3, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions
  2022-09-07  7:44 [PATCH v3, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions HAO CHEN GUI
  2022-09-21  5:32 ` Ping " HAO CHEN GUI
@ 2022-10-20  9:27 ` Kewen.Lin
  1 sibling, 0 replies; 3+ messages in thread
From: Kewen.Lin @ 2022-10-20  9:27 UTC (permalink / raw)
  To: HAO CHEN GUI; +Cc: Segher Boessenkool, David, Peter Bergner, gcc-patches

Hi Haochen,

Sorry for late review, some comments are inline.

on 2022/9/7 15:44, HAO CHEN GUI wrote:
> Hi,
> 
>   For scalar extract/insert instructions, exponent field can be stored in a
> 32-bit register. So this patch changes the mode of exponent field from DI to
> SI. The instructions using DI registers can be invoked with -mpowerpc64 in a
> 32-bit environment. The patch changes insn condition from TARGET_64BIT to
> TARGET_POWERPC64 for those instructions.
> 
>   This patch also changes prototypes of relevant built-ins and effective
> target of test cases.
> 
>   Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk? Any recommendations? Thanks a lot.
> 
> ChangeLog
> 2022-09-07  Haochen Gui  <guihaoc@linux.ibm.com>
> 
> gcc/
> 	* config/rs6000/rs6000-builtins.def
> 	(__builtin_vsx_scalar_extract_exp): Set return type to const unsigned
> 	int.
> 	(__builtin_vsx_scalar_extract_sig): Set return type to const unsigned
> 	long long.
> 	(__builtin_vsx_scalar_insert_exp): Set type of second argument to
> 	unsigned int.
> 	(__builtin_vsx_scalar_insert_exp_dp): Likewise.
> 	* config/rs6000/vsx.md (xsxexpdp): Set mode of first operand to
> 	SImode.  Remove TARGET_64BIT from insn condition.
> 	(xsxsigdp): Change insn condition from TARGET_64BIT to TARGET_POWERPC64.
> 	(xsiexpdp): Change insn condition from TARGET_64BIT to
> 	TARGET_POWERPC64.  Set mode of third operand to SImode.
> 	(xsiexpdpf): Set mode of third operand to SImode.  Remove TARGET_64BIT
> 	from insn condition.
> 
> gcc/testsuite/
> 	* gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Change effective
> 	target from lp64 to has_arch_ppc64.
> 	* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
> 	* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise.
> 
> patch.diff
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index f76f54793d7..ca2a1d7657e 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2847,17 +2847,17 @@
>    pure vsc __builtin_vsx_lxvl (const void *, signed long);
>      LXVL lxvl {}
> 
> -  const signed long __builtin_vsx_scalar_extract_exp (double);
> +  const unsigned int __builtin_vsx_scalar_extract_exp (double);
>      VSEEDP xsxexpdp {}
> 

With the relevant define_insn condition change and this prototype
change, I think this bif can work on 32 bit environment.  So it
should be moved to section [power9] instead of [power9-64]?

If we want this supported on 32 bit, the related documentation
and test cases need some updates accordingly.

For the documentation, such as "The *scalar_extract_exp* and
scalar_extract_sig functions require *a 64-bit environment*
supporting ISA 3.0 ...." in [1].

For the test case, please see separated comments in test case 
part below.

[1] https://gcc.gnu.org/onlinedocs//gcc/PowerPC-AltiVec-Built-in-Functions-Available-on-ISA-3_002e0.html

The above comments are also applied for the bif
__builtin_vsx_scalar_insert_exp_dp.


> -  const signed long __builtin_vsx_scalar_extract_sig (double);
> +  const unsigned long long __builtin_vsx_scalar_extract_sig (double);
>      VSESDP xsxsigdp {}
> 
>    const double __builtin_vsx_scalar_insert_exp (unsigned long long, \
> -                                                unsigned long long);
> +						unsigned int);
>      VSIEDP xsiexpdp {}
> 
> -  const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
> +  const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned int);
>      VSIEDPF xsiexpdpf {}
> 
>    pure vsc __builtin_vsx_xl_len_r (void *, signed long);
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index e226a93bbe5..9d3a2340a79 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -5095,10 +5095,10 @@ (define_insn "xsxexpqp_<mode>"
> 
>  ;; VSX Scalar Extract Exponent Double-Precision
>  (define_insn "xsxexpdp"
> -  [(set (match_operand:DI 0 "register_operand" "=r")
> -	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(unspec:SI [(match_operand:DF 1 "vsx_register_operand" "wa")]
>  	 UNSPEC_VSX_SXEXPDP))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR"
>    "xsxexpdp %0,%x1"
>    [(set_attr "type" "integer")])
> 
> @@ -5116,7 +5116,7 @@ (define_insn "xsxsigdp"
>    [(set (match_operand:DI 0 "register_operand" "=r")
>  	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
>  	 UNSPEC_VSX_SXSIG))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR && TARGET_POWERPC64"
>    "xsxsigdp %0,%x1"
>    [(set_attr "type" "integer")])
> 
> @@ -5145,9 +5145,9 @@ (define_insn "xsiexpqp_<mode>"
>  (define_insn "xsiexpdp"
>    [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
>  	(unspec:DF [(match_operand:DI 1 "register_operand" "r")
> -		    (match_operand:DI 2 "register_operand" "r")]
> +		    (match_operand:SI 2 "register_operand" "r")]
>  	 UNSPEC_VSX_SIEXPDP))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR && TARGET_POWERPC64"
>    "xsiexpdp %x0,%1,%2"
>    [(set_attr "type" "fpsimple")])
> 
> @@ -5155,9 +5155,9 @@ (define_insn "xsiexpdp"
>  (define_insn "xsiexpdpf"
>    [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
>  	(unspec:DF [(match_operand:DF 1 "register_operand" "r")
> -		    (match_operand:DI 2 "register_operand" "r")]
> +		    (match_operand:SI 2 "register_operand" "r")]
>  	 UNSPEC_VSX_SIEXPDP))]
> -  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "TARGET_P9_VECTOR"
>    "xsiexpdp %x0,%1,%2"
>    [(set_attr "type" "fpsimple")])
> 
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
> index 35bf1b240f3..9f327a4be6c 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */

If we all agree bif scalar_extract_exp should work on 32 bit
w/i or w/o has_arch_ppc64 support, then we should remove the
has_arch_ppc64 check here.

> 
>  /* This test should succeed only on 64-bit configurations.  */

This comment should be updated as well.  Same for scalar-extract-exp-6.c.

Besides, 

scalar-extract-exp-1.c doesn't need lp64;
scalar-extract-exp-2.c isn't effective any more.

And similar for scalar-insert-exp-{3,4,5}.c and scalar-insert-exp-13.c.

BR,
Kewen

>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
> index b9dd7d61aae..136471a35b3 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
> index 637080652b7..3be7eb13566 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
> index c85072da138..b96a745157d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> index d8243258a67..074c23f4530 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> index 384fc9cc675..6260e577c7d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> index 0e004224277..f024d390a5d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> @@ -1,7 +1,7 @@
> -/* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target p9vector_hw } */
> +/* { dg-do run } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */> +/* { dg-require-effective-target p9vector_hw } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> index 3ecbe3318e8..a65dce901df 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> @@ -1,7 +1,7 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> -/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-do compile } */
>  /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> 
>  /* This test should succeed only on 64-bit configurations.  */
>  #include <altivec.h>

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2022-10-20  9:27 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-07  7:44 [PATCH v3, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions HAO CHEN GUI
2022-09-21  5:32 ` Ping " HAO CHEN GUI
2022-10-20  9:27 ` Kewen.Lin

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).