* [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
@ 2023-06-28 11:55 Juzhe-Zhong
2023-06-28 18:16 ` Jeff Law
0 siblings, 1 reply; 13+ messages in thread
From: Juzhe-Zhong @ 2023-06-28 11:55 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc,
Juzhe-Zhong
Similar to vfwmacc. Add combine patterns as follows:
For vfwnmsac:
1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (reg) )))
2. (set (reg) (fma (neg (float_extend (reg))) (reg) (reg) )))
For vfwmsac:
1. (set (reg) (fma (float_extend (reg)) (float_extend (reg))) (neg (reg)) )))
2. (set (reg) (fma (float_extend (reg)) (reg) (neg (reg)) )))
For vfwnmacc:
1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (neg (reg)) )))
2. (set (reg) (fma (neg (float_extend (reg))) (reg) (neg (reg)) )))
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
(*single_widen_fnma<mode>): Ditto.
(*double_widen_fms<mode>): Ditto.
(*single_widen_fms<mode>): Ditto.
(*double_widen_fnms<mode>): Ditto.
(*single_widen_fnms<mode>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/widen/widen-10.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-11.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-12.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: New test.
---
gcc/config/riscv/autovec-opt.md | 182 ++++++++++++++++++
.../riscv/rvv/autovec/widen/widen-10.c | 22 +++
.../riscv/rvv/autovec/widen/widen-11.c | 22 +++
.../riscv/rvv/autovec/widen/widen-12.c | 22 +++
.../rvv/autovec/widen/widen-complicate-7.c | 27 +++
.../rvv/autovec/widen/widen-complicate-8.c | 27 +++
.../rvv/autovec/widen/widen-complicate-9.c | 27 +++
.../riscv/rvv/autovec/widen/widen_run-10.c | 32 +++
.../riscv/rvv/autovec/widen/widen_run-11.c | 32 +++
.../riscv/rvv/autovec/widen/widen_run-12.c | 32 +++
.../rvv/autovec/widen/widen_run_zvfh-10.c | 32 +++
.../rvv/autovec/widen/widen_run_zvfh-11.c | 32 +++
.../rvv/autovec/widen/widen_run_zvfh-12.c | 32 +++
13 files changed, 521 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 1a1cef0eaa5..0c0ba685d6b 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -502,3 +502,185 @@
}
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; -------------------------------------------------------------------------
+;; ---- [FP] VFWNMSAC
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfwnmsac.vv
+;; -------------------------------------------------------------------------
+
+;; Combine ext + ext + fnma ===> widen fnma.
+;; Most of circumstantces, LoopVectorizer will generate the following IR:
+;; vect__8.176_40 = (vector([2,2]) double) vect__7.175_41;
+;; vect__11.180_35 = (vector([2,2]) double) vect__10.179_36;
+;; vect__13.182_33 = .FNMA (vect__11.180_35, vect__8.176_40, vect__4.172_45);
+(define_insn_and_split "*double_widen_fnma<mode>"
+ [(set (match_operand:VWEXTF 0 "register_operand")
+ (fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
+ (match_operand:VWEXTF 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_widen_mul_neg (PLUS, <MODE>mode),
+ riscv_vector::RVV_WIDEN_TERNOP, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; This helps to match ext + fnma.
+(define_insn_and_split "*single_widen_fnma<mode>"
+ [(set (match_operand:VWEXTF 0 "register_operand")
+ (fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
+ (match_operand:VWEXTF 3 "register_operand")
+ (match_operand:VWEXTF 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ insn_code icode = code_for_pred_extend (<MODE>mode);
+ rtx tmp = gen_reg_rtx (<MODE>mode);
+ rtx ext_ops[] = {tmp, operands[2]};
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ext_ops);
+
+ rtx dst = expand_ternary_op (<MODE>mode, fnma_optab, tmp, operands[3],
+ operands[1], operands[0], 0);
+ emit_move_insn (operands[0], dst);
+ DONE;
+ }
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; -------------------------------------------------------------------------
+;; ---- [FP] VFWMSAC
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfwmsac.vv
+;; -------------------------------------------------------------------------
+
+;; Combine ext + ext + fms ===> widen fms.
+;; Most of circumstantces, LoopVectorizer will generate the following IR:
+;; vect__8.176_40 = (vector([2,2]) double) vect__7.175_41;
+;; vect__11.180_35 = (vector([2,2]) double) vect__10.179_36;
+;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
+(define_insn_and_split "*double_widen_fms<mode>"
+ [(set (match_operand:VWEXTF 0 "register_operand")
+ (fma:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand"))))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_widen_mul (MINUS, <MODE>mode),
+ riscv_vector::RVV_WIDEN_TERNOP, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; This helps to match ext + fms.
+(define_insn_and_split "*single_widen_fms<mode>"
+ [(set (match_operand:VWEXTF 0 "register_operand")
+ (fma:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+ (match_operand:VWEXTF 3 "register_operand")
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand"))))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ insn_code icode = code_for_pred_extend (<MODE>mode);
+ rtx tmp = gen_reg_rtx (<MODE>mode);
+ rtx ext_ops[] = {tmp, operands[2]};
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ext_ops);
+
+ rtx dst = expand_ternary_op (<MODE>mode, fms_optab, tmp, operands[3],
+ operands[1], operands[0], 0);
+ emit_move_insn (operands[0], dst);
+ DONE;
+ }
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; -------------------------------------------------------------------------
+;; ---- [FP] VFWNMACC
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfwnmacc.vv
+;; -------------------------------------------------------------------------
+
+;; Combine ext + ext + fnms ===> widen fnms.
+;; Most of circumstantces, LoopVectorizer will generate the following IR:
+;; vect__8.176_40 = (vector([2,2]) double) vect__7.175_41;
+;; vect__11.180_35 = (vector([2,2]) double) vect__10.179_36;
+;; vect__13.182_33 = .FNMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
+(define_insn_and_split "*double_widen_fnms<mode>"
+ [(set (match_operand:VWEXTF 0 "register_operand")
+ (fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand"))))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_widen_mul_neg (MINUS, <MODE>mode),
+ riscv_vector::RVV_WIDEN_TERNOP, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; This helps to match ext + fnms.
+(define_insn_and_split "*single_widen_fnms<mode>"
+ [(set (match_operand:VWEXTF 0 "register_operand")
+ (fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
+ (match_operand:VWEXTF 3 "register_operand")
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand"))))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ insn_code icode = code_for_pred_extend (<MODE>mode);
+ rtx tmp = gen_reg_rtx (<MODE>mode);
+ rtx ext_ops[] = {tmp, operands[2]};
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ext_ops);
+
+ rtx dst = expand_ternary_op (<MODE>mode, fnms_optab, tmp, operands[3],
+ operands[1], operands[0], 0);
+ emit_move_insn (operands[0], dst);
+ DONE;
+ }
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
new file mode 100644
index 00000000000..490f1a41068
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwmacc_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \
+ TYPE2 *__restrict a, \
+ TYPE2 *__restrict b, \
+ int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] += -((TYPE1) a[i] * (TYPE1) b[i]); \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (float, _Float16) \
+ TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwnmsac\.vv} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
new file mode 100644
index 00000000000..4d44a40fed3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwmacc_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \
+ TYPE2 *__restrict a, \
+ TYPE2 *__restrict b, \
+ int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = (TYPE1) a[i] * (TYPE1) b[i] - dst[i]; \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (float, _Float16) \
+ TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwmsac\.vv} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
new file mode 100644
index 00000000000..2cb2a1edebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwmacc_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \
+ TYPE2 *__restrict a, \
+ TYPE2 *__restrict b, \
+ int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = -((TYPE1) a[i] * (TYPE1) b[i]) - dst[i]; \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (float, _Float16) \
+ TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwnmacc\.vv} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
new file mode 100644
index 00000000000..2e3f6664d93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \
+ TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \
+ TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \
+ TYPE2 *__restrict a2, TYPE2 *__restrict b2, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ { \
+ dst[i] += -((TYPE1) a[i] * (TYPE1) b[i]); \
+ dst2[i] += -((TYPE1) a2[i] * (TYPE1) b[i]); \
+ dst3[i] += -((TYPE1) a2[i] * (TYPE1) a[i]); \
+ dst4[i] += -((TYPE1) a[i] * (TYPE1) b2[i]); \
+ } \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (float, _Float16) \
+ TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwnmsac\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
new file mode 100644
index 00000000000..2acfbd01c6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \
+ TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \
+ TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \
+ TYPE2 *__restrict a2, TYPE2 *__restrict b2, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ { \
+ dst[i] = (TYPE1) a[i] * (TYPE1) b[i] - dst[i]; \
+ dst2[i] = (TYPE1) a2[i] * (TYPE1) b[i] - dst2[i]; \
+ dst3[i] = (TYPE1) a2[i] * (TYPE1) a[i] - dst3[i]; \
+ dst4[i] = (TYPE1) a[i] * (TYPE1) b2[i] - dst4[i]; \
+ } \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (float, _Float16) \
+ TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwmsac\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
new file mode 100644
index 00000000000..da7f870c12b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \
+ TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \
+ TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \
+ TYPE2 *__restrict a2, TYPE2 *__restrict b2, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ { \
+ dst[i] = -((TYPE1) a[i] * (TYPE1) b[i]) - dst[i]; \
+ dst2[i] = -((TYPE1) a2[i] * (TYPE1) b[i]) - dst2[i]; \
+ dst3[i] = -((TYPE1) a2[i] * (TYPE1) a[i]) - dst3[i]; \
+ dst4[i] = -((TYPE1) a[i] * (TYPE1) b2[i]) - dst4[i]; \
+ } \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (float, _Float16) \
+ TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwnmacc\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c
new file mode 100644
index 00000000000..262660c5bcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <assert.h>
+#include "widen-10.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ TYPE1 dst2##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ dst##TYPE1[i] = LIMIT + i & 628; \
+ dst2##TYPE1[i] = LIMIT + i & 628; \
+ } \
+ vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] \
+ == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) + dst2##TYPE1[i]);
+
+#define RUN_ALL() RUN (double, float, -2147483648)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c
new file mode 100644
index 00000000000..246999cab62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <assert.h>
+#include "widen-11.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ TYPE1 dst2##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ dst##TYPE1[i] = LIMIT + i & 628; \
+ dst2##TYPE1[i] = LIMIT + i & 628; \
+ } \
+ vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] \
+ == ((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]);
+
+#define RUN_ALL() RUN (double, float, -2147483648)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c
new file mode 100644
index 00000000000..2a6a03b5b35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <assert.h>
+#include "widen-12.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ TYPE1 dst2##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ dst##TYPE1[i] = LIMIT + i & 628; \
+ dst2##TYPE1[i] = LIMIT + i & 628; \
+ } \
+ vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] \
+ == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]);
+
+#define RUN_ALL() RUN (double, float, -2147483648)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
new file mode 100644
index 00000000000..f678c35f81f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <assert.h>
+#include "widen-10.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ TYPE1 dst2##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ dst##TYPE1[i] = LIMIT + i & 628; \
+ dst2##TYPE1[i] = LIMIT + i & 628; \
+ } \
+ vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] \
+ == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) + dst2##TYPE1[i]);
+
+#define RUN_ALL() RUN (float, _Float16, -32768)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
new file mode 100644
index 00000000000..294f77dbc46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <assert.h>
+#include "widen-11.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ TYPE1 dst2##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ dst##TYPE1[i] = LIMIT + i & 628; \
+ dst2##TYPE1[i] = LIMIT + i & 628; \
+ } \
+ vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] \
+ == ((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]);
+
+#define RUN_ALL() RUN (float, _Float16, -32768)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
new file mode 100644
index 00000000000..013291cdc60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <assert.h>
+#include "widen-12.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ TYPE1 dst2##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ dst##TYPE1[i] = LIMIT + i & 628; \
+ dst2##TYPE1[i] = LIMIT + i & 628; \
+ } \
+ vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] \
+ == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]);
+
+#define RUN_ALL() RUN (float, _Float16, -32768)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
--
2.36.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-28 11:55 [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering Juzhe-Zhong
@ 2023-06-28 18:16 ` Jeff Law
2023-06-28 22:10 ` 钟居哲
0 siblings, 1 reply; 13+ messages in thread
From: Jeff Law @ 2023-06-28 18:16 UTC (permalink / raw)
To: Juzhe-Zhong, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, rdapp.gcc
On 6/28/23 05:55, Juzhe-Zhong wrote:
> Similar to vfwmacc. Add combine patterns as follows:
>
> For vfwnmsac:
> 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (reg) )))
> 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (reg) )))
>
> For vfwmsac:
> 1. (set (reg) (fma (float_extend (reg)) (float_extend (reg))) (neg (reg)) )))
> 2. (set (reg) (fma (float_extend (reg)) (reg) (neg (reg)) )))
>
> For vfwnmacc:
> 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (neg (reg)) )))
> 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (neg (reg)) )))
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
> (*single_widen_fnma<mode>): Ditto.
> (*double_widen_fms<mode>): Ditto.
> (*single_widen_fms<mode>): Ditto.
> (*double_widen_fnms<mode>): Ditto.
> (*single_widen_fnms<mode>): Ditto.
>
> +
> +;; This helps to match ext + fnma.
> +(define_insn_and_split "*single_widen_fnma<mode>"
> + [(set (match_operand:VWEXTF 0 "register_operand")
> + (fma:VWEXTF
> + (neg:VWEXTF
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
> + (match_operand:VWEXTF 3 "register_operand")
> + (match_operand:VWEXTF 1 "register_operand")))]
I'd like to understand this better. It looks like it's meant to be a
bridge to another pattern. However, it looks like it would be a 4->1
pattern without needing a bridge. So I'd like to know why that code
isn't working.
Can you send the before/after combine dumps which show this bridge
pattern being used?
The same concern exists with the other bridge patterns, but I don't
think I need to see the before/after for each of them.
Thanks,
Jeff
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-28 18:16 ` Jeff Law
@ 2023-06-28 22:10 ` 钟居哲
2023-06-28 22:43 ` Jeff Law
0 siblings, 1 reply; 13+ messages in thread
From: 钟居哲 @ 2023-06-28 22:10 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: kito.cheng, kito.cheng, palmer, palmer, rdapp.gcc
[-- Attachment #1: Type: text/plain, Size: 2362 bytes --]
Sure.
https://godbolt.org/z/8857KzTno
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 171 [ vect__29.45 ])))
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-06-29 02:16
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
On 6/28/23 05:55, Juzhe-Zhong wrote:
> Similar to vfwmacc. Add combine patterns as follows:
>
> For vfwnmsac:
> 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (reg) )))
> 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (reg) )))
>
> For vfwmsac:
> 1. (set (reg) (fma (float_extend (reg)) (float_extend (reg))) (neg (reg)) )))
> 2. (set (reg) (fma (float_extend (reg)) (reg) (neg (reg)) )))
>
> For vfwnmacc:
> 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (neg (reg)) )))
> 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (neg (reg)) )))
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
> (*single_widen_fnma<mode>): Ditto.
> (*double_widen_fms<mode>): Ditto.
> (*single_widen_fms<mode>): Ditto.
> (*double_widen_fnms<mode>): Ditto.
> (*single_widen_fnms<mode>): Ditto.
>
> +
> +;; This helps to match ext + fnma.
> +(define_insn_and_split "*single_widen_fnma<mode>"
> + [(set (match_operand:VWEXTF 0 "register_operand")
> + (fma:VWEXTF
> + (neg:VWEXTF
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
> + (match_operand:VWEXTF 3 "register_operand")
> + (match_operand:VWEXTF 1 "register_operand")))]
I'd like to understand this better. It looks like it's meant to be a
bridge to another pattern. However, it looks like it would be a 4->1
pattern without needing a bridge. So I'd like to know why that code
isn't working.
Can you send the before/after combine dumps which show this bridge
pattern being used?
The same concern exists with the other bridge patterns, but I don't
think I need to see the before/after for each of them.
Thanks,
Jeff
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-28 22:10 ` 钟居哲
@ 2023-06-28 22:43 ` Jeff Law
2023-06-28 22:56 ` 钟居哲
0 siblings, 1 reply; 13+ messages in thread
From: Jeff Law @ 2023-06-28 22:43 UTC (permalink / raw)
To: 钟居哲, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, rdapp.gcc
On 6/28/23 16:10, 钟居哲 wrote:
> Sure.
>
> https://godbolt.org/z/8857KzTno <https://godbolt.org/z/8857KzTno>
>
> Failed to match this instruction:
> (set (reg:VNx2DF 134 [ vect__31.47 ])
> (fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [
> vect__28.44 ])))
> (reg:VNx2DF 150 [ vect__8.12 ])
> (reg:VNx2DF 171 [ vect__29.45 ])))
Please attach the full dump. I would expect to see additional attempts
with more operands replaced.
jeff
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-28 22:43 ` Jeff Law
@ 2023-06-28 22:56 ` 钟居哲
2023-06-29 23:43 ` Jeff Law
0 siblings, 1 reply; 13+ messages in thread
From: 钟居哲 @ 2023-06-28 22:56 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: kito.cheng, kito.cheng, palmer, palmer, rdapp.gcc
[-- Attachment #1.1: Type: text/plain, Size: 742 bytes --]
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-06-29 06:43
To: 钟居哲; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
On 6/28/23 16:10, 钟居哲 wrote:
> Sure.
>
> https://godbolt.org/z/8857KzTno <https://godbolt.org/z/8857KzTno>
>
> Failed to match this instruction:
> (set (reg:VNx2DF 134 [ vect__31.47 ])
> (fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [
> vect__28.44 ])))
> (reg:VNx2DF 150 [ vect__8.12 ])
> (reg:VNx2DF 171 [ vect__29.45 ])))
Please attach the full dump. I would expect to see additional attempts
with more operands replaced.
jeff
[-- Attachment #2: dump.txt --]
[-- Type: application/octet-stream, Size: 129467 bytes --]
;; Function vwadd_TYPE1_float (_Z17vwadd_TYPE1_floatPdS_S_S_PfS0_S0_S0_i, funcdef_no=0, decl_uid=2849, cgraph_uid=1, symbol_order=0)
scanning new insn with uid = 85.
rescanning insn with uid = 2.
scanning new insn with uid = 86.
rescanning insn with uid = 3.
scanning new insn with uid = 87.
rescanning insn with uid = 4.
scanning new insn with uid = 88.
rescanning insn with uid = 5.
scanning new insn with uid = 89.
rescanning insn with uid = 6.
scanning new insn with uid = 90.
rescanning insn with uid = 7.
scanning new insn with uid = 91.
rescanning insn with uid = 8.
scanning new insn with uid = 92.
rescanning insn with uid = 9.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 6 n_edges 7 count 7 ( 1.2)
vwadd_TYPE1_float
Dataflow summary:
def_info->table_size = 71, use_info->table_size = 0
;; fully invalidated by EH 0 [zero] 3 [gp] 4 [tp] 5 [t0] 6 [t1] 7 [t2] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 28 [t3] 29 [t4] 30 [t5] 31 [t6] 32 [ft0] 33 [ft1] 34 [ft2] 35 [ft3] 36 [ft4] 37 [ft5] 38 [ft6] 39 [ft7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6] 49 [fa7] 60 [ft8] 61 [ft9] 62 [ft10] 63 [ft11] 66 [vl] 67 [vtype] 68 [vxrm] 69 [N/A] 70 [N/A] 71 [N/A] 72 [N/A] 73 [N/A] 74 [N/A] 75 [N/A] 76 [N/A] 77 [N/A] 78 [N/A] 79 [N/A] 80 [N/A] 81 [N/A] 82 [N/A] 83 [N/A] 84 [N/A] 85 [N/A] 86 [N/A] 87 [N/A] 88 [N/A] 89 [N/A] 90 [N/A] 91 [N/A] 92 [N/A] 93 [N/A] 94 [N/A] 95 [N/A] 96 [v0] 97 [v1] 98 [v2] 99 [v3] 100 [v4] 101 [v5] 102 [v6] 103 [v7] 104 [v8] 105 [v9] 106 [v10] 107 [v11] 108 [v12] 109 [v13] 110 [v14] 111 [v15] 112 [v16] 113 [v17] 114 [v18] 115 [v19] 116 [v20] 117 [v21] 118 [v22] 119 [v23] 120 [v24] 121 [v25] 122 [v26] 123 [v27] 124 [v28] 125 [v29] 126 [v30] 127 [v31]
;; hardware regs used 2 [sp] 64 [arg] 65 [frame]
;; regular block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; eh block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; entry block defs 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; exit block uses 1 [ra] 2 [sp] 8 [s0] 65 [frame]
;; regs ever live 0 [zero] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 66 [vl] 67 [vtype]
;; ref usage r0={8u} r1={1d,1u} r2={1d,5u} r8={1d,5u} r10={1d,1u} r11={1d,1u} r12={1d,1u} r13={1d,1u} r14={1d,1u} r15={1d,1u} r16={1d,1u} r17={1d,1u} r42={1d} r43={1d} r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r64={1d,5u,1e} r65={1d,5u} r66={12u} r67={12u} r134={1d,1u} r136={1d,1u} r137={1d,1u} r138={2d,3u} r139={1d,1u} r140={1d,1u} r141={2d,3u} r142={1d,1u} r143={1d,2u} r144={1d,1u} r145={1d,1u} r146={2d,3u} r147={1d,1u} r148={1d,2u} r149={1d,1u} r150={1d,3u} r151={1d,1u} r152={1d,4u} r153={1d,1u} r154={1d,8u} r155={2d,3u} r156={2d,3u} r157={1d,15u} r158={2d,3u} r159={2d,3u} r160={2d,3u} r161={2d,3u} r162={2d,2u} r163={2d,2u} r164={2d,2u} r165={2d,2u} r166={1d,2u} r168={1d} r169={1d} r170={1d} r171={1d,1u} r172={1d} r173={1d,1u} r174={1d,1u} r175={1d,1u} r176={1d,1u} r177={1d,1u} r178={1d,1u} r179={1d,1u} r180={1d,1u}
;; total ref usage 233{79d,153u,1e} in 70{70 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(1){ }d1(2){ }d2(8){ }d3(10){ }d4(11){ }d5(12){ }d6(13){ }d7(14){ }d8(15){ }d9(16){ }d10(17){ }d11(42){ }d12(43){ }d13(44){ }d14(45){ }d15(46){ }d16(47){ }d17(48){ }d18(49){ }d19(64){ }d20(65){ }}
;; bb 0 artificial_uses: { }
;; lr in 0 [zero] 66 [vl] 67 [vtype]
;; lr use
;; lr def 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; live in
;; live gen 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; live kill
;; lr out 0 [zero] 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 64 [arg] 65 [frame] 66 [vl] 67 [vtype]
;; live out 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 64 [arg] 65 [frame]
( 0 )->[2]->( 3 5 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(2){ }u-1(8){ }u-1(64){ }u-1(65){ }}
;; lr in 0 [zero] 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 64 [arg] 65 [frame] 66 [vl] 67 [vtype]
;; lr use 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 64 [arg] 65 [frame]
;; lr def 158 159 160 161 162 163 164 165 166 173 174 175 176 177 178 179 180
;; live in 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 64 [arg] 65 [frame]
;; live gen 158 159 160 161 162 163 164 165 166
;; live kill
;; lr out 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 158 159 160 161 162 163 164 165 166
;; live out 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 158 159 160 161 162 163 164 165 166
( 2 )->[3]->( 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(2){ }u-1(8){ }u-1(64){ }u-1(65){ }}
;; lr in 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 158 159 160 161 162 163 164 165 166
;; lr use 2 [sp] 8 [s0] 64 [arg] 65 [frame] 158 159 160 161 166
;; lr def 138 141 146 155 156
;; live in 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 158 159 160 161 162 163 164 165 166
;; live gen 138 141 146 155 156
;; live kill
;; lr out 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 138 141 146 155 156 158 159 160 161 162 163 164 165
;; live out 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 138 141 146 155 156 158 159 160 161 162 163 164 165
( 4 3 )->[4]->( 4 5 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u-1(2){ }u-1(8){ }u-1(64){ }u-1(65){ }}
;; lr in 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 138 141 146 155 156 158 159 160 161 162 163 164 165
;; lr use 0 [zero] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 138 141 146 155 156 158 159 160 161 162 163 164 165
;; lr def 134 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 168 169 170 171 172
;; live in 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 138 141 146 155 156 158 159 160 161 162 163 164 165
;; live gen 134 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 171
;; live kill 168 169 170 172
;; lr out 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 138 141 146 155 156 158 159 160 161 162 163 164 165
;; live out 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 138 141 146 155 156 158 159 160 161 162 163 164 165
( 4 2 )->[5]->( 1 )
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(2){ }u-1(8){ }u-1(64){ }u-1(65){ }}
;; lr in 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; lr use 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; lr def
;; live in 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; live gen
;; live kill
;; lr out 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; live out 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame]
( 5 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u-1(1){ }u-1(2){ }u-1(8){ }u-1(65){ }}
;; lr in 1 [ra] 2 [sp] 8 [s0] 65 [frame]
;; lr use 1 [ra] 2 [sp] 8 [s0] 65 [frame]
;; lr def
;; live in 1 [ra] 2 [sp] 8 [s0] 65 [frame]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 24 to worklist
Adding insn 72 to worklist
Adding insn 54 to worklist
Adding insn 48 to worklist
Adding insn 44 to worklist
Adding insn 38 to worklist
Finished finding needed instructions:
processing block 5 lr out = 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame]
processing block 4 lr out = 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 138 141 146 155 156 158 159 160 161 162 163 164 165
Adding insn 70 to worklist
Adding insn 69 to worklist
Adding insn 68 to worklist
Adding insn 67 to worklist
Adding insn 66 to worklist
Adding insn 65 to worklist
Adding insn 64 to worklist
Adding insn 63 to worklist
Adding insn 62 to worklist
Adding insn 61 to worklist
Adding insn 60 to worklist
Adding insn 59 to worklist
Adding insn 58 to worklist
Adding insn 53 to worklist
Adding insn 52 to worklist
Adding insn 51 to worklist
Adding insn 50 to worklist
Adding insn 47 to worklist
Adding insn 46 to worklist
Adding insn 43 to worklist
Adding insn 42 to worklist
Adding insn 41 to worklist
Adding insn 40 to worklist
Adding insn 37 to worklist
Adding insn 36 to worklist
Adding insn 35 to worklist
Adding insn 34 to worklist
Adding insn 33 to worklist
Adding insn 32 to worklist
Adding insn 31 to worklist
Adding insn 30 to worklist
Adding insn 28 to worklist
processing block 3 lr out = 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 138 141 146 155 156 158 159 160 161 162 163 164 165
Adding insn 15 to worklist
Adding insn 14 to worklist
Adding insn 13 to worklist
Adding insn 12 to worklist
Adding insn 26 to worklist
processing block 2 lr out = 0 [zero] 1 [ra] 2 [sp] 8 [s0] 64 [arg] 65 [frame] 66 [vl] 67 [vtype] 158 159 160 161 162 163 164 165 166
Adding insn 10 to worklist
Adding insn 9 to worklist
Adding insn 92 to worklist
Adding insn 8 to worklist
Adding insn 91 to worklist
Adding insn 7 to worklist
Adding insn 90 to worklist
Adding insn 6 to worklist
Adding insn 89 to worklist
Adding insn 5 to worklist
Adding insn 88 to worklist
Adding insn 4 to worklist
Adding insn 87 to worklist
Adding insn 3 to worklist
Adding insn 86 to worklist
Adding insn 2 to worklist
Adding insn 85 to worklist
df_worklist_dataflow_doublequeue: n_basic_blocks 6 n_edges 7 count 7 ( 1.2)
insn_cost 4 for 85: r173:DI=a0:DI
REG_DEAD a0:DI
insn_cost 4 for 2: r158:DI=r173:DI
REG_DEAD r173:DI
insn_cost 4 for 86: r174:DI=a1:DI
REG_DEAD a1:DI
insn_cost 4 for 3: r159:DI=r174:DI
REG_DEAD r174:DI
insn_cost 4 for 87: r175:DI=a2:DI
REG_DEAD a2:DI
insn_cost 4 for 4: r160:DI=r175:DI
REG_DEAD r175:DI
insn_cost 4 for 88: r176:DI=a3:DI
REG_DEAD a3:DI
insn_cost 4 for 5: r161:DI=r176:DI
REG_DEAD r176:DI
insn_cost 4 for 89: r177:DI=a4:DI
REG_DEAD a4:DI
insn_cost 4 for 6: r162:DI=r177:DI
REG_DEAD r177:DI
insn_cost 4 for 90: r178:DI=a5:DI
REG_DEAD a5:DI
insn_cost 4 for 7: r163:DI=r178:DI
REG_DEAD r178:DI
insn_cost 4 for 91: r179:DI=a6:DI
REG_DEAD a6:DI
insn_cost 4 for 8: r164:DI=r179:DI
REG_DEAD r179:DI
insn_cost 4 for 92: r180:DI=a7:DI
REG_DEAD a7:DI
insn_cost 4 for 9: r165:DI=r180:DI
REG_DEAD r180:DI
insn_cost 28 for 10: r166:DI=sign_extend([arg:DI])
REG_EQUIV sign_extend([arg:DI])
insn_cost 0 for 18: debug begin stmt marker
insn_cost 0 for 19: debug i => 0
insn_cost 0 for 20: debug begin stmt marker
insn_cost 4 for 24: pc={(r166:DI<=0)?L76:pc}
REG_BR_PROB 118111604
insn_cost 4 for 26: r156:DI=r166:DI
REG_DEAD r166:DI
insn_cost 4 for 12: r155:DI=r161:DI
insn_cost 4 for 13: r138:DI=r160:DI
insn_cost 4 for 14: r141:DI=r159:DI
insn_cost 4 for 15: r146:DI=r158:DI
insn_cost 12 for 28: r157:DI=unspec[r156:DI,0x8,0x5,0,0] 67
insn_cost 0 for 29: debug begin stmt marker
insn_cost 4 for 30: r154:DI=r157:DI<<0x3
insn_cost 4 for 31: r153:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r158:DI]:unspec[zero:SI] 68}
insn_cost 4 for 32: r152:DI=r157:DI<<0x2
insn_cost 4 for 33: r151:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r162:DI]:unspec[zero:SI] 68}
insn_cost 4 for 34: r150:VNx2DF=float_extend(r151:VNx2SF)
REG_DEAD r151:VNx2SF
insn_cost 4 for 35: r149:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r163:DI]:unspec[zero:SI] 68}
insn_cost 4 for 36: r148:VNx2DF=float_extend(r149:VNx2SF)
REG_DEAD r149:VNx2SF
insn_cost 4 for 37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
insn_cost 4 for 38: [r146:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r147:VNx2DF:[r146:DI]}
REG_DEAD r147:VNx2DF
insn_cost 0 for 39: debug begin stmt marker
insn_cost 4 for 40: r145:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r159:DI]:unspec[zero:SI] 68}
insn_cost 4 for 41: r144:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r164:DI]:unspec[zero:SI] 68}
insn_cost 4 for 42: r143:VNx2DF=float_extend(r144:VNx2SF)
REG_DEAD r144:VNx2SF
insn_cost 4 for 43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
insn_cost 4 for 44: [r141:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r142:VNx2DF:[r141:DI]}
REG_DEAD r142:VNx2DF
insn_cost 0 for 45: debug begin stmt marker
insn_cost 4 for 46: r140:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r160:DI]:unspec[zero:SI] 68}
insn_cost 4 for 47: {r139:VNx2DF={-r143:VNx2DF*r150:VNx2DF+r140:VNx2DF};clobber r170:DI;}
REG_DEAD r143:VNx2DF
REG_DEAD r140:VNx2DF
REG_UNUSED r170:DI
insn_cost 4 for 48: [r138:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r139:VNx2DF:[r138:DI]}
REG_DEAD r139:VNx2DF
insn_cost 0 for 49: debug begin stmt marker
insn_cost 4 for 50: r137:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r161:DI]:unspec[zero:SI] 68}
insn_cost 4 for 51: r136:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r165:DI]:unspec[zero:SI] 68}
REG_DEAD zero:SI
insn_cost 4 for 52: r171:VNx2DF=float_extend(r136:VNx2SF)
REG_DEAD r136:VNx2SF
insn_cost 4 for 53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
insn_cost 4 for 54: [r155:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r134:VNx2DF:[r155:DI]}
REG_DEAD r134:VNx2DF
REG_DEAD vtype:SI
REG_DEAD vl:SI
insn_cost 0 for 55: debug begin stmt marker
insn_cost 0 for 56: debug i => optimized away
insn_cost 0 for 57: debug begin stmt marker
insn_cost 4 for 58: r158:DI=r158:DI+r154:DI
insn_cost 4 for 59: r162:DI=r162:DI+r152:DI
insn_cost 4 for 60: r163:DI=r163:DI+r152:DI
insn_cost 4 for 61: r146:DI=r146:DI+r154:DI
insn_cost 4 for 62: r159:DI=r159:DI+r154:DI
insn_cost 4 for 63: r164:DI=r164:DI+r152:DI
insn_cost 4 for 64: r141:DI=r141:DI+r154:DI
insn_cost 4 for 65: r160:DI=r160:DI+r154:DI
insn_cost 4 for 66: r138:DI=r138:DI+r154:DI
insn_cost 4 for 67: r161:DI=r161:DI+r154:DI
insn_cost 4 for 68: r165:DI=r165:DI+r152:DI
REG_DEAD r152:DI
insn_cost 4 for 69: r155:DI=r155:DI+r154:DI
REG_DEAD r154:DI
insn_cost 4 for 70: r156:DI=r156:DI-r157:DI
REG_DEAD r157:DI
insn_cost 4 for 72: pc={(r156:DI!=0)?L71:pc}
REG_BR_PROB 894784862
Trying 10 -> 24:
10: r166:DI=sign_extend([arg:DI])
REG_EQUIV sign_extend([arg:DI])
24: pc={(r166:DI<=0)?L76:pc}
REG_BR_PROB 118111604
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (le (subreg:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]) 0)
(const_int 0 [0]))
(label_ref:DI 76)
(pc)))
(set (reg/v:DI 166 [ n ])
(sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128])))
])
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (le (subreg:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]) 0)
(const_int 0 [0]))
(label_ref:DI 76)
(pc)))
(set (reg/v:DI 166 [ n ])
(sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128])))
])
Successfully matched this instruction:
(set (reg/v:DI 166 [ n ])
(sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128])))
Failed to match this instruction:
(set (pc)
(if_then_else (le (subreg:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]) 0)
(const_int 0 [0]))
(label_ref:DI 76)
(pc)))
Trying 10 -> 24:
10: r166:DI=sign_extend([arg:DI])
REG_EQUIV sign_extend([arg:DI])
24: pc={(r166:DI<=0)?L76:pc}
REG_BR_PROB 118111604
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (le (subreg:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]) 0)
(const_int 0 [0]))
(label_ref:DI 76)
(pc)))
(set (reg/v:DI 166 [ n ])
(sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128])))
])
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (le (subreg:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]) 0)
(const_int 0 [0]))
(label_ref:DI 76)
(pc)))
(set (reg/v:DI 166 [ n ])
(sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128])))
])
Successfully matched this instruction:
(set (reg/v:DI 166 [ n ])
(sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128])))
Failed to match this instruction:
(set (pc)
(if_then_else (le (subreg:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]) 0)
(const_int 0 [0]))
(label_ref:DI 76)
(pc)))
Trying 28 -> 30:
28: r157:DI=unspec[r156:DI,0x8,0x5,0,0] 67
30: r154:DI=r157:DI<<0x3
Failed to match this instruction:
(parallel [
(set (reg:DI 154 [ ivtmp_105 ])
(ashift:DI (unspec:DI [
(reg:DI 156 [ ivtmp_115 ])
(const_int 8 [0x8])
(const_int 5 [0x5])
(const_int 0 [0]) repeated x2
] UNSPEC_VSETVL)
(const_int 3 [0x3])))
(set (reg:DI 157 [ _117 ])
(unspec:DI [
(reg:DI 156 [ ivtmp_115 ])
(const_int 8 [0x8])
(const_int 5 [0x5])
(const_int 0 [0]) repeated x2
] UNSPEC_VSETVL))
])
Failed to match this instruction:
(parallel [
(set (reg:DI 154 [ ivtmp_105 ])
(ashift:DI (unspec:DI [
(reg:DI 156 [ ivtmp_115 ])
(const_int 8 [0x8])
(const_int 5 [0x5])
(const_int 0 [0]) repeated x2
] UNSPEC_VSETVL)
(const_int 3 [0x3])))
(set (reg:DI 157 [ _117 ])
(unspec:DI [
(reg:DI 156 [ ivtmp_115 ])
(const_int 8 [0x8])
(const_int 5 [0x5])
(const_int 0 [0]) repeated x2
] UNSPEC_VSETVL))
])
Successfully matched this instruction:
(set (reg:DI 157 [ _117 ])
(unspec:DI [
(reg:DI 156 [ ivtmp_115 ])
(const_int 8 [0x8])
(const_int 5 [0x5])
(const_int 0 [0]) repeated x2
] UNSPEC_VSETVL))
Failed to match this instruction:
(set (reg:DI 154 [ ivtmp_105 ])
(ashift:DI (unspec:DI [
(reg:DI 156 [ ivtmp_115 ])
(const_int 8 [0x8])
(const_int 5 [0x5])
(const_int 0 [0]) repeated x2
] UNSPEC_VSETVL)
(const_int 3 [0x3])))
Trying 33 -> 34:
33: r151:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r162:DI]:unspec[zero:SI] 68}
34: r150:VNx2DF=float_extend(r151:VNx2SF)
REG_DEAD r151:VNx2SF
Failed to match this instruction:
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 162 [ a ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a.9_100]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 35 -> 36:
35: r149:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r163:DI]:unspec[zero:SI] 68}
36: r148:VNx2DF=float_extend(r149:VNx2SF)
REG_DEAD r149:VNx2SF
Failed to match this instruction:
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 163 [ b ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b.13_95]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 31 -> 37:
31: r153:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r158:DI]:unspec[zero:SI] 68}
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 168))
])
Failed to match this instruction:
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 34 -> 37:
34: r150:VNx2DF=float_extend(r151:VNx2SF)
REG_DEAD r151:VNx2SF
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ])))
(clobber (reg:DI 168))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ])))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
Failed to match this instruction:
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ])))
Trying 36 -> 37:
36: r148:VNx2DF=float_extend(r149:VNx2SF)
REG_DEAD r149:VNx2SF
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ])))
(clobber (reg:DI 168))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ])))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
Failed to match this instruction:
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ])))
Trying 33, 34 -> 37:
33: r151:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r162:DI]:unspec[zero:SI] 68}
34: r150:VNx2DF=float_extend(r151:VNx2SF)
REG_DEAD r151:VNx2SF
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 162 [ a ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a.9_100]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
(reg:VNx2DF 153 [ vect__4.8 ])))
(clobber (reg:DI 168))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 162 [ a ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a.9_100]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 162 [ a ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a.9_100]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
(reg:VNx2DF 153 [ vect__4.8 ])))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 162 [ a ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a.9_100]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
])
Failed to match this instruction:
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 162 [ a ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a.9_100]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 35, 36 -> 37:
35: r149:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r163:DI]:unspec[zero:SI] 68}
36: r148:VNx2DF=float_extend(r149:VNx2SF)
REG_DEAD r149:VNx2SF
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 163 [ b ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b.13_95]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ])))
(clobber (reg:DI 168))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 163 [ b ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b.13_95]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 163 [ b ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b.13_95]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ])))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 163 [ b ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b.13_95]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
])
Failed to match this instruction:
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 163 [ b ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b.13_95]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 34, 31 -> 37:
34: r150:VNx2DF=float_extend(r151:VNx2SF)
REG_DEAD r151:VNx2SF
31: r153:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r158:DI]:unspec[zero:SI] 68}
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 168))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
Failed to match this instruction:
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 36, 31 -> 37:
36: r148:VNx2DF=float_extend(r149:VNx2SF)
REG_DEAD r149:VNx2SF
31: r153:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r158:DI]:unspec[zero:SI] 68}
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 168))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
Failed to match this instruction:
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 36, 34 -> 37:
36: r148:VNx2DF=float_extend(r149:VNx2SF)
REG_DEAD r149:VNx2SF
34: r150:VNx2DF=float_extend(r151:VNx2SF)
REG_DEAD r151:VNx2SF
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ])))
(clobber (reg:DI 168))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ])))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Trying 37 -> 38:
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
38: [r146:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r147:VNx2DF:[r146:DI]}
REG_DEAD r147:VNx2DF
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
Trying 31, 37 -> 38:
31: r153:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r158:DI]:unspec[zero:SI] 68}
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
38: [r146:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r147:VNx2DF:[r146:DI]}
REG_DEAD r147:VNx2DF
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
Successfully matched this instruction:
(set (reg:VNx2DF 147 [ vect__13.18 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 147 [ vect__13.18 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
Trying 34, 37 -> 38:
34: r150:VNx2DF=float_extend(r151:VNx2SF)
REG_DEAD r151:VNx2SF
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
38: [r146:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r147:VNx2DF:[r146:DI]}
REG_DEAD r147:VNx2DF
Failed to match this instruction:
(parallel [
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Failed to match this instruction:
(parallel [
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ])))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))
(reg:VNx2DF 153 [ vect__4.8 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
Trying 36, 37 -> 38:
36: r148:VNx2DF=float_extend(r149:VNx2SF)
REG_DEAD r149:VNx2SF
37: {r147:VNx2DF={-r148:VNx2DF*r150:VNx2DF+r153:VNx2DF};clobber r168:DI;}
REG_DEAD r153:VNx2DF
REG_UNUSED r168:DI
38: [r146:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r147:VNx2DF:[r146:DI]}
REG_DEAD r147:VNx2DF
Failed to match this instruction:
(parallel [
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
])
Failed to match this instruction:
(parallel [
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ]))
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])))
Trying 41 -> 42:
41: r144:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r164:DI]:unspec[zero:SI] 68}
42: r143:VNx2DF=float_extend(r144:VNx2SF)
REG_DEAD r144:VNx2SF
Failed to match this instruction:
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 164 [ a2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a2.24_80]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 40 -> 43:
40: r145:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r159:DI]:unspec[zero:SI] 68}
43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 148 [ vect__11.16 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 169))
])
Failed to match this instruction:
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 148 [ vect__11.16 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 42 -> 43:
42: r143:VNx2DF=float_extend(r144:VNx2SF)
REG_DEAD r144:VNx2SF
43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ])))
(clobber (reg:DI 169))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ])))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
Failed to match this instruction:
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ])))
Trying 41, 42 -> 43:
41: r144:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r164:DI]:unspec[zero:SI] 68}
42: r143:VNx2DF=float_extend(r144:VNx2SF)
REG_DEAD r144:VNx2SF
43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 164 [ a2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a2.24_80]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ])))
(clobber (reg:DI 169))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 164 [ a2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a2.24_80]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 164 [ a2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a2.24_80]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ])))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 164 [ a2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a2.24_80]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
])
Failed to match this instruction:
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 164 [ a2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a2.24_80]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 42, 40 -> 43:
42: r143:VNx2DF=float_extend(r144:VNx2SF)
REG_DEAD r144:VNx2SF
40: r145:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r159:DI]:unspec[zero:SI] 68}
43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 169))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
])
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
Failed to match this instruction:
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 43 -> 44:
43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
44: [r141:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r142:VNx2DF:[r141:DI]}
REG_DEAD r142:VNx2DF
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ]))
(mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])))
Trying 40, 43 -> 44:
40: r145:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r159:DI]:unspec[zero:SI] 68}
43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
44: [r141:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r142:VNx2DF:[r141:DI]}
REG_DEAD r142:VNx2DF
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 148 [ vect__11.16 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
(mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])))
Successfully matched this instruction:
(set (reg:VNx2DF 142 [ vect__20.29 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 142 [ vect__20.29 ]))
(mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])))
Trying 42, 43 -> 44:
42: r143:VNx2DF=float_extend(r144:VNx2SF)
REG_DEAD r144:VNx2SF
43: {r142:VNx2DF={-r143:VNx2DF*r148:VNx2DF+r145:VNx2DF};clobber r169:DI;}
REG_DEAD r148:VNx2DF
REG_DEAD r145:VNx2DF
REG_UNUSED r169:DI
44: [r141:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r142:VNx2DF:[r141:DI]}
REG_DEAD r142:VNx2DF
Failed to match this instruction:
(parallel [
(set (mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ]))
(mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
])
Failed to match this instruction:
(parallel [
(set (mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ]))
(mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])))
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
])
Successfully matched this instruction:
(set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ])))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ]))
(mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])))
Trying 46 -> 47:
46: r140:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r160:DI]:unspec[zero:SI] 68}
47: {r139:VNx2DF={-r143:VNx2DF*r150:VNx2DF+r140:VNx2DF};clobber r170:DI;}
REG_DEAD r143:VNx2DF
REG_DEAD r140:VNx2DF
REG_UNUSED r170:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 139 [ vect__24.36 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 160 [ dst3 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.32_69]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 170))
])
Failed to match this instruction:
(set (reg:VNx2DF 139 [ vect__24.36 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 160 [ dst3 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.32_69]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 47 -> 48:
47: {r139:VNx2DF={-r143:VNx2DF*r150:VNx2DF+r140:VNx2DF};clobber r170:DI;}
REG_DEAD r143:VNx2DF
REG_DEAD r140:VNx2DF
REG_UNUSED r170:DI
48: [r138:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r139:VNx2DF:[r138:DI]}
REG_DEAD r139:VNx2DF
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 140 [ vect__22.34 ]))
(mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64])))
Trying 46, 47 -> 48:
46: r140:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r160:DI]:unspec[zero:SI] 68}
47: {r139:VNx2DF={-r143:VNx2DF*r150:VNx2DF+r140:VNx2DF};clobber r170:DI;}
REG_DEAD r143:VNx2DF
REG_DEAD r140:VNx2DF
REG_UNUSED r170:DI
48: [r138:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r139:VNx2DF:[r138:DI]}
REG_DEAD r139:VNx2DF
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 160 [ dst3 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.32_69]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
(mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64])))
Successfully matched this instruction:
(set (reg:VNx2DF 139 [ vect__24.36 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 160 [ dst3 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.32_69]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 139 [ vect__24.36 ]))
(mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64])))
Trying 51 -> 52:
51: r136:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r165:DI]:unspec[zero:SI] 68}
REG_DEAD zero:SI
52: r171:VNx2DF=float_extend(r136:VNx2SF)
REG_DEAD r136:VNx2SF
Failed to match this instruction:
(set (reg:VNx2DF 171 [ vect__29.45 ])
(float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 165 [ b2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b2.42_55]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 50 -> 53:
50: r137:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r161:DI]:unspec[zero:SI] 68}
53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 171 [ vect__29.45 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 172))
])
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 171 [ vect__29.45 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Trying 52 -> 53:
52: r171:VNx2DF=float_extend(r136:VNx2SF)
REG_DEAD r136:VNx2SF
53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ])))
(clobber (reg:DI 172))
])
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ])))
Trying 51, 52 -> 53:
51: r136:VNx2SF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r165:DI]:unspec[zero:SI] 68}
REG_DEAD zero:SI
52: r171:VNx2DF=float_extend(r136:VNx2SF)
REG_DEAD r136:VNx2SF
53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 165 [ b2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b2.42_55]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ])))
(clobber (reg:DI 172))
])
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 165 [ b2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b2.42_55]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ])))
Successfully matched this instruction:
(set (reg:VNx2SF 171 [ vect__29.45 ])
(if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 165 [ b2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b2.42_55]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 171 [ vect__29.45 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ])))
Trying 52, 50 -> 53:
52: r171:VNx2DF=float_extend(r136:VNx2SF)
REG_DEAD r136:VNx2SF
50: r137:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r161:DI]:unspec[zero:SI] 68}
53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
Failed to match this instruction:
(parallel [
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
(clobber (reg:DI 172))
])
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))))
Successfully matched this instruction:
(set (reg:VNx2DF 171 [ vect__29.45 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 171 [ vect__29.45 ])))
Trying 53 -> 54:
53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
54: [r155:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r134:VNx2DF:[r155:DI]}
REG_DEAD r134:VNx2DF
REG_DEAD vtype:SI
REG_DEAD vl:SI
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 171 [ vect__29.45 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ]))
(mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])))
Trying 50, 53 -> 54:
50: r137:VNx2DF={(unspec[const_vector,r157:DI,0x2,0x2,0,vl:SI,vtype:SI] 69)?[r161:DI]:unspec[zero:SI] 68}
53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
54: [r155:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r134:VNx2DF:[r155:DI]}
REG_DEAD r134:VNx2DF
REG_DEAD vtype:SI
REG_DEAD vl:SI
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 171 [ vect__29.45 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
(mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])))
Successfully matched this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 171 [ vect__29.45 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 134 [ vect__31.47 ]))
(mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])))
Trying 52, 53 -> 54:
52: r171:VNx2DF=float_extend(r136:VNx2SF)
REG_DEAD r136:VNx2SF
53: {r134:VNx2DF={-r171:VNx2DF*r150:VNx2DF+r137:VNx2DF};clobber r172:DI;}
REG_DEAD r171:VNx2DF
REG_DEAD r150:VNx2DF
REG_DEAD r137:VNx2DF
REG_UNUSED r172:DI
54: [r155:DI]={(unspec[const_vector,r157:DI,0,vl:SI,vtype:SI] 69)?r134:VNx2DF:[r155:DI]}
REG_DEAD r134:VNx2DF
REG_DEAD vtype:SI
REG_DEAD vl:SI
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ]))
(mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])))
Successfully matched this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
Failed to match this instruction:
(set (mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 134 [ vect__31.47 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ]))
(mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])))
Trying 30 -> 58:
30: r154:DI=r157:DI<<0x3
58: r158:DI=r158:DI+r154:DI
Failed to match this instruction:
(parallel [
(set (reg/v/f:DI 158 [ dst ])
(plus:DI (ashift:DI (reg:DI 157 [ _117 ])
(const_int 3 [0x3]))
(reg/v/f:DI 158 [ dst ])))
(set (reg:DI 154 [ ivtmp_105 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 3 [0x3])))
])
Failed to match this instruction:
(parallel [
(set (reg/v/f:DI 158 [ dst ])
(plus:DI (ashift:DI (reg:DI 157 [ _117 ])
(const_int 3 [0x3]))
(reg/v/f:DI 158 [ dst ])))
(set (reg:DI 154 [ ivtmp_105 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 3 [0x3])))
])
Successfully matched this instruction:
(set (reg:DI 154 [ ivtmp_105 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 3 [0x3])))
Failed to match this instruction:
(set (reg/v/f:DI 158 [ dst ])
(plus:DI (ashift:DI (reg:DI 157 [ _117 ])
(const_int 3 [0x3]))
(reg/v/f:DI 158 [ dst ])))
Trying 28, 30 -> 58:
28: r157:DI=unspec[r156:DI,0x8,0x5,0,0] 67
30: r154:DI=r157:DI<<0x3
58: r158:DI=r158:DI+r154:DI
Can't combine i1 into i3
Trying 32 -> 59:
32: r152:DI=r157:DI<<0x2
59: r162:DI=r162:DI+r152:DI
Failed to match this instruction:
(parallel [
(set (reg/v/f:DI 162 [ a ])
(plus:DI (ashift:DI (reg:DI 157 [ _117 ])
(const_int 2 [0x2]))
(reg/v/f:DI 162 [ a ])))
(set (reg:DI 152 [ ivtmp_101 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 2 [0x2])))
])
Failed to match this instruction:
(parallel [
(set (reg/v/f:DI 162 [ a ])
(plus:DI (ashift:DI (reg:DI 157 [ _117 ])
(const_int 2 [0x2]))
(reg/v/f:DI 162 [ a ])))
(set (reg:DI 152 [ ivtmp_101 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 2 [0x2])))
])
Successfully matched this instruction:
(set (reg:DI 152 [ ivtmp_101 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 2 [0x2])))
Failed to match this instruction:
(set (reg/v/f:DI 162 [ a ])
(plus:DI (ashift:DI (reg:DI 157 [ _117 ])
(const_int 2 [0x2]))
(reg/v/f:DI 162 [ a ])))
Trying 70 -> 72:
70: r156:DI=r156:DI-r157:DI
REG_DEAD r157:DI
72: pc={(r156:DI!=0)?L71:pc}
REG_BR_PROB 894784862
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (ne (reg:DI 156 [ ivtmp_115 ])
(reg:DI 157 [ _117 ]))
(label_ref:DI 71)
(pc)))
(set (reg:DI 156 [ ivtmp_115 ])
(minus:DI (reg:DI 156 [ ivtmp_115 ])
(reg:DI 157 [ _117 ])))
])
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (ne (reg:DI 156 [ ivtmp_115 ])
(reg:DI 157 [ _117 ]))
(label_ref:DI 71)
(pc)))
(set (reg:DI 156 [ ivtmp_115 ])
(minus:DI (reg:DI 156 [ ivtmp_115 ])
(reg:DI 157 [ _117 ])))
])
starting the processing of deferred insns
ending the processing of deferred insns
vwadd_TYPE1_float
Dataflow summary:
;; fully invalidated by EH 0 [zero] 3 [gp] 4 [tp] 5 [t0] 6 [t1] 7 [t2] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 28 [t3] 29 [t4] 30 [t5] 31 [t6] 32 [ft0] 33 [ft1] 34 [ft2] 35 [ft3] 36 [ft4] 37 [ft5] 38 [ft6] 39 [ft7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6] 49 [fa7] 60 [ft8] 61 [ft9] 62 [ft10] 63 [ft11] 66 [vl] 67 [vtype] 68 [vxrm] 69 [N/A] 70 [N/A] 71 [N/A] 72 [N/A] 73 [N/A] 74 [N/A] 75 [N/A] 76 [N/A] 77 [N/A] 78 [N/A] 79 [N/A] 80 [N/A] 81 [N/A] 82 [N/A] 83 [N/A] 84 [N/A] 85 [N/A] 86 [N/A] 87 [N/A] 88 [N/A] 89 [N/A] 90 [N/A] 91 [N/A] 92 [N/A] 93 [N/A] 94 [N/A] 95 [N/A] 96 [v0] 97 [v1] 98 [v2] 99 [v3] 100 [v4] 101 [v5] 102 [v6] 103 [v7] 104 [v8] 105 [v9] 106 [v10] 107 [v11] 108 [v12] 109 [v13] 110 [v14] 111 [v15] 112 [v16] 113 [v17] 114 [v18] 115 [v19] 116 [v20] 117 [v21] 118 [v22] 119 [v23] 120 [v24] 121 [v25] 122 [v26] 123 [v27] 124 [v28] 125 [v29] 126 [v30] 127 [v31]
;; hardware regs used 2 [sp] 64 [arg] 65 [frame]
;; regular block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; eh block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; entry block defs 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; exit block uses 1 [ra] 2 [sp] 8 [s0] 65 [frame]
;; regs ever live 0 [zero] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 66 [vl] 67 [vtype]
;; ref usage r0={8u} r1={1d,1u} r2={1d,5u} r8={1d,5u} r10={1d,1u} r11={1d,1u} r12={1d,1u} r13={1d,1u} r14={1d,1u} r15={1d,1u} r16={1d,1u} r17={1d,1u} r42={1d} r43={1d} r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r64={1d,5u,1e} r65={1d,5u} r66={12u} r67={12u} r134={1d,1u} r136={1d,1u} r137={1d,1u} r138={2d,3u} r139={1d,1u} r140={1d,1u} r141={2d,3u} r142={1d,1u} r143={1d,2u} r144={1d,1u} r145={1d,1u} r146={2d,3u} r147={1d,1u} r148={1d,2u} r149={1d,1u} r150={1d,3u} r151={1d,1u} r152={1d,4u} r153={1d,1u} r154={1d,8u} r155={2d,3u} r156={2d,3u} r157={1d,15u} r158={2d,3u} r159={2d,3u} r160={2d,3u} r161={2d,3u} r162={2d,2u} r163={2d,2u} r164={2d,2u} r165={2d,2u} r166={1d,2u} r168={1d} r169={1d} r170={1d} r171={1d,1u} r172={1d} r173={1d,1u} r174={1d,1u} r175={1d,1u} r176={1d,1u} r177={1d,1u} r178={1d,1u} r179={1d,1u} r180={1d,1u}
;; total ref usage 233{79d,153u,1e} in 70{70 regular + 0 call} insns.
(note 16 0 85 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 85 16 2 2 (set (reg:DI 173)
(reg:DI 10 a0 [ dst ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 10 a0 [ dst ])
(nil)))
(insn 2 85 86 2 (set (reg/v/f:DI 158 [ dst ])
(reg:DI 173)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 173)
(nil)))
(insn 86 2 3 2 (set (reg:DI 174)
(reg:DI 11 a1 [ dst2 ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 11 a1 [ dst2 ])
(nil)))
(insn 3 86 87 2 (set (reg/v/f:DI 159 [ dst2 ])
(reg:DI 174)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 174)
(nil)))
(insn 87 3 4 2 (set (reg:DI 175)
(reg:DI 12 a2 [ dst3 ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 12 a2 [ dst3 ])
(nil)))
(insn 4 87 88 2 (set (reg/v/f:DI 160 [ dst3 ])
(reg:DI 175)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 175)
(nil)))
(insn 88 4 5 2 (set (reg:DI 176)
(reg:DI 13 a3 [ dst4 ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 13 a3 [ dst4 ])
(nil)))
(insn 5 88 89 2 (set (reg/v/f:DI 161 [ dst4 ])
(reg:DI 176)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 176)
(nil)))
(insn 89 5 6 2 (set (reg:DI 177)
(reg:DI 14 a4 [ a ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 14 a4 [ a ])
(nil)))
(insn 6 89 90 2 (set (reg/v/f:DI 162 [ a ])
(reg:DI 177)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 177)
(nil)))
(insn 90 6 7 2 (set (reg:DI 178)
(reg:DI 15 a5 [ b ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 15 a5 [ b ])
(nil)))
(insn 7 90 91 2 (set (reg/v/f:DI 163 [ b ])
(reg:DI 178)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 178)
(nil)))
(insn 91 7 8 2 (set (reg:DI 179)
(reg:DI 16 a6 [ a2 ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 16 a6 [ a2 ])
(nil)))
(insn 8 91 92 2 (set (reg/v/f:DI 164 [ a2 ])
(reg:DI 179)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 179)
(nil)))
(insn 92 8 9 2 (set (reg:DI 180)
(reg:DI 17 a7 [ b2 ])) "/app/example.cpp":17:1 -1
(expr_list:REG_DEAD (reg:DI 17 a7 [ b2 ])
(nil)))
(insn 9 92 10 2 (set (reg/v/f:DI 165 [ b2 ])
(reg:DI 180)) "/app/example.cpp":17:1 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 180)
(nil)))
(insn 10 9 11 2 (set (reg/v:DI 166 [ n ])
(sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]))) "/app/example.cpp":17:1 -1
(expr_list:REG_EQUIV (sign_extend:DI (mem/c:SI (reg/f:DI 64 arg) [3 n+0 S4 A128]))
(nil)))
(note 11 10 18 2 NOTE_INSN_FUNCTION_BEG)
(debug_insn 18 11 19 2 (debug_marker) "/app/example.cpp":17:1 -1
(nil))
(debug_insn 19 18 20 2 (var_location:SI i (const_int 0 [0])) -1
(nil))
(debug_insn 20 19 24 2 (debug_marker) "/app/example.cpp":17:1 discrim 1 -1
(nil))
(jump_insn 24 20 25 2 (set (pc)
(if_then_else (le (reg/v:DI 166 [ n ])
(const_int 0 [0]))
(label_ref:DI 76)
(pc))) "/app/example.cpp":17:1 discrim 1 242 {*branchdi}
(int_list:REG_BR_PROB 118111604 (nil))
-> 76)
(note 25 24 26 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 26 25 12 3 (set (reg:DI 156 [ ivtmp_115 ])
(reg/v:DI 166 [ n ])) 179 {*movdi_64bit}
(expr_list:REG_DEAD (reg/v:DI 166 [ n ])
(nil)))
(insn 12 26 13 3 (set (reg/f:DI 155 [ vectp_dst4.48 ])
(reg/v/f:DI 161 [ dst4 ])) "/app/example.cpp":17:1 discrim 1 179 {*movdi_64bit}
(nil))
(insn 13 12 14 3 (set (reg/f:DI 138 [ vectp_dst3.37 ])
(reg/v/f:DI 160 [ dst3 ])) "/app/example.cpp":17:1 discrim 1 179 {*movdi_64bit}
(nil))
(insn 14 13 15 3 (set (reg/f:DI 141 [ vectp_dst2.30 ])
(reg/v/f:DI 159 [ dst2 ])) "/app/example.cpp":17:1 discrim 1 179 {*movdi_64bit}
(nil))
(insn 15 14 71 3 (set (reg/f:DI 146 [ vectp_dst.19 ])
(reg/v/f:DI 158 [ dst ])) "/app/example.cpp":17:1 discrim 1 179 {*movdi_64bit}
(nil))
(code_label 71 15 27 4 3 (nil) [1 uses])
(note 27 71 28 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 28 27 29 4 (set (reg:DI 157 [ _117 ])
(unspec:DI [
(reg:DI 156 [ ivtmp_115 ])
(const_int 8 [0x8])
(const_int 5 [0x5])
(const_int 0 [0]) repeated x2
] UNSPEC_VSETVL)) 1116 {vsetvldi_no_side_effects}
(nil))
(debug_insn 29 28 30 4 (debug_marker) "/app/example.cpp":17:1 discrim 3 -1
(nil))
(insn 30 29 31 4 (set (reg:DI 154 [ ivtmp_105 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 3 [0x3]))) 198 {ashldi3}
(nil))
(insn 31 30 32 4 (set (reg:VNx2DF 153 [ vect__4.8 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 158 [ dst ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.6_104]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1157 {pred_movvnx2df}
(nil))
(insn 32 31 33 4 (set (reg:DI 152 [ ivtmp_101 ])
(ashift:DI (reg:DI 157 [ _117 ])
(const_int 2 [0x2]))) 198 {ashldi3}
(nil))
(insn 33 32 34 4 (set (reg:VNx2SF 151 [ vect__7.11 ])
(if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 162 [ a ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a.9_100]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1151 {pred_movvnx2sf}
(nil))
(insn 34 33 35 4 (set (reg:VNx2DF 150 [ vect__8.12 ])
(float_extend:VNx2DF (reg:VNx2SF 151 [ vect__7.11 ]))) "/app/example.cpp":17:1 discrim 3 12395 {extendvnx2sfvnx2df2}
(expr_list:REG_DEAD (reg:VNx2SF 151 [ vect__7.11 ])
(nil)))
(insn 35 34 36 4 (set (reg:VNx2SF 149 [ vect__10.15 ])
(if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 163 [ b ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b.13_95]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1151 {pred_movvnx2sf}
(nil))
(insn 36 35 37 4 (set (reg:VNx2DF 148 [ vect__11.16 ])
(float_extend:VNx2DF (reg:VNx2SF 149 [ vect__10.15 ]))) "/app/example.cpp":17:1 discrim 3 12395 {extendvnx2sfvnx2df2}
(expr_list:REG_DEAD (reg:VNx2SF 149 [ vect__10.15 ])
(nil)))
(insn 37 36 38 4 (parallel [
(set (reg:VNx2DF 147 [ vect__13.18 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 148 [ vect__11.16 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 153 [ vect__4.8 ])))
(clobber (reg:DI 168))
]) "/app/example.cpp":17:1 discrim 3 12582 {*fnmavnx2dfdi}
(expr_list:REG_DEAD (reg:VNx2DF 153 [ vect__4.8 ])
(expr_list:REG_UNUSED (reg:DI 168)
(nil))))
(insn 38 37 39 4 (set (mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg:VNx2DF 147 [ vect__13.18 ])
(mem:VNx2DF (reg/f:DI 146 [ vectp_dst.19 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst.19_88]+0 S[16, 16] A64]))) "/app/example.cpp":17:1 discrim 3 1201 {pred_storevnx2df}
(expr_list:REG_DEAD (reg:VNx2DF 147 [ vect__13.18 ])
(nil)))
(debug_insn 39 38 40 4 (debug_marker) "/app/example.cpp":17:1 discrim 3 -1
(nil))
(insn 40 39 41 4 (set (reg:VNx2DF 145 [ vect__15.23 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 159 [ dst2 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.21_84]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1157 {pred_movvnx2df}
(nil))
(insn 41 40 42 4 (set (reg:VNx2SF 144 [ vect__17.26 ])
(if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 164 [ a2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_a2.24_80]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1151 {pred_movvnx2sf}
(nil))
(insn 42 41 43 4 (set (reg:VNx2DF 143 [ vect__18.27 ])
(float_extend:VNx2DF (reg:VNx2SF 144 [ vect__17.26 ]))) "/app/example.cpp":17:1 discrim 3 12395 {extendvnx2sfvnx2df2}
(expr_list:REG_DEAD (reg:VNx2SF 144 [ vect__17.26 ])
(nil)))
(insn 43 42 44 4 (parallel [
(set (reg:VNx2DF 142 [ vect__20.29 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 148 [ vect__11.16 ])
(reg:VNx2DF 145 [ vect__15.23 ])))
(clobber (reg:DI 169))
]) "/app/example.cpp":17:1 discrim 3 12582 {*fnmavnx2dfdi}
(expr_list:REG_DEAD (reg:VNx2DF 148 [ vect__11.16 ])
(expr_list:REG_DEAD (reg:VNx2DF 145 [ vect__15.23 ])
(expr_list:REG_UNUSED (reg:DI 169)
(nil)))))
(insn 44 43 45 4 (set (mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg:VNx2DF 142 [ vect__20.29 ])
(mem:VNx2DF (reg/f:DI 141 [ vectp_dst2.30 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst2.30_73]+0 S[16, 16] A64]))) "/app/example.cpp":17:1 discrim 3 1201 {pred_storevnx2df}
(expr_list:REG_DEAD (reg:VNx2DF 142 [ vect__20.29 ])
(nil)))
(debug_insn 45 44 46 4 (debug_marker) "/app/example.cpp":17:1 discrim 3 -1
(nil))
(insn 46 45 47 4 (set (reg:VNx2DF 140 [ vect__22.34 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 160 [ dst3 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.32_69]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1157 {pred_movvnx2df}
(nil))
(insn 47 46 48 4 (parallel [
(set (reg:VNx2DF 139 [ vect__24.36 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 143 [ vect__18.27 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 140 [ vect__22.34 ])))
(clobber (reg:DI 170))
]) "/app/example.cpp":17:1 discrim 3 12582 {*fnmavnx2dfdi}
(expr_list:REG_DEAD (reg:VNx2DF 143 [ vect__18.27 ])
(expr_list:REG_DEAD (reg:VNx2DF 140 [ vect__22.34 ])
(expr_list:REG_UNUSED (reg:DI 170)
(nil)))))
(insn 48 47 49 4 (set (mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg:VNx2DF 139 [ vect__24.36 ])
(mem:VNx2DF (reg/f:DI 138 [ vectp_dst3.37 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst3.37_63]+0 S[16, 16] A64]))) "/app/example.cpp":17:1 discrim 3 1201 {pred_storevnx2df}
(expr_list:REG_DEAD (reg:VNx2DF 139 [ vect__24.36 ])
(nil)))
(debug_insn 49 48 50 4 (debug_marker) "/app/example.cpp":17:1 discrim 3 -1
(nil))
(insn 50 49 51 4 (set (reg:VNx2DF 137 [ vect__26.41 ])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2DF (reg/v/f:DI 161 [ dst4 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.39_59]+0 S[16, 16] A64])
(unspec:VNx2DF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1157 {pred_movvnx2df}
(nil))
(insn 51 50 52 4 (set (reg:VNx2SF 136 [ vect__28.44 ])
(if_then_else:VNx2SF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem:VNx2SF (reg/v/f:DI 165 [ b2 ]) [2 MEM <vector([2,2]) float> [(float *)vectp_b2.42_55]+0 S[8, 8] A32])
(unspec:VNx2SF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.cpp":17:1 discrim 3 1151 {pred_movvnx2sf}
(expr_list:REG_DEAD (reg:SI 0 zero)
(nil)))
(insn 52 51 53 4 (set (reg:VNx2DF 171 [ vect__29.45 ])
(float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ]))) "/app/example.cpp":17:1 discrim 3 12395 {extendvnx2sfvnx2df2}
(expr_list:REG_DEAD (reg:VNx2SF 136 [ vect__28.44 ])
(nil)))
(insn 53 52 54 4 (parallel [
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (reg:VNx2DF 171 [ vect__29.45 ]))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 137 [ vect__26.41 ])))
(clobber (reg:DI 172))
]) "/app/example.cpp":17:1 discrim 3 12582 {*fnmavnx2dfdi}
(expr_list:REG_DEAD (reg:VNx2DF 171 [ vect__29.45 ])
(expr_list:REG_DEAD (reg:VNx2DF 150 [ vect__8.12 ])
(expr_list:REG_DEAD (reg:VNx2DF 137 [ vect__26.41 ])
(expr_list:REG_UNUSED (reg:DI 172)
(nil))))))
(insn 54 53 55 4 (set (mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64])
(if_then_else:VNx2DF (unspec:VNx2BI [
(const_vector:VNx2BI repeat [
(const_int 1 [0x1])
])
(reg:DI 157 [ _117 ])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg:VNx2DF 134 [ vect__31.47 ])
(mem:VNx2DF (reg/f:DI 155 [ vectp_dst4.48 ]) [1 MEM <vector([2,2]) double> [(double *)vectp_dst4.48_111]+0 S[16, 16] A64]))) "/app/example.cpp":17:1 discrim 3 1201 {pred_storevnx2df}
(expr_list:REG_DEAD (reg:VNx2DF 134 [ vect__31.47 ])
(expr_list:REG_DEAD (reg:SI 67 vtype)
(expr_list:REG_DEAD (reg:SI 66 vl)
(nil)))))
(debug_insn 55 54 56 4 (debug_marker) "/app/example.cpp":17:1 discrim 3 -1
(nil))
(debug_insn 56 55 57 4 (var_location:SI i (clobber (const_int 0 [0]))) -1
(nil))
(debug_insn 57 56 58 4 (debug_marker) "/app/example.cpp":17:1 discrim 1 -1
(nil))
(insn 58 57 59 4 (set (reg/v/f:DI 158 [ dst ])
(plus:DI (reg/v/f:DI 158 [ dst ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 59 58 60 4 (set (reg/v/f:DI 162 [ a ])
(plus:DI (reg/v/f:DI 162 [ a ])
(reg:DI 152 [ ivtmp_101 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 60 59 61 4 (set (reg/v/f:DI 163 [ b ])
(plus:DI (reg/v/f:DI 163 [ b ])
(reg:DI 152 [ ivtmp_101 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 61 60 62 4 (set (reg/f:DI 146 [ vectp_dst.19 ])
(plus:DI (reg/f:DI 146 [ vectp_dst.19 ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 62 61 63 4 (set (reg/v/f:DI 159 [ dst2 ])
(plus:DI (reg/v/f:DI 159 [ dst2 ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 63 62 64 4 (set (reg/v/f:DI 164 [ a2 ])
(plus:DI (reg/v/f:DI 164 [ a2 ])
(reg:DI 152 [ ivtmp_101 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 64 63 65 4 (set (reg/f:DI 141 [ vectp_dst2.30 ])
(plus:DI (reg/f:DI 141 [ vectp_dst2.30 ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 65 64 66 4 (set (reg/v/f:DI 160 [ dst3 ])
(plus:DI (reg/v/f:DI 160 [ dst3 ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 66 65 67 4 (set (reg/f:DI 138 [ vectp_dst3.37 ])
(plus:DI (reg/f:DI 138 [ vectp_dst3.37 ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 67 66 68 4 (set (reg/v/f:DI 161 [ dst4 ])
(plus:DI (reg/v/f:DI 161 [ dst4 ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(nil))
(insn 68 67 69 4 (set (reg/v/f:DI 165 [ b2 ])
(plus:DI (reg/v/f:DI 165 [ b2 ])
(reg:DI 152 [ ivtmp_101 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(expr_list:REG_DEAD (reg:DI 152 [ ivtmp_101 ])
(nil)))
(insn 69 68 70 4 (set (reg/f:DI 155 [ vectp_dst4.48 ])
(plus:DI (reg/f:DI 155 [ vectp_dst4.48 ])
(reg:DI 154 [ ivtmp_105 ]))) "/app/example.cpp":17:1 discrim 1 5 {adddi3}
(expr_list:REG_DEAD (reg:DI 154 [ ivtmp_105 ])
(nil)))
(insn 70 69 72 4 (set (reg:DI 156 [ ivtmp_115 ])
(minus:DI (reg:DI 156 [ ivtmp_115 ])
(reg:DI 157 [ _117 ]))) "/app/example.cpp":17:1 discrim 1 11 {subdi3}
(expr_list:REG_DEAD (reg:DI 157 [ _117 ])
(nil)))
(jump_insn 72 70 76 4 (set (pc)
(if_then_else (ne (reg:DI 156 [ ivtmp_115 ])
(const_int 0 [0]))
(label_ref:DI 71)
(pc))) 242 {*branchdi}
(int_list:REG_BR_PROB 894784862 (nil))
-> 71)
(code_label 76 72 77 5 1 (nil) [1 uses])
(note 77 76 0 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
;; Combiner totals: 40 attempts, 39 substitutions (19 requiring new space),
;; 0 successes.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-28 22:56 ` 钟居哲
@ 2023-06-29 23:43 ` Jeff Law
2023-06-30 1:14 ` juzhe.zhong
0 siblings, 1 reply; 13+ messages in thread
From: Jeff Law @ 2023-06-29 23:43 UTC (permalink / raw)
To: 钟居哲, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, rdapp.gcc
On 6/28/23 16:56, 钟居哲 wrote:
>
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
> *From:* Jeff Law <mailto:jeffreyalaw@gmail.com>
> *Date:* 2023-06-29 06:43
> *To:* 钟居哲 <mailto:juzhe.zhong@rivai.ai>; gcc-patches
> <mailto:gcc-patches@gcc.gnu.org>
> *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; kito.cheng
> <mailto:kito.cheng@sifive.com>; palmer <mailto:palmer@dabbelt.com>;
> palmer <mailto:palmer@rivosinc.com>; rdapp.gcc
> <mailto:rdapp.gcc@gmail.com>
> *Subject:* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac
> combine lowering
> On 6/28/23 16:10, 钟居哲 wrot
> > Sure.
> >
> > https://godbolt.org/z/8857KzTno <https://godbolt.org/z/8857KzTno>
> >
> > Failed to match this instruction:
> > (set (reg:VNx2DF 134 [ vect__31.47 ])
> > (fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [
> > vect__28.44 ])))
> > (reg:VNx2DF 150 [ vect__8.12 ])
> > (reg:VNx2DF 171 [ vect__29.45 ])))
> Please attach the full dump. I would expect to see additional attempts
> with more operands replaced.
THanks for the dump. I think this fundamentally the same issue as the
widening problem.
Drop those intermediate patterns. They're not needed/helpful. You may
need a dependency height reduction pattern to get the code you want, but
I see no evidence those extra patterns will solve anything.
jeff
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-29 23:43 ` Jeff Law
@ 2023-06-30 1:14 ` juzhe.zhong
2023-06-30 1:26 ` Jeff Law
0 siblings, 1 reply; 13+ messages in thread
From: juzhe.zhong @ 2023-06-30 1:14 UTC (permalink / raw)
To: jeffreyalaw, gcc-patches
Cc: kito.cheng, Kito.cheng, palmer, palmer, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 1939 bytes --]
No, reduction patterns won't help.
As I said in vfwmul patch. You should make sure your environment is working then try again.
Thanks.
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-06-30 07:43
To: 钟居哲; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
On 6/28/23 16:56, 钟居哲 wrote:
>
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
> *From:* Jeff Law <mailto:jeffreyalaw@gmail.com>
> *Date:* 2023-06-29 06:43
> *To:* 钟居哲 <mailto:juzhe.zhong@rivai.ai>; gcc-patches
> <mailto:gcc-patches@gcc.gnu.org>
> *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; kito.cheng
> <mailto:kito.cheng@sifive.com>; palmer <mailto:palmer@dabbelt.com>;
> palmer <mailto:palmer@rivosinc.com>; rdapp.gcc
> <mailto:rdapp.gcc@gmail.com>
> *Subject:* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac
> combine lowering
> On 6/28/23 16:10, 钟居哲 wrot
> > Sure.
> >
> > https://godbolt.org/z/8857KzTno <https://godbolt.org/z/8857KzTno>
> >
> > Failed to match this instruction:
> > (set (reg:VNx2DF 134 [ vect__31.47 ])
> > (fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [
> > vect__28.44 ])))
> > (reg:VNx2DF 150 [ vect__8.12 ])
> > (reg:VNx2DF 171 [ vect__29.45 ])))
> Please attach the full dump. I would expect to see additional attempts
> with more operands replaced.
THanks for the dump. I think this fundamentally the same issue as the
widening problem.
Drop those intermediate patterns. They're not needed/helpful. You may
need a dependency height reduction pattern to get the code you want, but
I see no evidence those extra patterns will solve anything.
jeff
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-30 1:14 ` juzhe.zhong
@ 2023-06-30 1:26 ` Jeff Law
2023-06-30 1:32 ` juzhe.zhong
0 siblings, 1 reply; 13+ messages in thread
From: Jeff Law @ 2023-06-30 1:26 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches
Cc: kito.cheng, Kito.cheng, palmer, palmer, Robin Dapp
On 6/29/23 19:14, juzhe.zhong@rivai.ai wrote:
> No, reduction patterns won't help.
> As I said in vfwmul patch. You should make sure your environment is
> working then try again.
I've triple checked this already.
I checked it again and your patch does not impact behavior, nor should
it. I checked it on top of these trunk commits:
14bfda6084eaca07c842566a34316974907958e2
e714af12e3bee0032d8d226f87d92c9bc46f0269
I checked it with the code from the godbolt links you suggested with the
options shown in those links.
More importantly, your explanation of what the pattern is supposed to do
shows a misunderstanding of what combine's capabilities actually are. A
bridge or intermediate pattern is not needed here, combine can
substitute multiple sources in combination attempts as can be clearly
seen from the dump fragments I posted.
The only reason I didn't reject the patch at the outset was the
possibility that maybe we were trying to combine more than 4
instructions or that possibility something about the number of operands,
unspecs, whatever were getting in the way.
This patch is not needed and does not affect code generation.
I would strongly suggest looking at a dependency height reduction
pattern if you want to optimize that code further.
Jeff
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-30 1:26 ` Jeff Law
@ 2023-06-30 1:32 ` juzhe.zhong
2023-07-03 7:48 ` Robin Dapp
0 siblings, 1 reply; 13+ messages in thread
From: juzhe.zhong @ 2023-06-30 1:32 UTC (permalink / raw)
To: jeffreyalaw, gcc-patches
Cc: kito.cheng, Kito.cheng, palmer, palmer, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 2212 bytes --]
>> I've triple checked this already.
You mean you still didn't see vfwmul.vv ?
That's odd. Let's wait for kito or Robin test this patch.
Then, I believe they will know what I am saying.
>> I would strongly suggest looking at a dependency height reduction
>> pattern if you want to optimize that code further.
I did it long time ago. Turns out it's better to do that on Combine PASS in both GCC and LLVM.
Never mind, I always have this implementation in my downstream and won't affect my downstream GCC maintainment.
It's ok that this patch is not approved since I can get the perfect codegen in my downstream.
Thanks.
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-06-30 09:26
To: juzhe.zhong@rivai.ai; gcc-patches
CC: kito.cheng; Kito.cheng; palmer; palmer; Robin Dapp
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
On 6/29/23 19:14, juzhe.zhong@rivai.ai wrote:
> No, reduction patterns won't help.
> As I said in vfwmul patch. You should make sure your environment is
> working then try again.
I've triple checked this already.
I checked it again and your patch does not impact behavior, nor should
it. I checked it on top of these trunk commits:
14bfda6084eaca07c842566a34316974907958e2
e714af12e3bee0032d8d226f87d92c9bc46f0269
I checked it with the code from the godbolt links you suggested with the
options shown in those links.
More importantly, your explanation of what the pattern is supposed to do
shows a misunderstanding of what combine's capabilities actually are. A
bridge or intermediate pattern is not needed here, combine can
substitute multiple sources in combination attempts as can be clearly
seen from the dump fragments I posted.
The only reason I didn't reject the patch at the outset was the
possibility that maybe we were trying to combine more than 4
instructions or that possibility something about the number of operands,
unspecs, whatever were getting in the way.
This patch is not needed and does not affect code generation.
I would strongly suggest looking at a dependency height reduction
pattern if you want to optimize that code further.
Jeff
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-06-30 1:32 ` juzhe.zhong
@ 2023-07-03 7:48 ` Robin Dapp
2023-07-03 9:01 ` Kito Cheng
0 siblings, 1 reply; 13+ messages in thread
From: Robin Dapp @ 2023-07-03 7:48 UTC (permalink / raw)
To: juzhe.zhong, jeffreyalaw, gcc-patches
Cc: rdapp.gcc, kito.cheng, Kito.cheng, palmer, palmer
To reiterate, this is OK from my side. As discussed in the other
thread, Jeff would like to have more info on whether a bridge pattern
is needed at all and I agreed to get back to it in a while. Until
then, we can merge this.
Regards
Robin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-07-03 7:48 ` Robin Dapp
@ 2023-07-03 9:01 ` Kito Cheng
2023-07-03 9:12 ` juzhe.zhong
0 siblings, 1 reply; 13+ messages in thread
From: Kito Cheng @ 2023-07-03 9:01 UTC (permalink / raw)
To: Robin Dapp
Cc: juzhe.zhong, jeffreyalaw, gcc-patches, Kito.cheng, palmer, palmer
Tried on local, widen-complicate-7.c, widen-complicate-8.c and
widen-complicate-9.c need those bridge pattern, otherwise will fail to
combine, so give an explicitly LGTM from my side.
On Mon, Jul 3, 2023 at 3:48 PM Robin Dapp via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> To reiterate, this is OK from my side. As discussed in the other
> thread, Jeff would like to have more info on whether a bridge pattern
> is needed at all and I agreed to get back to it in a while. Until
> then, we can merge this.
>
> Regards
> Robin
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-07-03 9:01 ` Kito Cheng
@ 2023-07-03 9:12 ` juzhe.zhong
2023-07-03 9:27 ` Lehua Ding
0 siblings, 1 reply; 13+ messages in thread
From: juzhe.zhong @ 2023-07-03 9:12 UTC (permalink / raw)
To: kito.cheng, Robin Dapp
Cc: jeffreyalaw, gcc-patches, Kito.cheng, palmer, palmer,
丁乐华
[-- Attachment #1: Type: text/plain, Size: 852 bytes --]
Thanks kito.
Lehua will merge it for me.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-07-03 17:01
To: Robin Dapp
CC: juzhe.zhong@rivai.ai; jeffreyalaw; gcc-patches; Kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
Tried on local, widen-complicate-7.c, widen-complicate-8.c and
widen-complicate-9.c need those bridge pattern, otherwise will fail to
combine, so give an explicitly LGTM from my side.
On Mon, Jul 3, 2023 at 3:48 PM Robin Dapp via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> To reiterate, this is OK from my side. As discussed in the other
> thread, Jeff would like to have more info on whether a bridge pattern
> is needed at all and I agreed to get back to it in a while. Until
> then, we can merge this.
>
> Regards
> Robin
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
2023-07-03 9:12 ` juzhe.zhong
@ 2023-07-03 9:27 ` Lehua Ding
0 siblings, 0 replies; 13+ messages in thread
From: Lehua Ding @ 2023-07-03 9:27 UTC (permalink / raw)
To: 钟居哲, kito.cheng, Robin Dapp
Cc: Jeff Law, gcc-patches, Kito Cheng, palmer, palmer
[-- Attachment #1: Type: text/plain, Size: 1607 bytes --]
Commited, thanks Robin, Kito, and Jeff.
------------------ Original ------------------
From: "juzhe.zhong@rivai.ai"<juzhe.zhong@rivai.ai>;
Date: Mon, Jul 3, 2023 05:12 PM
To: "kito.cheng"<kito.cheng@gmail.com>; "Robin Dapp"<rdapp.gcc@gmail.com>;
Cc: "Jeff Law"<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>; "Kito Cheng"<kito.cheng@sifive.com>; "palmer"<palmer@dabbelt.com>; "palmer"<palmer@rivosinc.com>; "丁乐华"<lehua.ding@rivai.ai>;
Subject: Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
Thanks kito.
Lehua will merge it for me.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-07-03 17:01
To: Robin Dapp
CC: juzhe.zhong@rivai.ai; jeffreyalaw; gcc-patches; Kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
Tried on local, widen-complicate-7.c, widen-complicate-8.c and
widen-complicate-9.c need those bridge pattern, otherwise will fail to
combine, so give an explicitly LGTM from my side.
On Mon, Jul 3, 2023 at 3:48 PM Robin Dapp via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> To reiterate, this is OK from my side. As discussed in the other
> thread, Jeff would like to have more info on whether a bridge pattern
> is needed at all and I agreed to get back to it in a while. Until
> then, we can merge this.
>
> Regards
> Robin
>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-07-03 9:27 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-28 11:55 [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering Juzhe-Zhong
2023-06-28 18:16 ` Jeff Law
2023-06-28 22:10 ` 钟居哲
2023-06-28 22:43 ` Jeff Law
2023-06-28 22:56 ` 钟居哲
2023-06-29 23:43 ` Jeff Law
2023-06-30 1:14 ` juzhe.zhong
2023-06-30 1:26 ` Jeff Law
2023-06-30 1:32 ` juzhe.zhong
2023-07-03 7:48 ` Robin Dapp
2023-07-03 9:01 ` Kito Cheng
2023-07-03 9:12 ` juzhe.zhong
2023-07-03 9:27 ` Lehua Ding
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