* [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions @ 2023-02-16 6:13 Tejas Belagod 2023-02-16 6:13 ` [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features Tejas Belagod 2023-02-27 12:16 ` [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Richard Sandiford 0 siblings, 2 replies; 4+ messages in thread From: Tejas Belagod @ 2023-02-16 6:13 UTC (permalink / raw) To: gcc-patches; +Cc: Tejas Belagod, richard.sandiford, Richard.Earnshaw Transitive closures of architectural extensions have to be manually maintained for AARCH64_OPT_EXTENSION list. Currently aes, sha2 and sha3 extensions add AARCH64_FL_SIMD has their dependency - this does not automatically pull in the transitive dependence of AARCH64_FL_FP from AARCH64_FL_SIMD's definition. As described the transitive closure/dependence has to be maintained manually. This patch adds AARCH64_FL_FP to each of these crypto extensions' dependence set. Automatic transitive closure maintenance is fixed on trunk in commit 11a113d501ff64fa4843e28d0a21b3f4e9d0d3de. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (aes, sha2, sha3): Update AARCH64_OPT_EXTENSION definition of architectural dependence for defintion of aes, sha2 and sha3 with AARCH64_FL_FP. --- gcc/config/aarch64/aarch64-option-extensions.def | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index b4d0ac8b600..88cefc20022 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -118,19 +118,19 @@ AARCH64_OPT_EXTENSION("dotprod", AARCH64_FL_DOTPROD, AARCH64_FL_SIMD, 0, \ /* Enabling "aes" also enables "simd". Disabling "aes" disables "aes" and "sve2-aes'. */ -AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, \ - AARCH64_FL_SVE2_AES, false, "aes") +AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD | \ + AARCH64_FL_FP, AARCH64_FL_SVE2_AES, false, "aes") /* Enabling "sha2" also enables "simd". Disabling "sha2" just disables "sha2". */ -AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD, 0, false, \ - "sha1 sha2") +AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD | \ + AARCH64_FL_FP, 0, false, "sha1 sha2") /* Enabling "sha3" enables "simd" and "sha2". Disabling "sha3" disables "sha3" and "sve2-sha3". */ AARCH64_OPT_EXTENSION("sha3", AARCH64_FL_SHA3, AARCH64_FL_SIMD | \ - AARCH64_FL_SHA2, AARCH64_FL_SVE2_SHA3, false, \ - "sha3 sha512") + AARCH64_FL_SHA2 | AARCH64_FL_FP, AARCH64_FL_SVE2_SHA3, \ + false, "sha3 sha512") /* Enabling "sm4" also enables "simd". Disabling "sm4" disables "sm4" and "sve2-sm4". */ -- 2.17.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features 2023-02-16 6:13 [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Tejas Belagod @ 2023-02-16 6:13 ` Tejas Belagod 2023-02-27 12:19 ` Richard Sandiford 2023-02-27 12:16 ` [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Richard Sandiford 1 sibling, 1 reply; 4+ messages in thread From: Tejas Belagod @ 2023-02-16 6:13 UTC (permalink / raw) To: gcc-patches; +Cc: Tejas Belagod, richard.sandiford, Richard.Earnshaw The 64-bit variant of PMULL{2} and AES instructions are available if FEAT_AES is implemented according to the Arm ARM [1]. Similarly FEAT_SHA1 and FEAT_SHA256 enable the use of SHA1 and SHA256 instruction variants. This patch fixes arm_neon.h to correctly reflect the feature availability based on '+aes' and '+sha2' as opposed to the ambiguous catch-all '+crypto'. [1] Section D17.2.61, C7.2.215 2022-01-11 Tejas Belagod <tejas.belagod@arm.com> gcc/ChangeLog: * config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8, vaesdq_u8, vaesmcq_u8, vaesimcq_u8): Gate under "nothing+aes". (vsha1*_u32, vsha256*_u32): Gate under "nothing+sha2". gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/pmull64.c: New. * gcc.target/aarch64/aes-fuse-1.c: Replace '+crypto' with corresponding feature flag based on the intrinsic. * gcc.target/aarch64/aes-fuse-2.c: Likewise. * gcc.target/aarch64/aes_1.c: Likewise. * gcc.target/aarch64/aes_2.c: Likewise. * gcc.target/aarch64/aes_xor_combine.c: Likewise. * gcc.target/aarch64/sha1_1.c: Likewise. * gcc.target/aarch64/sha256_1.c: Likewise. * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise. --- gcc/config/aarch64/arm_neon.h | 35 ++++++++++--------- .../gcc.target/aarch64/acle/pmull64.c | 14 ++++++++ gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c | 4 +-- gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c | 4 +-- gcc/testsuite/gcc.target/aarch64/aes_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/aes_2.c | 4 ++- .../gcc.target/aarch64/aes_xor_combine.c | 2 +- gcc/testsuite/gcc.target/aarch64/sha1_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/sha256_1.c | 2 +- .../aarch64/target_attr_crypto_ice_1.c | 2 +- 10 files changed, 44 insertions(+), 27 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/pmull64.c diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 85d03c58d2a..695aafd9a5e 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -10243,7 +10243,7 @@ vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d) #pragma GCC pop_options #pragma GCC push_options -#pragma GCC target ("+nothing+crypto") +#pragma GCC target ("+nothing+aes") /* vaes */ __extension__ extern __inline uint8x16_t @@ -10273,6 +10273,22 @@ vaesimcq_u8 (uint8x16_t data) { return __builtin_aarch64_crypto_aesimcv16qi_uu (data); } + +__extension__ extern __inline poly128_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_p64 (poly64_t __a, poly64_t __b) +{ + return + __builtin_aarch64_crypto_pmulldi_ppp (__a, __b); +} + +__extension__ extern __inline poly128_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_high_p64 (poly64x2_t __a, poly64x2_t __b) +{ + return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b); +} + #pragma GCC pop_options /* vcage */ @@ -23519,7 +23535,7 @@ vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c) } #pragma GCC push_options -#pragma GCC target ("+nothing+crypto") +#pragma GCC target ("+nothing+sha2") /* vsha1 */ @@ -23596,21 +23612,6 @@ vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15) __w12_15); } -__extension__ extern __inline poly128_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmull_p64 (poly64_t __a, poly64_t __b) -{ - return - __builtin_aarch64_crypto_pmulldi_ppp (__a, __b); -} - -__extension__ extern __inline poly128_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmull_high_p64 (poly64x2_t __a, poly64x2_t __b) -{ - return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b); -} - #pragma GCC pop_options /* vshl */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c b/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c new file mode 100644 index 00000000000..6a1e99e2d0d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.2-a" } */ + +#pragma push_options +#pragma GCC target ("+aes") + +#include "arm_neon.h" + +int foo (poly64_t a, poly64_t b) +{ + return vgetq_lane_s32 (vreinterpretq_s32_p128 (vmull_p64 (a, b)), 0); +} + +/* { dg-final { scan-assembler "\tpmull\tv" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c b/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c index d7b4f89919d..1b4e10f78db 100644 --- a/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c +++ b/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mcpu=cortex-a72+crypto -dp" } */ -/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/ +/* { dg-options "-O3 -mcpu=cortex-a72+aes -dp" } */ +/* { dg-additional-options "-march=armv8-a+aes" { target { aarch64*-*-* } } }*/ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c b/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c index dfe01b03a36..4c028b39083 100644 --- a/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c +++ b/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mcpu=cortex-a72+crypto -dp" } */ -/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/ +/* { dg-options "-O3 -mcpu=cortex-a72+aes -dp" } */ +/* { dg-additional-options "-march=armv8-a+aes" { target { aarch64*-*-* } } }*/ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc/testsuite/gcc.target/aarch64/aes_1.c index 5578e85dab7..754c4ab90e7 100644 --- a/gcc/testsuite/gcc.target/aarch64/aes_1.c +++ b/gcc/testsuite/gcc.target/aarch64/aes_1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=armv8-a+crypto" } */ +/* { dg-options "-march=armv8-a+aes" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/aarch64/aes_2.c b/gcc/testsuite/gcc.target/aarch64/aes_2.c index 70f113fb5ab..442c1006706 100644 --- a/gcc/testsuite/gcc.target/aarch64/aes_2.c +++ b/gcc/testsuite/gcc.target/aarch64/aes_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=armv8-a+crypto" } */ +/* { dg-options "-O3 -march=armv8-a+aes" } */ #include "arm_neon.h" @@ -76,4 +76,6 @@ test7 (uint8x16_t a, uint8x16_t b) return result; } /* { dg-final { scan-assembler-not "mov" } } */ +/* { dg-final { scan-assembler "aesd\tv" } } */ +/* { dg-final { scan-assembler "aese\tv" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c index 833e9b3073b..ee0f0e99856 100644 --- a/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c +++ b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mcpu=cortex-a55+crypto" } */ +/* { dg-options "-O3 -mcpu=cortex-a55+aes" } */ #include <arm_neon.h> #define AESE(r, v, key) (r = vaeseq_u8 ((v), (key))); diff --git a/gcc/testsuite/gcc.target/aarch64/sha1_1.c b/gcc/testsuite/gcc.target/aarch64/sha1_1.c index e208fe7d93f..ba56c04a118 100644 --- a/gcc/testsuite/gcc.target/aarch64/sha1_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sha1_1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=armv8-a+crypto" } */ +/* { dg-options "-march=armv8-a+sha2" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc/testsuite/gcc.target/aarch64/sha256_1.c index 2102daf20a3..c3860c6b537 100644 --- a/gcc/testsuite/gcc.target/aarch64/sha256_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sha256_1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=armv8-a+crypto" } */ +/* { dg-options "-march=armv8-a+sha2" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c index c74cc900f98..3b354c06110 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c @@ -6,7 +6,7 @@ /* Unless we do something about re-laying out the SIMD builtin types this testcase ICEs during expansion of the crypto builtin. */ -__attribute__ ((target ("cpu=cortex-a57+crypto"))) +__attribute__ ((target ("cpu=cortex-a57+sha2"))) uint32x4_t test_vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) { -- 2.17.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features 2023-02-16 6:13 ` [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features Tejas Belagod @ 2023-02-27 12:19 ` Richard Sandiford 0 siblings, 0 replies; 4+ messages in thread From: Richard Sandiford @ 2023-02-27 12:19 UTC (permalink / raw) To: Tejas Belagod; +Cc: gcc-patches, Richard.Earnshaw Tejas Belagod <tejas.belagod@arm.com> writes: > The 64-bit variant of PMULL{2} and AES instructions are available if FEAT_AES > is implemented according to the Arm ARM [1]. Similarly FEAT_SHA1 and > FEAT_SHA256 enable the use of SHA1 and SHA256 instruction variants. > This patch fixes arm_neon.h to correctly reflect the feature availability based > on '+aes' and '+sha2' as opposed to the ambiguous catch-all '+crypto'. > > [1] Section D17.2.61, C7.2.215 > > 2022-01-11 Tejas Belagod <tejas.belagod@arm.com> > > gcc/ChangeLog: > > * config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8, > vaesdq_u8, vaesmcq_u8, vaesimcq_u8): Gate under "nothing+aes". > (vsha1*_u32, vsha256*_u32): Gate under "nothing+sha2". > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/acle/pmull64.c: New. > * gcc.target/aarch64/aes-fuse-1.c: Replace '+crypto' with corresponding > feature flag based on the intrinsic. > * gcc.target/aarch64/aes-fuse-2.c: Likewise. > * gcc.target/aarch64/aes_1.c: Likewise. > * gcc.target/aarch64/aes_2.c: Likewise. > * gcc.target/aarch64/aes_xor_combine.c: Likewise. > * gcc.target/aarch64/sha1_1.c: Likewise. > * gcc.target/aarch64/sha256_1.c: Likewise. > * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise. OK to backport, thanks. Richard > --- > gcc/config/aarch64/arm_neon.h | 35 ++++++++++--------- > .../gcc.target/aarch64/acle/pmull64.c | 14 ++++++++ > gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c | 4 +-- > gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c | 4 +-- > gcc/testsuite/gcc.target/aarch64/aes_1.c | 2 +- > gcc/testsuite/gcc.target/aarch64/aes_2.c | 4 ++- > .../gcc.target/aarch64/aes_xor_combine.c | 2 +- > gcc/testsuite/gcc.target/aarch64/sha1_1.c | 2 +- > gcc/testsuite/gcc.target/aarch64/sha256_1.c | 2 +- > .../aarch64/target_attr_crypto_ice_1.c | 2 +- > 10 files changed, 44 insertions(+), 27 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/pmull64.c > > diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h > index 85d03c58d2a..695aafd9a5e 100644 > --- a/gcc/config/aarch64/arm_neon.h > +++ b/gcc/config/aarch64/arm_neon.h > @@ -10243,7 +10243,7 @@ vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d) > #pragma GCC pop_options > > #pragma GCC push_options > -#pragma GCC target ("+nothing+crypto") > +#pragma GCC target ("+nothing+aes") > /* vaes */ > > __extension__ extern __inline uint8x16_t > @@ -10273,6 +10273,22 @@ vaesimcq_u8 (uint8x16_t data) > { > return __builtin_aarch64_crypto_aesimcv16qi_uu (data); > } > + > +__extension__ extern __inline poly128_t > +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > +vmull_p64 (poly64_t __a, poly64_t __b) > +{ > + return > + __builtin_aarch64_crypto_pmulldi_ppp (__a, __b); > +} > + > +__extension__ extern __inline poly128_t > +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > +vmull_high_p64 (poly64x2_t __a, poly64x2_t __b) > +{ > + return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b); > +} > + > #pragma GCC pop_options > > /* vcage */ > @@ -23519,7 +23535,7 @@ vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c) > } > > #pragma GCC push_options > -#pragma GCC target ("+nothing+crypto") > +#pragma GCC target ("+nothing+sha2") > > /* vsha1 */ > > @@ -23596,21 +23612,6 @@ vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15) > __w12_15); > } > > -__extension__ extern __inline poly128_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -vmull_p64 (poly64_t __a, poly64_t __b) > -{ > - return > - __builtin_aarch64_crypto_pmulldi_ppp (__a, __b); > -} > - > -__extension__ extern __inline poly128_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -vmull_high_p64 (poly64x2_t __a, poly64x2_t __b) > -{ > - return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b); > -} > - > #pragma GCC pop_options > > /* vshl */ > diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c b/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c > new file mode 100644 > index 00000000000..6a1e99e2d0d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=armv8.2-a" } */ > + > +#pragma push_options > +#pragma GCC target ("+aes") > + > +#include "arm_neon.h" > + > +int foo (poly64_t a, poly64_t b) > +{ > + return vgetq_lane_s32 (vreinterpretq_s32_p128 (vmull_p64 (a, b)), 0); > +} > + > +/* { dg-final { scan-assembler "\tpmull\tv" } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c b/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c > index d7b4f89919d..1b4e10f78db 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c > +++ b/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c > @@ -1,6 +1,6 @@ > /* { dg-do compile } */ > -/* { dg-options "-O3 -mcpu=cortex-a72+crypto -dp" } */ > -/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/ > +/* { dg-options "-O3 -mcpu=cortex-a72+aes -dp" } */ > +/* { dg-additional-options "-march=armv8-a+aes" { target { aarch64*-*-* } } }*/ > > #include <arm_neon.h> > > diff --git a/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c b/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c > index dfe01b03a36..4c028b39083 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c > +++ b/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c > @@ -1,6 +1,6 @@ > /* { dg-do compile } */ > -/* { dg-options "-O3 -mcpu=cortex-a72+crypto -dp" } */ > -/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/ > +/* { dg-options "-O3 -mcpu=cortex-a72+aes -dp" } */ > +/* { dg-additional-options "-march=armv8-a+aes" { target { aarch64*-*-* } } }*/ > > #include <arm_neon.h> > > diff --git a/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc/testsuite/gcc.target/aarch64/aes_1.c > index 5578e85dab7..754c4ab90e7 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aes_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/aes_1.c > @@ -1,6 +1,6 @@ > > /* { dg-do compile } */ > -/* { dg-options "-march=armv8-a+crypto" } */ > +/* { dg-options "-march=armv8-a+aes" } */ > > #include "arm_neon.h" > > diff --git a/gcc/testsuite/gcc.target/aarch64/aes_2.c b/gcc/testsuite/gcc.target/aarch64/aes_2.c > index 70f113fb5ab..442c1006706 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aes_2.c > +++ b/gcc/testsuite/gcc.target/aarch64/aes_2.c > @@ -1,6 +1,6 @@ > > /* { dg-do compile } */ > -/* { dg-options "-O3 -march=armv8-a+crypto" } */ > +/* { dg-options "-O3 -march=armv8-a+aes" } */ > > #include "arm_neon.h" > > @@ -76,4 +76,6 @@ test7 (uint8x16_t a, uint8x16_t b) > return result; > } > /* { dg-final { scan-assembler-not "mov" } } */ > +/* { dg-final { scan-assembler "aesd\tv" } } */ > +/* { dg-final { scan-assembler "aese\tv" } } */ > > diff --git a/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c > index 833e9b3073b..ee0f0e99856 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c > +++ b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O3 -mcpu=cortex-a55+crypto" } */ > +/* { dg-options "-O3 -mcpu=cortex-a55+aes" } */ > #include <arm_neon.h> > > #define AESE(r, v, key) (r = vaeseq_u8 ((v), (key))); > diff --git a/gcc/testsuite/gcc.target/aarch64/sha1_1.c b/gcc/testsuite/gcc.target/aarch64/sha1_1.c > index e208fe7d93f..ba56c04a118 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sha1_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/sha1_1.c > @@ -1,6 +1,6 @@ > > /* { dg-do compile } */ > -/* { dg-options "-march=armv8-a+crypto" } */ > +/* { dg-options "-march=armv8-a+sha2" } */ > > #include "arm_neon.h" > > diff --git a/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc/testsuite/gcc.target/aarch64/sha256_1.c > index 2102daf20a3..c3860c6b537 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sha256_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/sha256_1.c > @@ -1,6 +1,6 @@ > > /* { dg-do compile } */ > -/* { dg-options "-march=armv8-a+crypto" } */ > +/* { dg-options "-march=armv8-a+sha2" } */ > > #include "arm_neon.h" > > diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c > index c74cc900f98..3b354c06110 100644 > --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c > @@ -6,7 +6,7 @@ > /* Unless we do something about re-laying out the SIMD builtin types > this testcase ICEs during expansion of the crypto builtin. */ > > -__attribute__ ((target ("cpu=cortex-a57+crypto"))) > +__attribute__ ((target ("cpu=cortex-a57+sha2"))) > uint32x4_t > test_vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) > { ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions 2023-02-16 6:13 [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Tejas Belagod 2023-02-16 6:13 ` [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features Tejas Belagod @ 2023-02-27 12:16 ` Richard Sandiford 1 sibling, 0 replies; 4+ messages in thread From: Richard Sandiford @ 2023-02-27 12:16 UTC (permalink / raw) To: Tejas Belagod; +Cc: gcc-patches, Richard.Earnshaw Tejas Belagod <tejas.belagod@arm.com> writes: > Transitive closures of architectural extensions have to be manually maintained > for AARCH64_OPT_EXTENSION list. Currently aes, sha2 and sha3 extensions add > AARCH64_FL_SIMD has their dependency - this does not automatically pull in the > transitive dependence of AARCH64_FL_FP from AARCH64_FL_SIMD's definition. As > described the transitive closure/dependence has to be maintained manually. > This patch adds AARCH64_FL_FP to each of these crypto extensions' dependence > set. Automatic transitive closure maintenance is fixed on trunk in commit > 11a113d501ff64fa4843e28d0a21b3f4e9d0d3de. > > gcc/ChangeLog: > > * config/aarch64/aarch64-option-extensions.def (aes, sha2, sha3): > Update AARCH64_OPT_EXTENSION definition of architectural dependence for > defintion of aes, sha2 and sha3 with AARCH64_FL_FP. OK, thanks. Richard > --- > gcc/config/aarch64/aarch64-option-extensions.def | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def > index b4d0ac8b600..88cefc20022 100644 > --- a/gcc/config/aarch64/aarch64-option-extensions.def > +++ b/gcc/config/aarch64/aarch64-option-extensions.def > @@ -118,19 +118,19 @@ AARCH64_OPT_EXTENSION("dotprod", AARCH64_FL_DOTPROD, AARCH64_FL_SIMD, 0, \ > > /* Enabling "aes" also enables "simd". > Disabling "aes" disables "aes" and "sve2-aes'. */ > -AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, \ > - AARCH64_FL_SVE2_AES, false, "aes") > +AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD | \ > + AARCH64_FL_FP, AARCH64_FL_SVE2_AES, false, "aes") > > /* Enabling "sha2" also enables "simd". > Disabling "sha2" just disables "sha2". */ > -AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD, 0, false, \ > - "sha1 sha2") > +AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD | \ > + AARCH64_FL_FP, 0, false, "sha1 sha2") > > /* Enabling "sha3" enables "simd" and "sha2". > Disabling "sha3" disables "sha3" and "sve2-sha3". */ > AARCH64_OPT_EXTENSION("sha3", AARCH64_FL_SHA3, AARCH64_FL_SIMD | \ > - AARCH64_FL_SHA2, AARCH64_FL_SVE2_SHA3, false, \ > - "sha3 sha512") > + AARCH64_FL_SHA2 | AARCH64_FL_FP, AARCH64_FL_SVE2_SHA3, \ > + false, "sha3 sha512") > > /* Enabling "sm4" also enables "simd". > Disabling "sm4" disables "sm4" and "sve2-sm4". */ ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-02-27 12:19 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-02-16 6:13 [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Tejas Belagod 2023-02-16 6:13 ` [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features Tejas Belagod 2023-02-27 12:19 ` Richard Sandiford 2023-02-27 12:16 ` [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Richard Sandiford
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