* [PATCH 0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support
@ 2023-11-07 10:30 Victor Do Nascimento
2023-11-07 10:30 ` [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions Victor Do Nascimento
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Victor Do Nascimento @ 2023-11-07 10:30 UTC (permalink / raw)
To: gcc-patches
Cc: kyrylo.tkachov, richard.sandiford, Richard.Earnshaw,
Victor Do Nascimento
Given the introduction of optional 128-bit page table descriptor and
translation hardening extension support with the Arm9.4-a
architecture, this patch series introduces the necessary changes to
the aarch64-specific builtin code to enable the reading and writing of
128-bit system registers. In so doing, the following ACLE builtins and
feature macro are made available to the compiler:
* __uint128_t __arm_rsr128(const char *special_register);
* void __arm_wsr128(const char *special_register, __uint128_t value);
* __ARM_FEATURE_SYSREG128.
Finally, in order to update the GCC system-register database bringing
it in line with Binutils, and in so doing add the relevant 128-bit
system registers to GCC, this patch also introduces the Guarded
Control Stack (GCS) `+gcs' architecture modifier flag, allowing the
inclusion of the novel GCS system registers which are now supported
and also present in the `aarch64-sys-regs.def' system register
database.
Victor Do Nascimento (5):
aarch64: Add march flags for +the and +d128 arch extensions
aarch64: Add support for GCS system registers with the +gcs modifier
aarch64: Sync `aarch64-sys-regs.def' with Binutils.
aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins
aarch64: Add rsr128 and wsr128 ACLE tests
gcc/config/aarch64/aarch64-arches.def | 2 +
gcc/config/aarch64/aarch64-builtins.cc | 50 ++++++++++++++++---
gcc/config/aarch64/aarch64-c.cc | 1 +
.../aarch64/aarch64-option-extensions.def | 6 +++
gcc/config/aarch64/aarch64-protos.h | 2 +-
gcc/config/aarch64/aarch64-sys-regs.def | 30 +++++++----
gcc/config/aarch64/aarch64.cc | 6 ++-
gcc/config/aarch64/aarch64.h | 21 ++++++++
gcc/config/aarch64/aarch64.md | 18 +++++++
gcc/config/aarch64/arm_acle.h | 11 ++++
gcc/doc/invoke.texi | 8 +++
gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 30 ++++++++++-
12 files changed, 165 insertions(+), 20 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions
2023-11-07 10:30 [PATCH 0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support Victor Do Nascimento
@ 2023-11-07 10:30 ` Victor Do Nascimento
2023-11-07 23:18 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 2/5] aarch64: Add support for GCS system registers with the +gcs modifier Victor Do Nascimento
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Victor Do Nascimento @ 2023-11-07 10:30 UTC (permalink / raw)
To: gcc-patches
Cc: kyrylo.tkachov, richard.sandiford, Richard.Earnshaw,
Victor Do Nascimento
Given the introduction of optional 128-bit page table descriptor and
translation hardening extension support with the Arm9.4-a
architecture, this introduces the relevant flags to enable the reading
and writing of 128-bit system registers.
The `+d128' -march modifier enables the use of the following ACLE
builtin functions:
* __uint128_t __arm_rsr128(const char *special_register);
* void __arm_wsr128(const char *special_register, __uint128_t value);
and defines the __ARM_FEATURE_SYSREG128 macro to 1.
Finally, the `rcwmask_el1' and `rcwsmask_el1' 128-bit system register
implementations are also reliant on the enablement of the `+the' flag,
which is thus also implemented in this patch.
gcc/ChangeLog:
* config/aarch64/aarch64-arches.def (armv8.9-a): New.
(armv9.4-a): Likewise.
* config/aarch64/aarch64-option-extensions.def (d128): Likewise.
(the): Likewise.
* config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise.
(AARCH64_ISA_V8_9A): Likewise.
(TARGET_ARMV9_4): Likewise.
(AARCH64_ISA_D128): Likewise.
(AARCH64_ISA_THE): Likewise.
(TARGET_D128): Likewise.
* doc/invoke.texi (AArch64 Options): Document new -march flags
and extensions.
---
gcc/config/aarch64/aarch64-arches.def | 2 ++
gcc/config/aarch64/aarch64-c.cc | 1 +
gcc/config/aarch64/aarch64-option-extensions.def | 4 ++++
gcc/config/aarch64/aarch64.h | 15 +++++++++++++++
gcc/doc/invoke.texi | 6 ++++++
5 files changed, 28 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def
index 7ae92aa8e98..becccb801d0 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -39,10 +39,12 @@ AARCH64_ARCH("armv8.5-a", generic, V8_5A, 8, (V8_4A, SB, SSBS, PR
AARCH64_ARCH("armv8.6-a", generic, V8_6A, 8, (V8_5A, I8MM, BF16))
AARCH64_ARCH("armv8.7-a", generic, V8_7A, 8, (V8_6A, LS64))
AARCH64_ARCH("armv8.8-a", generic, V8_8A, 8, (V8_7A, MOPS))
+AARCH64_ARCH("armv8.9-a", generic, V8_9A, 8, (V8_8A))
AARCH64_ARCH("armv8-r", generic, V8R , 8, (V8_4A))
AARCH64_ARCH("armv9-a", generic, V9A , 9, (V8_5A, SVE2))
AARCH64_ARCH("armv9.1-a", generic, V9_1A, 9, (V8_6A, V9A))
AARCH64_ARCH("armv9.2-a", generic, V9_2A, 9, (V8_7A, V9_1A))
AARCH64_ARCH("armv9.3-a", generic, V9_3A, 9, (V8_8A, V9_2A))
+AARCH64_ARCH("armv9.4-a", generic, V9_4A, 9, (V8_9A, V9_3A))
#undef AARCH64_ARCH
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index be8b7236cf9..cacf8e8ed25 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -206,6 +206,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
+ aarch64_def_or_undef (TARGET_D128, "__ARM_FEATURE_SYSREG128", pfile);
/* Not for ACLE, but required to keep "float.h" correct if we switch
target between implementations that do or do not support ARMv8.2-A
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index 825f3bf7758..da31f7c32d1 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -151,4 +151,8 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "")
AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")
+AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
+
+AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
+
#undef AARCH64_OPT_EXTENSION
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 84e6f79ca83..1b3c800ec89 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -219,13 +219,17 @@ enum class aarch64_feature : unsigned char {
#define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH)
#define AARCH64_ISA_V8_7A (aarch64_isa_flags & AARCH64_FL_V8_7A)
#define AARCH64_ISA_V8_8A (aarch64_isa_flags & AARCH64_FL_V8_8A)
+#define AARCH64_ISA_V8_9A (aarch64_isa_flags & AARCH64_FL_V8_9A)
#define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A)
#define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A)
#define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A)
#define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A)
+#define AARCH64_ISA_V9_4A (aarch64_isa_flags & AARCH64_FL_V9_4A)
#define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS)
#define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64)
#define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
+#define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128)
+#define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE)
/* AARCH64_FL options necessary for system register implementation. */
@@ -388,6 +392,17 @@ enum class aarch64_feature : unsigned char {
/* ARMv8.1-A Adv.SIMD support. */
#define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
+/* Armv9.4-A features. */
+#define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A)
+
+/* 128-bit System Registers and Instructions from Armv9.4-a are enabled
+ through +d128. */
+#define TARGET_D128 (AARCH64_ISA_D128)
+
+/* Armv8.9-A/9.4-A Translation Hardening Extension system registers are
+ enabled through +the. */
+#define TARGET_THE (AARCH64_ISA_THE)
+
/* Standard register usage. */
/* 31 64-bit general purpose registers R0-R30:
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6e776a0faa1..88327ce9681 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -20722,10 +20722,12 @@ and the features that they enable by default:
@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
@item @samp{armv8.7-a} @tab Armv8.7-A @tab @samp{armv8.6-a}, @samp{+ls64}
@item @samp{armv8.8-a} @tab Armv8.8-a @tab @samp{armv8.7-a}, @samp{+mops}
+@item @samp{armv8.9-a} @tab Armv8.9-a @tab @samp{armv8.8-a}
@item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve}, @samp{+sve2}
@item @samp{armv9.1-a} @tab Armv9.1-A @tab @samp{armv9-a}, @samp{+bf16}, @samp{+i8mm}
@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+ls64}
@item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
+@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
@item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r}
@end multitable
@@ -21028,6 +21030,10 @@ Enable the Flag Manipulation instructions Extension.
Enable the Pointer Authentication Extension.
@item cssc
Enable the Common Short Sequence Compression instructions.
+@item d128
+Enable support for 128-bit system register read/write instructions.
+@item the
+Enable support for Armv8.9-a/9.4-a translation hardening extension.
@end table
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/5] aarch64: Add support for GCS system registers with the +gcs modifier
2023-11-07 10:30 [PATCH 0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support Victor Do Nascimento
2023-11-07 10:30 ` [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions Victor Do Nascimento
@ 2023-11-07 10:30 ` Victor Do Nascimento
2023-11-07 23:19 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 3/5] aarch64: Sync `aarch64-sys-regs.def' with Binutils Victor Do Nascimento
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Victor Do Nascimento @ 2023-11-07 10:30 UTC (permalink / raw)
To: gcc-patches
Cc: kyrylo.tkachov, richard.sandiford, Richard.Earnshaw,
Victor Do Nascimento
Given the introduction of system registers associated with the Guarded
Control Stack extension to Armv9.4-a in Binutils and their reliance on
the `+gcs' modifier, we implement the necessary changes in GCC to
allow for them to be recognized by the compiler.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (gcs): New.
* config/aarch64/aarch64.h (AARCH64_ISA_GCS): New.
(TARGET_THE): Likewise.
* doc/invoke.texi (AArch64 Options): Describe GCS.
---
gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
gcc/config/aarch64/aarch64.h | 6 ++++++
gcc/doc/invoke.texi | 2 ++
3 files changed, 10 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index da31f7c32d1..e72c039b612 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -155,4 +155,6 @@ AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
+AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
+
#undef AARCH64_OPT_EXTENSION
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 1b3c800ec89..69ef54553d7 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -230,6 +230,7 @@ enum class aarch64_feature : unsigned char {
#define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
#define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128)
#define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE)
+#define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS)
/* AARCH64_FL options necessary for system register implementation. */
@@ -403,6 +404,11 @@ enum class aarch64_feature : unsigned char {
enabled through +the. */
#define TARGET_THE (AARCH64_ISA_THE)
+/* Armv9.4-A Guarded Control Stack extension system registers are
+ enabled through +gcs. */
+#define TARGET_GCS (AARCH64_ISA_GCS)
+
+
/* Standard register usage. */
/* 31 64-bit general purpose registers R0-R30:
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 88327ce9681..88ee1fdb524 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21032,6 +21032,8 @@ Enable the Pointer Authentication Extension.
Enable the Common Short Sequence Compression instructions.
@item d128
Enable support for 128-bit system register read/write instructions.
+@item gcs
+Enable support for Armv9.4-a Guarded Control Stack extension.
@item the
Enable support for Armv8.9-a/9.4-a translation hardening extension.
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/5] aarch64: Sync `aarch64-sys-regs.def' with Binutils.
2023-11-07 10:30 [PATCH 0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support Victor Do Nascimento
2023-11-07 10:30 ` [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions Victor Do Nascimento
2023-11-07 10:30 ` [PATCH 2/5] aarch64: Add support for GCS system registers with the +gcs modifier Victor Do Nascimento
@ 2023-11-07 10:30 ` Victor Do Nascimento
2023-11-07 23:17 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 4/5] aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins Victor Do Nascimento
2023-11-07 10:30 ` [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests Victor Do Nascimento
4 siblings, 1 reply; 13+ messages in thread
From: Victor Do Nascimento @ 2023-11-07 10:30 UTC (permalink / raw)
To: gcc-patches
Cc: kyrylo.tkachov, richard.sandiford, Richard.Earnshaw,
Victor Do Nascimento
This patch updates `aarch64-sys-regs.def', bringing it into sync with
the Binutils source.
gcc/ChangeLog:
* config/aarch64/aarch64-sys-regs.def (par_el1): New.
(rcwmask_el1): Likewise.
(rcwsmask_el1): Likewise.
(ttbr0_el1): Likewise.
(ttbr0_el12): Likewise.
(ttbr0_el2): Likewise.
(ttbr1_el1): Likewise.
(ttbr1_el12): Likewise.
(ttbr1_el2): Likewise.
(vttbr_el2): Likewise.
(gcspr_el0): Likewise.
(gcspr_el1): Likewise.
(gcspr_el12): Likewise.
(gcspr_el2): Likewise.
(gcspr_el3): Likewise.
(gcscre0_el1): Likewise.
(gcscr_el1): Likewise.
(gcscr_el12): Likewise.
(gcscr_el2): Likewise.
(gcscr_el3): Likewise.
---
gcc/config/aarch64/aarch64-sys-regs.def | 30 +++++++++++++++++--------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sys-regs.def b/gcc/config/aarch64/aarch64-sys-regs.def
index d24a2455503..96bdadb0b0f 100644
--- a/gcc/config/aarch64/aarch64-sys-regs.def
+++ b/gcc/config/aarch64/aarch64-sys-regs.def
@@ -419,6 +419,16 @@
SYSREG ("fpcr", CPENC (3,3,4,4,0), 0, AARCH64_NO_FEATURES)
SYSREG ("fpexc32_el2", CPENC (3,4,5,3,0), 0, AARCH64_NO_FEATURES)
SYSREG ("fpsr", CPENC (3,3,4,4,1), 0, AARCH64_NO_FEATURES)
+ SYSREG ("gcspr_el0", CPENC (3,3,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcspr_el1", CPENC (3,0,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcspr_el2", CPENC (3,4,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcspr_el12", CPENC (3,5,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcspr_el3", CPENC (3,6,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcscre0_el1", CPENC (3,0,2,5,2), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcscr_el1", CPENC (3,0,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcscr_el2", CPENC (3,4,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcscr_el12", CPENC (3,5,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
+ SYSREG ("gcscr_el3", CPENC (3,6,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
SYSREG ("gcr_el1", CPENC (3,0,1,0,6), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
SYSREG ("gmid_el1", CPENC (3,1,0,0,4), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
SYSREG ("gpccr_el3", CPENC (3,6,2,1,6), 0, AARCH64_NO_FEATURES)
@@ -584,7 +594,7 @@
SYSREG ("oslar_el1", CPENC (2,0,1,0,4), F_REG_WRITE, AARCH64_NO_FEATURES)
SYSREG ("oslsr_el1", CPENC (2,0,1,1,4), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("pan", CPENC (3,0,4,2,3), F_ARCHEXT, AARCH64_FEATURE (PAN))
- SYSREG ("par_el1", CPENC (3,0,7,4,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("par_el1", CPENC (3,0,7,4,0), F_REG_128, AARCH64_NO_FEATURES)
SYSREG ("pmbidr_el1", CPENC (3,0,9,10,7), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmblimitr_el1", CPENC (3,0,9,10,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmbptr_el1", CPENC (3,0,9,10,1), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
@@ -746,6 +756,8 @@
SYSREG ("prlar_el2", CPENC (3,4,6,8,1), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("prselr_el1", CPENC (3,0,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("prselr_el2", CPENC (3,4,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R))
+ SYSREG ("rcwmask_el1", CPENC (3,0,13,0,6), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (THE))
+ SYSREG ("rcwsmask_el1", CPENC (3,0,13,0,3), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (THE))
SYSREG ("revidr_el1", CPENC (3,0,0,0,6), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("rgsr_el1", CPENC (3,0,1,0,5), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
SYSREG ("rmr_el1", CPENC (3,0,12,0,2), 0, AARCH64_NO_FEATURES)
@@ -1034,13 +1046,13 @@
SYSREG ("trfcr_el1", CPENC (3,0,1,2,1), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("trfcr_el12", CPENC (3,5,1,2,1), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("trfcr_el2", CPENC (3,4,1,2,1), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
- SYSREG ("ttbr0_el1", CPENC (3,0,2,0,0), 0, AARCH64_NO_FEATURES)
- SYSREG ("ttbr0_el12", CPENC (3,5,2,0,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
- SYSREG ("ttbr0_el2", CPENC (3,4,2,0,0), F_ARCHEXT, AARCH64_FEATURE (V8A))
+ SYSREG ("ttbr0_el1", CPENC (3,0,2,0,0), F_REG_128, AARCH64_NO_FEATURES)
+ SYSREG ("ttbr0_el12", CPENC (3,5,2,0,0), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8_1A))
+ SYSREG ("ttbr0_el2", CPENC (3,4,2,0,0), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8A))
SYSREG ("ttbr0_el3", CPENC (3,6,2,0,0), 0, AARCH64_NO_FEATURES)
- SYSREG ("ttbr1_el1", CPENC (3,0,2,0,1), 0, AARCH64_NO_FEATURES)
- SYSREG ("ttbr1_el12", CPENC (3,5,2,0,1), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
- SYSREG ("ttbr1_el2", CPENC (3,4,2,0,1), F_ARCHEXT, AARCH64_FEATURES (2, V8A, V8_1A))
+ SYSREG ("ttbr1_el1", CPENC (3,0,2,0,1), F_REG_128, AARCH64_NO_FEATURES)
+ SYSREG ("ttbr1_el12", CPENC (3,5,2,0,1), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8_1A))
+ SYSREG ("ttbr1_el2", CPENC (3,4,2,0,1), F_ARCHEXT|F_REG_128, AARCH64_FEATURES (2, V8A, V8_1A))
SYSREG ("uao", CPENC (3,0,4,2,4), F_ARCHEXT, AARCH64_FEATURE (V8_2A))
SYSREG ("vbar_el1", CPENC (3,0,12,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vbar_el12", CPENC (3,5,12,0,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
@@ -1057,8 +1069,8 @@
SYSREG ("vstcr_el2", CPENC (3,4,2,6,2), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("vsttbr_el2", CPENC (3,4,2,6,0), F_ARCHEXT, AARCH64_FEATURES (2, V8A, V8_4A))
SYSREG ("vtcr_el2", CPENC (3,4,2,1,2), 0, AARCH64_NO_FEATURES)
- SYSREG ("vttbr_el2", CPENC (3,4,2,1,0), F_ARCHEXT, AARCH64_FEATURE (V8A))
+ SYSREG ("vttbr_el2", CPENC (3,4,2,1,0), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8A))
SYSREG ("zcr_el1", CPENC (3,0,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
SYSREG ("zcr_el12", CPENC (3,5,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
SYSREG ("zcr_el2", CPENC (3,4,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
- SYSREG ("zcr_el3", CPENC (3,6,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
\ No newline at end of file
+ SYSREG ("zcr_el3", CPENC (3,6,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/5] aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins
2023-11-07 10:30 [PATCH 0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support Victor Do Nascimento
` (2 preceding siblings ...)
2023-11-07 10:30 ` [PATCH 3/5] aarch64: Sync `aarch64-sys-regs.def' with Binutils Victor Do Nascimento
@ 2023-11-07 10:30 ` Victor Do Nascimento
2023-11-07 23:14 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests Victor Do Nascimento
4 siblings, 1 reply; 13+ messages in thread
From: Victor Do Nascimento @ 2023-11-07 10:30 UTC (permalink / raw)
To: gcc-patches
Cc: kyrylo.tkachov, richard.sandiford, Richard.Earnshaw,
Victor Do Nascimento
Implement the ACLE builtins for 128-bit system register manipulation:
* __uint128_t __arm_rsr128(const char *special_register);
* void __arm_wsr128(const char *special_register, __uint128_t value);
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc (AARCH64_RSR128): New
`enum aarch64_builtins' value.
(AARCH64_WSR128): Likewise.
(aarch64_init_rwsr_builtins): Init `__builtin_aarch64_rsr128'
and `__builtin_aarch64_wsr128' builtins.
(aarch64_expand_rwsr_builtin): Extend function to handle
`__builtin_aarch64_{rsr|wsr}128'.
* config/aarch64/aarch64-protos.h (aarch64_retrieve_sysreg):
Update function signature.
* config/aarch64/aarch64.cc (F_REG_128): New.
(aarch64_retrieve_sysreg): Add 128-bit register mode check.
* config/aarch64/aarch64.md (UNSPEC_SYSREG_RTI): New.
(UNSPEC_SYSREG_WTI): Likewise.
(aarch64_read_sysregti): Likewise.
(aarch64_write_sysregti): Likewise.
---
gcc/config/aarch64/aarch64-builtins.cc | 50 +++++++++++++++++++++-----
gcc/config/aarch64/aarch64-protos.h | 2 +-
gcc/config/aarch64/aarch64.cc | 6 +++-
gcc/config/aarch64/aarch64.md | 18 ++++++++++
gcc/config/aarch64/arm_acle.h | 11 ++++++
5 files changed, 77 insertions(+), 10 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index c5f20f68bca..40d3788b5e0 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -815,11 +815,13 @@ enum aarch64_builtins
AARCH64_RSR64,
AARCH64_RSRF,
AARCH64_RSRF64,
+ AARCH64_RSR128,
AARCH64_WSR,
AARCH64_WSRP,
AARCH64_WSR64,
AARCH64_WSRF,
AARCH64_WSRF64,
+ AARCH64_WSR128,
AARCH64_BUILTIN_MAX
};
@@ -1842,6 +1844,10 @@ aarch64_init_rwsr_builtins (void)
= build_function_type_list (double_type_node, const_char_ptr_type, NULL);
AARCH64_INIT_RWSR_BUILTINS_DECL (RSRF64, rsrf64, fntype);
+ fntype
+ = build_function_type_list (uint128_type_node, const_char_ptr_type, NULL);
+ AARCH64_INIT_RWSR_BUILTINS_DECL (RSR128, rsr128, fntype);
+
fntype
= build_function_type_list (void_type_node, const_char_ptr_type,
uint32_type_node, NULL);
@@ -1867,6 +1873,12 @@ aarch64_init_rwsr_builtins (void)
= build_function_type_list (void_type_node, const_char_ptr_type,
double_type_node, NULL);
AARCH64_INIT_RWSR_BUILTINS_DECL (WSRF64, wsrf64, fntype);
+
+ fntype
+ = build_function_type_list (void_type_node, const_char_ptr_type,
+ uint128_type_node, NULL);
+ AARCH64_INIT_RWSR_BUILTINS_DECL (WSR128, wsr128, fntype);
+
}
/* Initialize the memory tagging extension (MTE) builtins. */
@@ -2710,6 +2722,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
tree arg0, arg1;
rtx const_str, input_val, subreg;
enum machine_mode mode;
+ enum insn_code icode;
class expand_operand ops[2];
arg0 = CALL_EXPR_ARG (exp, 0);
@@ -2718,7 +2731,18 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
|| fcode == AARCH64_WSRP
|| fcode == AARCH64_WSR64
|| fcode == AARCH64_WSRF
- || fcode == AARCH64_WSRF64);
+ || fcode == AARCH64_WSRF64
+ || fcode == AARCH64_WSR128);
+
+ bool op128 = (fcode == AARCH64_RSR128 || fcode == AARCH64_WSR128);
+ enum machine_mode sysreg_mode = op128 ? TImode : DImode;
+
+ if (op128 && !TARGET_D128)
+ {
+ error_at (EXPR_LOCATION (exp), "128-bit system register suppport requires "
+ "the +d128 Armv9.4-A extension");
+ return const0_rtx;
+ }
/* Argument 0 (system register name) must be a string literal. */
gcc_assert (TREE_CODE (arg0) == ADDR_EXPR
@@ -2741,7 +2765,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
sysreg_name[pos] = TOLOWER (sysreg_name[pos]);
const char* name_output = aarch64_retrieve_sysreg ((const char *) sysreg_name,
- write_op);
+ write_op, op128);
if (name_output == NULL)
{
error_at (EXPR_LOCATION (exp), "invalid system register name provided");
@@ -2760,13 +2784,17 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
mode = TYPE_MODE (TREE_TYPE (arg1));
input_val = copy_to_mode_reg (mode, expand_normal (arg1));
+ icode = (op128 ? CODE_FOR_aarch64_write_sysregti
+ : CODE_FOR_aarch64_write_sysregdi);
+
switch (fcode)
{
case AARCH64_WSR:
case AARCH64_WSRP:
case AARCH64_WSR64:
case AARCH64_WSRF64:
- subreg = lowpart_subreg (DImode, input_val, mode);
+ case AARCH64_WSR128:
+ subreg = lowpart_subreg (sysreg_mode, input_val, mode);
break;
case AARCH64_WSRF:
subreg = gen_lowpart_SUBREG (SImode, input_val);
@@ -2775,8 +2803,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
}
create_fixed_operand (&ops[0], const_str);
- create_input_operand (&ops[1], subreg, DImode);
- expand_insn (CODE_FOR_aarch64_write_sysregdi, 2, ops);
+ create_input_operand (&ops[1], subreg, sysreg_mode);
+ expand_insn (icode, 2, ops);
return target;
}
@@ -2784,10 +2812,13 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
/* Read operations are implied by !write_op. */
gcc_assert (call_expr_nargs (exp) == 1);
+ icode = (op128 ? CODE_FOR_aarch64_read_sysregti
+ : CODE_FOR_aarch64_read_sysregdi);
+
/* Emit the initial read_sysregdi rtx. */
- create_output_operand (&ops[0], target, DImode);
+ create_output_operand (&ops[0], target, sysreg_mode);
create_fixed_operand (&ops[1], const_str);
- expand_insn (CODE_FOR_aarch64_read_sysregdi, 2, ops);
+ expand_insn (icode, 2, ops);
target = ops[0].value;
/* Do any necessary post-processing on the result. */
@@ -2797,7 +2828,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
case AARCH64_RSRP:
case AARCH64_RSR64:
case AARCH64_RSRF64:
- return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, DImode);
+ case AARCH64_RSR128:
+ return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
case AARCH64_RSRF:
subreg = gen_lowpart_SUBREG (SImode, target);
return gen_lowpart_SUBREG (SFmode, subreg);
@@ -3048,11 +3080,13 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,
case AARCH64_RSR64:
case AARCH64_RSRF:
case AARCH64_RSRF64:
+ case AARCH64_RSR128:
case AARCH64_WSR:
case AARCH64_WSRP:
case AARCH64_WSR64:
case AARCH64_WSRF:
case AARCH64_WSRF64:
+ case AARCH64_WSR128:
return aarch64_expand_rwsr_builtin (exp, target, fcode);
}
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index dbd486cfea4..6a306134c2d 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -831,7 +831,7 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);
bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
enum simd_immediate_check w = AARCH64_CHECK_MOV);
bool aarch64_valid_sysreg_name_p (const char *);
-const char *aarch64_retrieve_sysreg (const char *, bool);
+const char *aarch64_retrieve_sysreg (const char *, bool, bool);
rtx aarch64_check_zero_based_sve_index_immediate (rtx);
bool aarch64_sve_index_immediate_p (rtx);
bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index c0d75f167be..ff7e75e1f19 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -2846,6 +2846,8 @@ typedef struct {
#define F_ARCHEXT (1 << 4)
/* Flag indicating register name is alias for another system register. */
#define F_REG_ALIAS (1 << 5)
+/* Flag indicatinig registers which may be implemented with 128-bits. */
+#define F_REG_128 (1 << 6)
/* Database of system registers, their encodings and architectural
requirements. */
@@ -28245,7 +28247,7 @@ aarch64_valid_sysreg_name_p (const char *regname)
name, otherwise NULL. WRITE_P is true iff the register is being
written to. */
const char *
-aarch64_retrieve_sysreg (const char *regname, bool write_p)
+aarch64_retrieve_sysreg (const char *regname, bool write_p, bool is128op)
{
const sysreg_t *sysreg = aarch64_lookup_sysreg_map (regname);
if (sysreg == NULL)
@@ -28255,6 +28257,8 @@ aarch64_retrieve_sysreg (const char *regname, bool write_p)
else
return NULL;
}
+ if (is128op && !(sysreg->properties & F_REG_128))
+ return NULL;
if ((write_p && (sysreg->properties & F_REG_READ))
|| (!write_p && (sysreg->properties & F_REG_WRITE)))
return NULL;
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index aee8f8ad65a..3be813efcd4 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -282,7 +282,9 @@
UNSPEC_RDFFR
UNSPEC_WRFFR
UNSPEC_SYSREG_RDI
+ UNSPEC_SYSREG_RTI
UNSPEC_SYSREG_WDI
+ UNSPEC_SYSREG_WTI
;; Represents an SVE-style lane index, in which the indexing applies
;; within the containing 128-bit block.
UNSPEC_SVE_LANE_SELECT
@@ -486,6 +488,14 @@
"mrs\t%x0, %1"
)
+(define_insn "aarch64_read_sysregti"
+ [(set (match_operand:TI 0 "register_operand" "=r")
+ (unspec_volatile:TI [(match_operand 1 "aarch64_sysreg_string" "")]
+ UNSPEC_SYSREG_RTI))]
+ "TARGET_D128"
+ "mrrs\t%x0, %H0, %x1"
+)
+
(define_insn "aarch64_write_sysregdi"
[(unspec_volatile:DI [(match_operand 0 "aarch64_sysreg_string" "")
(match_operand:DI 1 "register_operand" "rZ")]
@@ -494,6 +504,14 @@
"msr\t%0, %x1"
)
+(define_insn "aarch64_write_sysregti"
+ [(unspec_volatile:TI [(match_operand 0 "aarch64_sysreg_string" "")
+ (match_operand:TI 1 "register_operand" "r")]
+ UNSPEC_SYSREG_WTI)]
+ "TARGET_D128"
+ "msrr\t%x0, %x1, %H1"
+)
+
(define_insn "indirect_jump"
[(set (pc) (match_operand:DI 0 "register_operand" "r"))]
""
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index 71ada878299..80282b361a4 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -344,6 +344,17 @@ __rndrrs (uint64_t *__res)
#define __arm_wsrf64(__regname, __value) \
__builtin_aarch64_wsrf64 (__regname, __value)
+#pragma GCC push_options
+#pragma GCC target ("+nothing+d128")
+
+#define __arm_rsr128(__regname) \
+ __builtin_aarch64_rsr128 (__regname)
+
+#define __arm_wsr128(__regname, __value) \
+ __builtin_aarch64_wsr128 (__regname, __value)
+
+#pragma GCC pop_options
+
#ifdef __cplusplus
}
#endif
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests
2023-11-07 10:30 [PATCH 0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support Victor Do Nascimento
` (3 preceding siblings ...)
2023-11-07 10:30 ` [PATCH 4/5] aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins Victor Do Nascimento
@ 2023-11-07 10:30 ` Victor Do Nascimento
2023-11-07 22:51 ` Richard Sandiford
4 siblings, 1 reply; 13+ messages in thread
From: Victor Do Nascimento @ 2023-11-07 10:30 UTC (permalink / raw)
To: gcc-patches
Cc: kyrylo.tkachov, richard.sandiford, Richard.Earnshaw,
Victor Do Nascimento
Extend existing unit tests for the ACLE system register manipulation
functions to include 128-bit tests.
gcc/testsuite/ChangeLog:
* gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New.
(set_wsr128): Likewise.
---
gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 30 +++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
index 3af4b960306..e7725022316 100644
--- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
+++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
@@ -1,11 +1,15 @@
/* Test the __arm_[r,w]sr ACLE intrinsics family. */
/* Check that function variants for different data types handle types correctly. */
/* { dg-do compile } */
-/* { dg-options "-O1 -march=armv8.4-a" } */
+/* { dg-options "-O1 -march=armv9.4-a+d128" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <arm_acle.h>
+#ifndef __ARM_FEATURE_SYSREG128
+#error "__ARM_FEATURE_SYSREG128 feature macro not defined."
+#endif
+
/*
** get_rsr:
** ...
@@ -66,6 +70,17 @@ get_rsrf64 ()
return __arm_rsrf64("trcseqstr");
}
+/*
+** get_rsr128:
+** mrrs x0, x1, s3_0_c7_c4_0
+** ...
+*/
+__uint128_t
+get_rsr128 ()
+{
+ __arm_rsr128("par_el1");
+}
+
/*
** set_wsr32:
** ...
@@ -129,6 +144,18 @@ set_wsrf64(double a)
__arm_wsrf64("trcseqstr", a);
}
+/*
+** set_wsr128:
+** ...
+** msrr s3_0_c7_c4_0, x0, x1
+** ...
+*/
+void
+set_wsr128 (__uint128_t c)
+{
+ __arm_wsr128 ("par_el1", c);
+}
+
/*
** set_custom:
** ...
@@ -142,3 +169,4 @@ void set_custom()
__uint64_t b = __arm_rsr64("S1_2_C3_C4_5");
__arm_wsr64("S1_2_C3_C4_5", b);
}
+
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests
2023-11-07 10:30 ` [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests Victor Do Nascimento
@ 2023-11-07 22:51 ` Richard Sandiford
2023-11-08 9:49 ` Christophe Lyon
0 siblings, 1 reply; 13+ messages in thread
From: Richard Sandiford @ 2023-11-07 22:51 UTC (permalink / raw)
To: Victor Do Nascimento; +Cc: gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Victor Do Nascimento <victor.donascimento@arm.com> writes:
> Extend existing unit tests for the ACLE system register manipulation
> functions to include 128-bit tests.
>
> gcc/testsuite/ChangeLog:
>
> * gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New.
> (set_wsr128): Likewise.
> ---
> gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 30 +++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
> index 3af4b960306..e7725022316 100644
> --- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
> +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
> @@ -1,11 +1,15 @@
> /* Test the __arm_[r,w]sr ACLE intrinsics family. */
> /* Check that function variants for different data types handle types correctly. */
> /* { dg-do compile } */
> -/* { dg-options "-O1 -march=armv8.4-a" } */
> +/* { dg-options "-O1 -march=armv9.4-a+d128" } */
> /* { dg-final { check-function-bodies "**" "" } } */
I'm nervous about having our only tests for 64-bit reads and writes
using such a high minimum version. Could the file instead be compiled
without any minimum architecture and have tests that work with plain
-march=armv8-a? Then the test could switch to other architectures
where necessary using #pragam GCC target. This test...
> #include <arm_acle.h>
>
> +#ifndef __ARM_FEATURE_SYSREG128
> +#error "__ARM_FEATURE_SYSREG128 feature macro not defined."
> +#endif
> +
...would still work. with a #pragma GCC target.
Thanks,
Richard
> /*
> ** get_rsr:
> ** ...
> @@ -66,6 +70,17 @@ get_rsrf64 ()
> return __arm_rsrf64("trcseqstr");
> }
>
> +/*
> +** get_rsr128:
> +** mrrs x0, x1, s3_0_c7_c4_0
> +** ...
> +*/
> +__uint128_t
> +get_rsr128 ()
> +{
> + __arm_rsr128("par_el1");
> +}
> +
> /*
> ** set_wsr32:
> ** ...
> @@ -129,6 +144,18 @@ set_wsrf64(double a)
> __arm_wsrf64("trcseqstr", a);
> }
>
> +/*
> +** set_wsr128:
> +** ...
> +** msrr s3_0_c7_c4_0, x0, x1
> +** ...
> +*/
> +void
> +set_wsr128 (__uint128_t c)
> +{
> + __arm_wsr128 ("par_el1", c);
> +}
> +
> /*
> ** set_custom:
> ** ...
> @@ -142,3 +169,4 @@ void set_custom()
> __uint64_t b = __arm_rsr64("S1_2_C3_C4_5");
> __arm_wsr64("S1_2_C3_C4_5", b);
> }
> +
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins
2023-11-07 10:30 ` [PATCH 4/5] aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins Victor Do Nascimento
@ 2023-11-07 23:14 ` Richard Sandiford
0 siblings, 0 replies; 13+ messages in thread
From: Richard Sandiford @ 2023-11-07 23:14 UTC (permalink / raw)
To: Victor Do Nascimento; +Cc: gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Victor Do Nascimento <victor.donascimento@arm.com> writes:
> Implement the ACLE builtins for 128-bit system register manipulation:
>
> * __uint128_t __arm_rsr128(const char *special_register);
> * void __arm_wsr128(const char *special_register, __uint128_t value);
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-builtins.cc (AARCH64_RSR128): New
> `enum aarch64_builtins' value.
> (AARCH64_WSR128): Likewise.
> (aarch64_init_rwsr_builtins): Init `__builtin_aarch64_rsr128'
> and `__builtin_aarch64_wsr128' builtins.
> (aarch64_expand_rwsr_builtin): Extend function to handle
> `__builtin_aarch64_{rsr|wsr}128'.
> * config/aarch64/aarch64-protos.h (aarch64_retrieve_sysreg):
> Update function signature.
> * config/aarch64/aarch64.cc (F_REG_128): New.
> (aarch64_retrieve_sysreg): Add 128-bit register mode check.
> * config/aarch64/aarch64.md (UNSPEC_SYSREG_RTI): New.
> (UNSPEC_SYSREG_WTI): Likewise.
> (aarch64_read_sysregti): Likewise.
> (aarch64_write_sysregti): Likewise.
> ---
> gcc/config/aarch64/aarch64-builtins.cc | 50 +++++++++++++++++++++-----
> gcc/config/aarch64/aarch64-protos.h | 2 +-
> gcc/config/aarch64/aarch64.cc | 6 +++-
> gcc/config/aarch64/aarch64.md | 18 ++++++++++
> gcc/config/aarch64/arm_acle.h | 11 ++++++
> 5 files changed, 77 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
> index c5f20f68bca..40d3788b5e0 100644
> --- a/gcc/config/aarch64/aarch64-builtins.cc
> +++ b/gcc/config/aarch64/aarch64-builtins.cc
> @@ -815,11 +815,13 @@ enum aarch64_builtins
> AARCH64_RSR64,
> AARCH64_RSRF,
> AARCH64_RSRF64,
> + AARCH64_RSR128,
> AARCH64_WSR,
> AARCH64_WSRP,
> AARCH64_WSR64,
> AARCH64_WSRF,
> AARCH64_WSRF64,
> + AARCH64_WSR128,
> AARCH64_BUILTIN_MAX
> };
>
> @@ -1842,6 +1844,10 @@ aarch64_init_rwsr_builtins (void)
> = build_function_type_list (double_type_node, const_char_ptr_type, NULL);
> AARCH64_INIT_RWSR_BUILTINS_DECL (RSRF64, rsrf64, fntype);
>
> + fntype
> + = build_function_type_list (uint128_type_node, const_char_ptr_type, NULL);
> + AARCH64_INIT_RWSR_BUILTINS_DECL (RSR128, rsr128, fntype);
> +
> fntype
> = build_function_type_list (void_type_node, const_char_ptr_type,
> uint32_type_node, NULL);
> @@ -1867,6 +1873,12 @@ aarch64_init_rwsr_builtins (void)
> = build_function_type_list (void_type_node, const_char_ptr_type,
> double_type_node, NULL);
> AARCH64_INIT_RWSR_BUILTINS_DECL (WSRF64, wsrf64, fntype);
> +
> + fntype
> + = build_function_type_list (void_type_node, const_char_ptr_type,
> + uint128_type_node, NULL);
> + AARCH64_INIT_RWSR_BUILTINS_DECL (WSR128, wsr128, fntype);
> +
> }
>
> /* Initialize the memory tagging extension (MTE) builtins. */
> @@ -2710,6 +2722,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
> tree arg0, arg1;
> rtx const_str, input_val, subreg;
> enum machine_mode mode;
> + enum insn_code icode;
> class expand_operand ops[2];
>
> arg0 = CALL_EXPR_ARG (exp, 0);
> @@ -2718,7 +2731,18 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
> || fcode == AARCH64_WSRP
> || fcode == AARCH64_WSR64
> || fcode == AARCH64_WSRF
> - || fcode == AARCH64_WSRF64);
> + || fcode == AARCH64_WSRF64
> + || fcode == AARCH64_WSR128);
> +
> + bool op128 = (fcode == AARCH64_RSR128 || fcode == AARCH64_WSR128);
> + enum machine_mode sysreg_mode = op128 ? TImode : DImode;
> +
> + if (op128 && !TARGET_D128)
> + {
> + error_at (EXPR_LOCATION (exp), "128-bit system register suppport requires "
> + "the +d128 Armv9.4-A extension");
Elsewhere we've put feature names in quotes, since they're code
or code-adjacent. Probably also best to drop Armv9.4-A part,
since the requirement is tied only to +d128. So:
error_at (EXPR_LOCATION (exp),
"128-bit system register suppport requires the %<d128%>"
" extension");
(formatted that way to avoid a long line).
> + return const0_rtx;
> + }
>
> /* Argument 0 (system register name) must be a string literal. */
> gcc_assert (TREE_CODE (arg0) == ADDR_EXPR
> @@ -2741,7 +2765,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
> sysreg_name[pos] = TOLOWER (sysreg_name[pos]);
>
> const char* name_output = aarch64_retrieve_sysreg ((const char *) sysreg_name,
> - write_op);
> + write_op, op128);
> if (name_output == NULL)
> {
> error_at (EXPR_LOCATION (exp), "invalid system register name provided");
> @@ -2760,13 +2784,17 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
> mode = TYPE_MODE (TREE_TYPE (arg1));
> input_val = copy_to_mode_reg (mode, expand_normal (arg1));
>
> + icode = (op128 ? CODE_FOR_aarch64_write_sysregti
> + : CODE_FOR_aarch64_write_sysregdi);
> +
> switch (fcode)
> {
> case AARCH64_WSR:
> case AARCH64_WSRP:
> case AARCH64_WSR64:
> case AARCH64_WSRF64:
> - subreg = lowpart_subreg (DImode, input_val, mode);
> + case AARCH64_WSR128:
> + subreg = lowpart_subreg (sysreg_mode, input_val, mode);
> break;
> case AARCH64_WSRF:
> subreg = gen_lowpart_SUBREG (SImode, input_val);
> @@ -2775,8 +2803,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
> }
>
> create_fixed_operand (&ops[0], const_str);
> - create_input_operand (&ops[1], subreg, DImode);
> - expand_insn (CODE_FOR_aarch64_write_sysregdi, 2, ops);
> + create_input_operand (&ops[1], subreg, sysreg_mode);
> + expand_insn (icode, 2, ops);
>
> return target;
> }
> @@ -2784,10 +2812,13 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
> /* Read operations are implied by !write_op. */
> gcc_assert (call_expr_nargs (exp) == 1);
>
> + icode = (op128 ? CODE_FOR_aarch64_read_sysregti
> + : CODE_FOR_aarch64_read_sysregdi);
> +
> /* Emit the initial read_sysregdi rtx. */
> - create_output_operand (&ops[0], target, DImode);
> + create_output_operand (&ops[0], target, sysreg_mode);
> create_fixed_operand (&ops[1], const_str);
> - expand_insn (CODE_FOR_aarch64_read_sysregdi, 2, ops);
> + expand_insn (icode, 2, ops);
> target = ops[0].value;
>
> /* Do any necessary post-processing on the result. */
> @@ -2797,7 +2828,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
> case AARCH64_RSRP:
> case AARCH64_RSR64:
> case AARCH64_RSRF64:
> - return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, DImode);
> + case AARCH64_RSR128:
> + return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
> case AARCH64_RSRF:
> subreg = gen_lowpart_SUBREG (SImode, target);
> return gen_lowpart_SUBREG (SFmode, subreg);
> @@ -3048,11 +3080,13 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,
> case AARCH64_RSR64:
> case AARCH64_RSRF:
> case AARCH64_RSRF64:
> + case AARCH64_RSR128:
> case AARCH64_WSR:
> case AARCH64_WSRP:
> case AARCH64_WSR64:
> case AARCH64_WSRF:
> case AARCH64_WSRF64:
> + case AARCH64_WSR128:
> return aarch64_expand_rwsr_builtin (exp, target, fcode);
> }
>
> diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
> index dbd486cfea4..6a306134c2d 100644
> --- a/gcc/config/aarch64/aarch64-protos.h
> +++ b/gcc/config/aarch64/aarch64-protos.h
> @@ -831,7 +831,7 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);
> bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
> enum simd_immediate_check w = AARCH64_CHECK_MOV);
> bool aarch64_valid_sysreg_name_p (const char *);
> -const char *aarch64_retrieve_sysreg (const char *, bool);
> +const char *aarch64_retrieve_sysreg (const char *, bool, bool);
> rtx aarch64_check_zero_based_sve_index_immediate (rtx);
> bool aarch64_sve_index_immediate_p (rtx);
> bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index c0d75f167be..ff7e75e1f19 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -2846,6 +2846,8 @@ typedef struct {
> #define F_ARCHEXT (1 << 4)
> /* Flag indicating register name is alias for another system register. */
> #define F_REG_ALIAS (1 << 5)
> +/* Flag indicatinig registers which may be implemented with 128-bits. */
> +#define F_REG_128 (1 << 6)
>
> /* Database of system registers, their encodings and architectural
> requirements. */
> @@ -28245,7 +28247,7 @@ aarch64_valid_sysreg_name_p (const char *regname)
> name, otherwise NULL. WRITE_P is true iff the register is being
> written to. */
> const char *
> -aarch64_retrieve_sysreg (const char *regname, bool write_p)
> +aarch64_retrieve_sysreg (const char *regname, bool write_p, bool is128op)
> {
> const sysreg_t *sysreg = aarch64_lookup_sysreg_map (regname);
> if (sysreg == NULL)
The comment should describe the new parameter.
Looks good otherwise.
Thanks,
Richard
> @@ -28255,6 +28257,8 @@ aarch64_retrieve_sysreg (const char *regname, bool write_p)
> else
> return NULL;
> }
> + if (is128op && !(sysreg->properties & F_REG_128))
> + return NULL;
> if ((write_p && (sysreg->properties & F_REG_READ))
> || (!write_p && (sysreg->properties & F_REG_WRITE)))
> return NULL;
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index aee8f8ad65a..3be813efcd4 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -282,7 +282,9 @@
> UNSPEC_RDFFR
> UNSPEC_WRFFR
> UNSPEC_SYSREG_RDI
> + UNSPEC_SYSREG_RTI
> UNSPEC_SYSREG_WDI
> + UNSPEC_SYSREG_WTI
> ;; Represents an SVE-style lane index, in which the indexing applies
> ;; within the containing 128-bit block.
> UNSPEC_SVE_LANE_SELECT
> @@ -486,6 +488,14 @@
> "mrs\t%x0, %1"
> )
>
> +(define_insn "aarch64_read_sysregti"
> + [(set (match_operand:TI 0 "register_operand" "=r")
> + (unspec_volatile:TI [(match_operand 1 "aarch64_sysreg_string" "")]
> + UNSPEC_SYSREG_RTI))]
> + "TARGET_D128"
> + "mrrs\t%x0, %H0, %x1"
> +)
> +
> (define_insn "aarch64_write_sysregdi"
> [(unspec_volatile:DI [(match_operand 0 "aarch64_sysreg_string" "")
> (match_operand:DI 1 "register_operand" "rZ")]
> @@ -494,6 +504,14 @@
> "msr\t%0, %x1"
> )
>
> +(define_insn "aarch64_write_sysregti"
> + [(unspec_volatile:TI [(match_operand 0 "aarch64_sysreg_string" "")
> + (match_operand:TI 1 "register_operand" "r")]
> + UNSPEC_SYSREG_WTI)]
> + "TARGET_D128"
> + "msrr\t%x0, %x1, %H1"
> +)
> +
> (define_insn "indirect_jump"
> [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
> ""
> diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
> index 71ada878299..80282b361a4 100644
> --- a/gcc/config/aarch64/arm_acle.h
> +++ b/gcc/config/aarch64/arm_acle.h
> @@ -344,6 +344,17 @@ __rndrrs (uint64_t *__res)
> #define __arm_wsrf64(__regname, __value) \
> __builtin_aarch64_wsrf64 (__regname, __value)
>
> +#pragma GCC push_options
> +#pragma GCC target ("+nothing+d128")
> +
> +#define __arm_rsr128(__regname) \
> + __builtin_aarch64_rsr128 (__regname)
> +
> +#define __arm_wsr128(__regname, __value) \
> + __builtin_aarch64_wsr128 (__regname, __value)
> +
> +#pragma GCC pop_options
> +
> #ifdef __cplusplus
> }
> #endif
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/5] aarch64: Sync `aarch64-sys-regs.def' with Binutils.
2023-11-07 10:30 ` [PATCH 3/5] aarch64: Sync `aarch64-sys-regs.def' with Binutils Victor Do Nascimento
@ 2023-11-07 23:17 ` Richard Sandiford
0 siblings, 0 replies; 13+ messages in thread
From: Richard Sandiford @ 2023-11-07 23:17 UTC (permalink / raw)
To: Victor Do Nascimento; +Cc: gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Victor Do Nascimento <victor.donascimento@arm.com> writes:
> This patch updates `aarch64-sys-regs.def', bringing it into sync with
> the Binutils source.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-sys-regs.def (par_el1): New.
> (rcwmask_el1): Likewise.
> (rcwsmask_el1): Likewise.
> (ttbr0_el1): Likewise.
> (ttbr0_el12): Likewise.
> (ttbr0_el2): Likewise.
> (ttbr1_el1): Likewise.
> (ttbr1_el12): Likewise.
> (ttbr1_el2): Likewise.
> (vttbr_el2): Likewise.
> (gcspr_el0): Likewise.
> (gcspr_el1): Likewise.
> (gcspr_el12): Likewise.
> (gcspr_el2): Likewise.
> (gcspr_el3): Likewise.
> (gcscre0_el1): Likewise.
> (gcscr_el1): Likewise.
> (gcscr_el12): Likewise.
> (gcscr_el2): Likewise.
> (gcscr_el3): Likewise.
LGTM. Process-wise, I think we should consider simple copies of this file
from binutils to be pre-approved/obvious.
Thanks,
Richard
> ---
> gcc/config/aarch64/aarch64-sys-regs.def | 30 +++++++++++++++++--------
> 1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-sys-regs.def b/gcc/config/aarch64/aarch64-sys-regs.def
> index d24a2455503..96bdadb0b0f 100644
> --- a/gcc/config/aarch64/aarch64-sys-regs.def
> +++ b/gcc/config/aarch64/aarch64-sys-regs.def
> @@ -419,6 +419,16 @@
> SYSREG ("fpcr", CPENC (3,3,4,4,0), 0, AARCH64_NO_FEATURES)
> SYSREG ("fpexc32_el2", CPENC (3,4,5,3,0), 0, AARCH64_NO_FEATURES)
> SYSREG ("fpsr", CPENC (3,3,4,4,1), 0, AARCH64_NO_FEATURES)
> + SYSREG ("gcspr_el0", CPENC (3,3,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcspr_el1", CPENC (3,0,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcspr_el2", CPENC (3,4,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcspr_el12", CPENC (3,5,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcspr_el3", CPENC (3,6,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcscre0_el1", CPENC (3,0,2,5,2), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcscr_el1", CPENC (3,0,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcscr_el2", CPENC (3,4,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcscr_el12", CPENC (3,5,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
> + SYSREG ("gcscr_el3", CPENC (3,6,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS))
> SYSREG ("gcr_el1", CPENC (3,0,1,0,6), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
> SYSREG ("gmid_el1", CPENC (3,1,0,0,4), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
> SYSREG ("gpccr_el3", CPENC (3,6,2,1,6), 0, AARCH64_NO_FEATURES)
> @@ -584,7 +594,7 @@
> SYSREG ("oslar_el1", CPENC (2,0,1,0,4), F_REG_WRITE, AARCH64_NO_FEATURES)
> SYSREG ("oslsr_el1", CPENC (2,0,1,1,4), F_REG_READ, AARCH64_NO_FEATURES)
> SYSREG ("pan", CPENC (3,0,4,2,3), F_ARCHEXT, AARCH64_FEATURE (PAN))
> - SYSREG ("par_el1", CPENC (3,0,7,4,0), 0, AARCH64_NO_FEATURES)
> + SYSREG ("par_el1", CPENC (3,0,7,4,0), F_REG_128, AARCH64_NO_FEATURES)
> SYSREG ("pmbidr_el1", CPENC (3,0,9,10,7), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (PROFILE))
> SYSREG ("pmblimitr_el1", CPENC (3,0,9,10,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
> SYSREG ("pmbptr_el1", CPENC (3,0,9,10,1), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
> @@ -746,6 +756,8 @@
> SYSREG ("prlar_el2", CPENC (3,4,6,8,1), F_ARCHEXT, AARCH64_FEATURE (V8R))
> SYSREG ("prselr_el1", CPENC (3,0,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R))
> SYSREG ("prselr_el2", CPENC (3,4,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R))
> + SYSREG ("rcwmask_el1", CPENC (3,0,13,0,6), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (THE))
> + SYSREG ("rcwsmask_el1", CPENC (3,0,13,0,3), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (THE))
> SYSREG ("revidr_el1", CPENC (3,0,0,0,6), F_REG_READ, AARCH64_NO_FEATURES)
> SYSREG ("rgsr_el1", CPENC (3,0,1,0,5), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
> SYSREG ("rmr_el1", CPENC (3,0,12,0,2), 0, AARCH64_NO_FEATURES)
> @@ -1034,13 +1046,13 @@
> SYSREG ("trfcr_el1", CPENC (3,0,1,2,1), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
> SYSREG ("trfcr_el12", CPENC (3,5,1,2,1), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
> SYSREG ("trfcr_el2", CPENC (3,4,1,2,1), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
> - SYSREG ("ttbr0_el1", CPENC (3,0,2,0,0), 0, AARCH64_NO_FEATURES)
> - SYSREG ("ttbr0_el12", CPENC (3,5,2,0,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
> - SYSREG ("ttbr0_el2", CPENC (3,4,2,0,0), F_ARCHEXT, AARCH64_FEATURE (V8A))
> + SYSREG ("ttbr0_el1", CPENC (3,0,2,0,0), F_REG_128, AARCH64_NO_FEATURES)
> + SYSREG ("ttbr0_el12", CPENC (3,5,2,0,0), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8_1A))
> + SYSREG ("ttbr0_el2", CPENC (3,4,2,0,0), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8A))
> SYSREG ("ttbr0_el3", CPENC (3,6,2,0,0), 0, AARCH64_NO_FEATURES)
> - SYSREG ("ttbr1_el1", CPENC (3,0,2,0,1), 0, AARCH64_NO_FEATURES)
> - SYSREG ("ttbr1_el12", CPENC (3,5,2,0,1), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
> - SYSREG ("ttbr1_el2", CPENC (3,4,2,0,1), F_ARCHEXT, AARCH64_FEATURES (2, V8A, V8_1A))
> + SYSREG ("ttbr1_el1", CPENC (3,0,2,0,1), F_REG_128, AARCH64_NO_FEATURES)
> + SYSREG ("ttbr1_el12", CPENC (3,5,2,0,1), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8_1A))
> + SYSREG ("ttbr1_el2", CPENC (3,4,2,0,1), F_ARCHEXT|F_REG_128, AARCH64_FEATURES (2, V8A, V8_1A))
> SYSREG ("uao", CPENC (3,0,4,2,4), F_ARCHEXT, AARCH64_FEATURE (V8_2A))
> SYSREG ("vbar_el1", CPENC (3,0,12,0,0), 0, AARCH64_NO_FEATURES)
> SYSREG ("vbar_el12", CPENC (3,5,12,0,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
> @@ -1057,8 +1069,8 @@
> SYSREG ("vstcr_el2", CPENC (3,4,2,6,2), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
> SYSREG ("vsttbr_el2", CPENC (3,4,2,6,0), F_ARCHEXT, AARCH64_FEATURES (2, V8A, V8_4A))
> SYSREG ("vtcr_el2", CPENC (3,4,2,1,2), 0, AARCH64_NO_FEATURES)
> - SYSREG ("vttbr_el2", CPENC (3,4,2,1,0), F_ARCHEXT, AARCH64_FEATURE (V8A))
> + SYSREG ("vttbr_el2", CPENC (3,4,2,1,0), F_ARCHEXT|F_REG_128, AARCH64_FEATURE (V8A))
> SYSREG ("zcr_el1", CPENC (3,0,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
> SYSREG ("zcr_el12", CPENC (3,5,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
> SYSREG ("zcr_el2", CPENC (3,4,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
> - SYSREG ("zcr_el3", CPENC (3,6,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
> \ No newline at end of file
> + SYSREG ("zcr_el3", CPENC (3,6,1,2,0), F_ARCHEXT, AARCH64_FEATURE (SVE))
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions
2023-11-07 10:30 ` [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions Victor Do Nascimento
@ 2023-11-07 23:18 ` Richard Sandiford
0 siblings, 0 replies; 13+ messages in thread
From: Richard Sandiford @ 2023-11-07 23:18 UTC (permalink / raw)
To: Victor Do Nascimento; +Cc: gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Victor Do Nascimento <victor.donascimento@arm.com> writes:
> Given the introduction of optional 128-bit page table descriptor and
> translation hardening extension support with the Arm9.4-a
> architecture, this introduces the relevant flags to enable the reading
> and writing of 128-bit system registers.
>
> The `+d128' -march modifier enables the use of the following ACLE
> builtin functions:
>
> * __uint128_t __arm_rsr128(const char *special_register);
> * void __arm_wsr128(const char *special_register, __uint128_t value);
>
> and defines the __ARM_FEATURE_SYSREG128 macro to 1.
>
> Finally, the `rcwmask_el1' and `rcwsmask_el1' 128-bit system register
> implementations are also reliant on the enablement of the `+the' flag,
> which is thus also implemented in this patch.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-arches.def (armv8.9-a): New.
> (armv9.4-a): Likewise.
> * config/aarch64/aarch64-option-extensions.def (d128): Likewise.
> (the): Likewise.
> * config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise.
> (AARCH64_ISA_V8_9A): Likewise.
> (TARGET_ARMV9_4): Likewise.
> (AARCH64_ISA_D128): Likewise.
> (AARCH64_ISA_THE): Likewise.
> (TARGET_D128): Likewise.
> * doc/invoke.texi (AArch64 Options): Document new -march flags
> and extensions.
OK, thanks.
Richard
> ---
> gcc/config/aarch64/aarch64-arches.def | 2 ++
> gcc/config/aarch64/aarch64-c.cc | 1 +
> gcc/config/aarch64/aarch64-option-extensions.def | 4 ++++
> gcc/config/aarch64/aarch64.h | 15 +++++++++++++++
> gcc/doc/invoke.texi | 6 ++++++
> 5 files changed, 28 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def
> index 7ae92aa8e98..becccb801d0 100644
> --- a/gcc/config/aarch64/aarch64-arches.def
> +++ b/gcc/config/aarch64/aarch64-arches.def
> @@ -39,10 +39,12 @@ AARCH64_ARCH("armv8.5-a", generic, V8_5A, 8, (V8_4A, SB, SSBS, PR
> AARCH64_ARCH("armv8.6-a", generic, V8_6A, 8, (V8_5A, I8MM, BF16))
> AARCH64_ARCH("armv8.7-a", generic, V8_7A, 8, (V8_6A, LS64))
> AARCH64_ARCH("armv8.8-a", generic, V8_8A, 8, (V8_7A, MOPS))
> +AARCH64_ARCH("armv8.9-a", generic, V8_9A, 8, (V8_8A))
> AARCH64_ARCH("armv8-r", generic, V8R , 8, (V8_4A))
> AARCH64_ARCH("armv9-a", generic, V9A , 9, (V8_5A, SVE2))
> AARCH64_ARCH("armv9.1-a", generic, V9_1A, 9, (V8_6A, V9A))
> AARCH64_ARCH("armv9.2-a", generic, V9_2A, 9, (V8_7A, V9_1A))
> AARCH64_ARCH("armv9.3-a", generic, V9_3A, 9, (V8_8A, V9_2A))
> +AARCH64_ARCH("armv9.4-a", generic, V9_4A, 9, (V8_9A, V9_3A))
>
> #undef AARCH64_ARCH
> diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
> index be8b7236cf9..cacf8e8ed25 100644
> --- a/gcc/config/aarch64/aarch64-c.cc
> +++ b/gcc/config/aarch64/aarch64-c.cc
> @@ -206,6 +206,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
> aarch64_def_or_undef (TARGET_LS64,
> "__ARM_FEATURE_LS64", pfile);
> aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
> + aarch64_def_or_undef (TARGET_D128, "__ARM_FEATURE_SYSREG128", pfile);
>
> /* Not for ACLE, but required to keep "float.h" correct if we switch
> target between implementations that do or do not support ARMv8.2-A
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
> index 825f3bf7758..da31f7c32d1 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -151,4 +151,8 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "")
>
> AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")
>
> +AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
> +
> +AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
> +
> #undef AARCH64_OPT_EXTENSION
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index 84e6f79ca83..1b3c800ec89 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -219,13 +219,17 @@ enum class aarch64_feature : unsigned char {
> #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH)
> #define AARCH64_ISA_V8_7A (aarch64_isa_flags & AARCH64_FL_V8_7A)
> #define AARCH64_ISA_V8_8A (aarch64_isa_flags & AARCH64_FL_V8_8A)
> +#define AARCH64_ISA_V8_9A (aarch64_isa_flags & AARCH64_FL_V8_9A)
> #define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A)
> #define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A)
> #define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A)
> #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A)
> +#define AARCH64_ISA_V9_4A (aarch64_isa_flags & AARCH64_FL_V9_4A)
> #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS)
> #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64)
> #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
> +#define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128)
> +#define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE)
>
> /* AARCH64_FL options necessary for system register implementation. */
>
> @@ -388,6 +392,17 @@ enum class aarch64_feature : unsigned char {
> /* ARMv8.1-A Adv.SIMD support. */
> #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
>
> +/* Armv9.4-A features. */
> +#define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A)
> +
> +/* 128-bit System Registers and Instructions from Armv9.4-a are enabled
> + through +d128. */
> +#define TARGET_D128 (AARCH64_ISA_D128)
> +
> +/* Armv8.9-A/9.4-A Translation Hardening Extension system registers are
> + enabled through +the. */
> +#define TARGET_THE (AARCH64_ISA_THE)
> +
> /* Standard register usage. */
>
> /* 31 64-bit general purpose registers R0-R30:
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 6e776a0faa1..88327ce9681 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -20722,10 +20722,12 @@ and the features that they enable by default:
> @item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
> @item @samp{armv8.7-a} @tab Armv8.7-A @tab @samp{armv8.6-a}, @samp{+ls64}
> @item @samp{armv8.8-a} @tab Armv8.8-a @tab @samp{armv8.7-a}, @samp{+mops}
> +@item @samp{armv8.9-a} @tab Armv8.9-a @tab @samp{armv8.8-a}
> @item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve}, @samp{+sve2}
> @item @samp{armv9.1-a} @tab Armv9.1-A @tab @samp{armv9-a}, @samp{+bf16}, @samp{+i8mm}
> @item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+ls64}
> @item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
> +@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
> @item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r}
> @end multitable
>
> @@ -21028,6 +21030,10 @@ Enable the Flag Manipulation instructions Extension.
> Enable the Pointer Authentication Extension.
> @item cssc
> Enable the Common Short Sequence Compression instructions.
> +@item d128
> +Enable support for 128-bit system register read/write instructions.
> +@item the
> +Enable support for Armv8.9-a/9.4-a translation hardening extension.
>
> @end table
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/5] aarch64: Add support for GCS system registers with the +gcs modifier
2023-11-07 10:30 ` [PATCH 2/5] aarch64: Add support for GCS system registers with the +gcs modifier Victor Do Nascimento
@ 2023-11-07 23:19 ` Richard Sandiford
0 siblings, 0 replies; 13+ messages in thread
From: Richard Sandiford @ 2023-11-07 23:19 UTC (permalink / raw)
To: Victor Do Nascimento; +Cc: gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Victor Do Nascimento <victor.donascimento@arm.com> writes:
> Given the introduction of system registers associated with the Guarded
> Control Stack extension to Armv9.4-a in Binutils and their reliance on
> the `+gcs' modifier, we implement the necessary changes in GCC to
> allow for them to be recognized by the compiler.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-option-extensions.def (gcs): New.
> * config/aarch64/aarch64.h (AARCH64_ISA_GCS): New.
> (TARGET_THE): Likewise.
> * doc/invoke.texi (AArch64 Options): Describe GCS.
OK, thanks.
Richard
> ---
> gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
> gcc/config/aarch64/aarch64.h | 6 ++++++
> gcc/doc/invoke.texi | 2 ++
> 3 files changed, 10 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
> index da31f7c32d1..e72c039b612 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -155,4 +155,6 @@ AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
>
> AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
>
> +AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
> +
> #undef AARCH64_OPT_EXTENSION
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index 1b3c800ec89..69ef54553d7 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -230,6 +230,7 @@ enum class aarch64_feature : unsigned char {
> #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
> #define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128)
> #define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE)
> +#define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS)
>
> /* AARCH64_FL options necessary for system register implementation. */
>
> @@ -403,6 +404,11 @@ enum class aarch64_feature : unsigned char {
> enabled through +the. */
> #define TARGET_THE (AARCH64_ISA_THE)
>
> +/* Armv9.4-A Guarded Control Stack extension system registers are
> + enabled through +gcs. */
> +#define TARGET_GCS (AARCH64_ISA_GCS)
> +
> +
> /* Standard register usage. */
>
> /* 31 64-bit general purpose registers R0-R30:
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 88327ce9681..88ee1fdb524 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -21032,6 +21032,8 @@ Enable the Pointer Authentication Extension.
> Enable the Common Short Sequence Compression instructions.
> @item d128
> Enable support for 128-bit system register read/write instructions.
> +@item gcs
> +Enable support for Armv9.4-a Guarded Control Stack extension.
> @item the
> Enable support for Armv8.9-a/9.4-a translation hardening extension.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests
2023-11-07 22:51 ` Richard Sandiford
@ 2023-11-08 9:49 ` Christophe Lyon
2023-11-08 10:03 ` Richard Sandiford
0 siblings, 1 reply; 13+ messages in thread
From: Christophe Lyon @ 2023-11-08 9:49 UTC (permalink / raw)
To: Victor Do Nascimento, gcc-patches, kyrylo.tkachov,
Richard.Earnshaw, richard.sandiford
On 11/7/23 23:51, Richard Sandiford wrote:
> Victor Do Nascimento <victor.donascimento@arm.com> writes:
>> Extend existing unit tests for the ACLE system register manipulation
>> functions to include 128-bit tests.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New.
>> (set_wsr128): Likewise.
>> ---
>> gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 30 +++++++++++++++++++-
>> 1 file changed, 29 insertions(+), 1 deletion(-)
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
>> index 3af4b960306..e7725022316 100644
>> --- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
>> +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
>> @@ -1,11 +1,15 @@
>> /* Test the __arm_[r,w]sr ACLE intrinsics family. */
>> /* Check that function variants for different data types handle types correctly. */
>> /* { dg-do compile } */
>> -/* { dg-options "-O1 -march=armv8.4-a" } */
>> +/* { dg-options "-O1 -march=armv9.4-a+d128" } */
>> /* { dg-final { check-function-bodies "**" "" } } */
>
> I'm nervous about having our only tests for 64-bit reads and writes
> using such a high minimum version. Could the file instead be compiled
> without any minimum architecture and have tests that work with plain
> -march=armv8-a? Then the test could switch to other architectures
> where necessary using #pragam GCC target. This test...
>
>> #include <arm_acle.h>
>>
>> +#ifndef __ARM_FEATURE_SYSREG128
>> +#error "__ARM_FEATURE_SYSREG128 feature macro not defined."
>> +#endif
>> +
>
> ...would still work. with a #pragma GCC target.
>
Or maybe add a new test file for 128 bit sysregs, and thus have two test
files, the existing one for 64 bit sysregs, and the new one for 128 bit
sysregs?
Thanks,
Christophe
> Thanks,
> Richard
>
>> /*
>> ** get_rsr:
>> ** ...
>> @@ -66,6 +70,17 @@ get_rsrf64 ()
>> return __arm_rsrf64("trcseqstr");
>> }
>>
>> +/*
>> +** get_rsr128:
>> +** mrrs x0, x1, s3_0_c7_c4_0
>> +** ...
>> +*/
>> +__uint128_t
>> +get_rsr128 ()
>> +{
>> + __arm_rsr128("par_el1");
>> +}
>> +
>> /*
>> ** set_wsr32:
>> ** ...
>> @@ -129,6 +144,18 @@ set_wsrf64(double a)
>> __arm_wsrf64("trcseqstr", a);
>> }
>>
>> +/*
>> +** set_wsr128:
>> +** ...
>> +** msrr s3_0_c7_c4_0, x0, x1
>> +** ...
>> +*/
>> +void
>> +set_wsr128 (__uint128_t c)
>> +{
>> + __arm_wsr128 ("par_el1", c);
>> +}
>> +
>> /*
>> ** set_custom:
>> ** ...
>> @@ -142,3 +169,4 @@ void set_custom()
>> __uint64_t b = __arm_rsr64("S1_2_C3_C4_5");
>> __arm_wsr64("S1_2_C3_C4_5", b);
>> }
>> +
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests
2023-11-08 9:49 ` Christophe Lyon
@ 2023-11-08 10:03 ` Richard Sandiford
0 siblings, 0 replies; 13+ messages in thread
From: Richard Sandiford @ 2023-11-08 10:03 UTC (permalink / raw)
To: Christophe Lyon
Cc: Victor Do Nascimento, gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Christophe Lyon <christophe.lyon@arm.com> writes:
> On 11/7/23 23:51, Richard Sandiford wrote:
>> Victor Do Nascimento <victor.donascimento@arm.com> writes:
>>> Extend existing unit tests for the ACLE system register manipulation
>>> functions to include 128-bit tests.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New.
>>> (set_wsr128): Likewise.
>>> ---
>>> gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 30 +++++++++++++++++++-
>>> 1 file changed, 29 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
>>> index 3af4b960306..e7725022316 100644
>>> --- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
>>> +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
>>> @@ -1,11 +1,15 @@
>>> /* Test the __arm_[r,w]sr ACLE intrinsics family. */
>>> /* Check that function variants for different data types handle types correctly. */
>>> /* { dg-do compile } */
>>> -/* { dg-options "-O1 -march=armv8.4-a" } */
>>> +/* { dg-options "-O1 -march=armv9.4-a+d128" } */
>>> /* { dg-final { check-function-bodies "**" "" } } */
>>
>> I'm nervous about having our only tests for 64-bit reads and writes
>> using such a high minimum version. Could the file instead be compiled
>> without any minimum architecture and have tests that work with plain
>> -march=armv8-a? Then the test could switch to other architectures
>> where necessary using #pragam GCC target. This test...
>>
>>> #include <arm_acle.h>
>>>
>>> +#ifndef __ARM_FEATURE_SYSREG128
>>> +#error "__ARM_FEATURE_SYSREG128 feature macro not defined."
>>> +#endif
>>> +
>>
>> ...would still work. with a #pragma GCC target.
>>
>
> Or maybe add a new test file for 128 bit sysregs, and thus have two test
> files, the existing one for 64 bit sysregs, and the new one for 128 bit
> sysregs?
Yeah, that would be ok too, but what I was suggesting would lead to
at least three groups of tests rather than two.
Thanks,
Richard
>
> Thanks,
>
> Christophe
>
>
>
>> Thanks,
>> Richard
>>
>>> /*
>>> ** get_rsr:
>>> ** ...
>>> @@ -66,6 +70,17 @@ get_rsrf64 ()
>>> return __arm_rsrf64("trcseqstr");
>>> }
>>>
>>> +/*
>>> +** get_rsr128:
>>> +** mrrs x0, x1, s3_0_c7_c4_0
>>> +** ...
>>> +*/
>>> +__uint128_t
>>> +get_rsr128 ()
>>> +{
>>> + __arm_rsr128("par_el1");
>>> +}
>>> +
>>> /*
>>> ** set_wsr32:
>>> ** ...
>>> @@ -129,6 +144,18 @@ set_wsrf64(double a)
>>> __arm_wsrf64("trcseqstr", a);
>>> }
>>>
>>> +/*
>>> +** set_wsr128:
>>> +** ...
>>> +** msrr s3_0_c7_c4_0, x0, x1
>>> +** ...
>>> +*/
>>> +void
>>> +set_wsr128 (__uint128_t c)
>>> +{
>>> + __arm_wsr128 ("par_el1", c);
>>> +}
>>> +
>>> /*
>>> ** set_custom:
>>> ** ...
>>> @@ -142,3 +169,4 @@ void set_custom()
>>> __uint64_t b = __arm_rsr64("S1_2_C3_C4_5");
>>> __arm_wsr64("S1_2_C3_C4_5", b);
>>> }
>>> +
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-11-08 10:03 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-07 10:30 [PATCH 0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support Victor Do Nascimento
2023-11-07 10:30 ` [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions Victor Do Nascimento
2023-11-07 23:18 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 2/5] aarch64: Add support for GCS system registers with the +gcs modifier Victor Do Nascimento
2023-11-07 23:19 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 3/5] aarch64: Sync `aarch64-sys-regs.def' with Binutils Victor Do Nascimento
2023-11-07 23:17 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 4/5] aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins Victor Do Nascimento
2023-11-07 23:14 ` Richard Sandiford
2023-11-07 10:30 ` [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests Victor Do Nascimento
2023-11-07 22:51 ` Richard Sandiford
2023-11-08 9:49 ` Christophe Lyon
2023-11-08 10:03 ` Richard Sandiford
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