From: Richard Biener <rguenther@suse.de>
To: Hans-Peter Nilsson <hp@bitrange.com>
Cc: "Richard Sandiford" <richard.sandiford@arm.com>,
钟居哲 <juzhe.zhong@rivai.ai>, "kito.cheng" <kito.cheng@gmail.com>,
"Jeff Law" <jeffreyalaw@gmail.com>,
gcc-patches <gcc-patches@gcc.gnu.org>,
palmer <palmer@dabbelt.com>, jakub <jakub@redhat.com>
Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit
Date: Mon, 17 Apr 2023 06:38:22 +0000 (UTC) [thread overview]
Message-ID: <nycvar.YFH.7.77.849.2304170636010.4466@jbgna.fhfr.qr> (raw)
In-Reply-To: <alpine.BSF.2.20.16.2304142234060.23164@arjuna.pair.com>
On Fri, 14 Apr 2023, Hans-Peter Nilsson wrote:
> On Thu, 13 Apr 2023, Richard Biener via Gcc-patches wrote:
>
> > On Thu, 13 Apr 2023, Richard Sandiford wrote:
> >
> > > ??? <juzhe.zhong@rivai.ai> writes:
> > > > Yeah, like kito said.
> > > > Turns out the tuple type model in ARM SVE is the optimal solution for RVV.
> > > > And we like ARM SVE style implmentation.
> > > >
> > > > And now we see swapping rtx_code and mode in rtx_def can make rtx_def overal not exceed 64 bit.
> > > > But it seems that there is still problem in tree_type_common and tree_decl_common, is that right?
> > >
> > > I thought upthread we had a way forward for tree_type_common and
> > > tree_decl_common too, but maybe I only convinced myself. :)
> > >
> > > > After several trys (remove all redundant TI/TF vector modes and FP16 vector mode), now there are 252 modes
> > > > in RISC-V port. Basically, I can keep supporting new RVV intrinsisc features recently.
> > > > However, we can't support more in the future, for example, FP16 vector, BF16 vector, matrix modes, VLS modes,...etc.
> > >
> > > I agree it doesn't make sense to try to squeeze modes out like this.
> > > It's a bit artificial, and like you say, it's likely only putting
> > > off the inevitable.
> >
> > Agreed. Let's do the proposed TYPE_PRECISION change first and then
> > see how bad 16bit mode will be.
>
> (I don't see the following obvious having been pointed out, or
> why it doesn't apply, but if so, I hope you don't mind repeating
> it, so:)
>
> If after all, a change to the size of the code and mode
> bit-fields in rtx_def is necessary, like to still fit 64 bytes
> such become non-byte sizes *and* that matters for compilation
> time, can that change please be made target-dependent? Not as
> in set by a target macro, but rather deduced from the number of
> modes defined by the target?
>
> After all, that number is readily available (or if there's an
> order problem seems likely to easily be made available to the
> rtx_def build-time definition (as opposed to a gen-* -time
> definition).
But it gets us in the "wrong" direction with the goal of having
pluggable targets (aka a multi-target compiler)?
Anyway, I suggest we'll see how the space requirements work out.
We should definitely try hard to put the fields on a byte
boundary so accesses become at most a load + and.
Richard.
next prev parent reply other threads:[~2023-04-17 6:38 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-10 14:48 juzhe.zhong
2023-04-10 14:54 ` Jeff Law
2023-04-10 15:02 ` juzhe.zhong
2023-04-10 15:14 ` juzhe.zhong
2023-04-11 9:16 ` Jakub Jelinek
2023-04-11 9:46 ` juzhe.zhong
2023-04-11 10:11 ` Jakub Jelinek
2023-04-11 10:25 ` juzhe.zhong
2023-04-11 10:52 ` Jakub Jelinek
2023-04-11 9:46 ` Richard Sandiford
2023-04-11 9:59 ` Jakub Jelinek
2023-04-11 10:11 ` juzhe.zhong
2023-04-11 10:05 ` Richard Earnshaw
2023-04-11 10:15 ` Richard Sandiford
2023-04-11 10:59 ` Richard Biener
2023-04-11 11:11 ` Richard Sandiford
2023-04-11 11:19 ` juzhe.zhong
2023-04-11 13:50 ` Kito Cheng
2023-04-12 7:53 ` Richard Biener
2023-04-12 9:06 ` Kito Cheng
2023-04-12 9:21 ` Richard Biener
2023-04-12 9:31 ` Kito Cheng
2023-04-12 23:22 ` 钟居哲
2023-04-13 13:06 ` Richard Sandiford
2023-04-13 14:02 ` Richard Biener
2023-04-15 2:58 ` Hans-Peter Nilsson
2023-04-17 6:38 ` Richard Biener [this message]
2023-04-20 5:37 ` Hans-Peter Nilsson
2023-05-05 1:43 ` Li, Pan2
2023-05-05 6:25 ` Richard Biener
2023-05-06 1:10 ` Li, Pan2
2023-05-06 1:53 ` Kito Cheng
2023-05-06 1:59 ` juzhe.zhong
2023-05-06 2:12 ` Li, Pan2
2023-05-06 2:18 ` Kito Cheng
2023-05-06 2:20 ` Li, Pan2
2023-05-06 2:48 ` Li, Pan2
2023-05-07 1:55 ` Li, Pan2
2023-05-07 15:23 ` Jeff Law
2023-05-08 1:07 ` Li, Pan2
2023-05-08 6:29 ` Richard Biener
2023-05-08 6:41 ` Li, Pan2
2023-05-08 6:59 ` Li, Pan2
2023-05-08 7:37 ` Richard Biener
2023-05-08 8:05 ` Li, Pan2
2023-05-09 6:13 ` Li, Pan2
2023-05-09 7:04 ` Richard Biener
2023-05-09 10:16 ` Richard Sandiford
2023-05-09 10:26 ` Richard Biener
2023-05-09 11:50 ` Li, Pan2
2023-05-10 5:09 ` Li, Pan2
2023-05-10 7:22 ` Li, Pan2
2023-05-08 1:35 ` Li, Pan2
2023-04-10 15:18 ` Jakub Jelinek
2023-04-10 15:22 ` juzhe.zhong
2023-04-10 20:42 ` Jeff Law
2023-04-10 23:03 ` juzhe.zhong
2023-04-11 1:36 ` juzhe.zhong
[not found] ` <20230410232205400970205@rivai.ai>
2023-04-10 15:33 ` juzhe.zhong
2023-04-10 20:39 ` Jeff Law
2023-04-10 20:36 ` Jeff Law
2023-04-10 22:53 ` juzhe.zhong
2023-04-10 15:10 ` Jakub Jelinek
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