* [RFC] Support register groups in inline asm
@ 2016-11-15 17:37 Andrew Senkevich
2016-11-16 5:02 ` Andrew Pinski
0 siblings, 1 reply; 6+ messages in thread
From: Andrew Senkevich @ 2016-11-15 17:37 UTC (permalink / raw)
To: GCC Mailing List, Jeff Law, Kirill Yukhin
Hi,
new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use
of register groups.
To support register groups feature in inline asm needed some extension
with new constraints.
Current proposal is the following syntax:
__asm__ (“SMTH %[group], %[single]" :
[single] "+x"(v0) :
[group]
"Yg4"(v1), “1+1"(v2), “1+2"(v3), “1+3"(v4));
where "YgN" constraint specifies group of N consecutive registers
(which is started from register having number as "0 mod
2^ceil(log2(N))"),
and "1+K" specifies the next registers in the group.
Is this syntax ok? How to implement it?
Any comments or proposals will be appreciated, thanks.
--
WBR,
Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC] Support register groups in inline asm
2016-11-15 17:37 [RFC] Support register groups in inline asm Andrew Senkevich
@ 2016-11-16 5:02 ` Andrew Pinski
2016-12-05 15:32 ` Andrew Senkevich
0 siblings, 1 reply; 6+ messages in thread
From: Andrew Pinski @ 2016-11-16 5:02 UTC (permalink / raw)
To: Andrew Senkevich; +Cc: GCC Mailing List, Jeff Law, Kirill Yukhin
On Tue, Nov 15, 2016 at 9:36 AM, Andrew Senkevich
<andrew.n.senkevich@gmail.com> wrote:
> Hi,
>
> new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use
> of register groups.
>
> To support register groups feature in inline asm needed some extension
> with new constraints.
>
> Current proposal is the following syntax:
>
> __asm__ (“SMTH %[group], %[single]" :
> [single] "+x"(v0) :
> [group]
> "Yg4"(v1), “1+1"(v2), “1+2"(v3), “1+3"(v4));
>
> where "YgN" constraint specifies group of N consecutive registers
> (which is started from register having number as "0 mod
> 2^ceil(log2(N))"),
> and "1+K" specifies the next registers in the group.
>
> Is this syntax ok? How to implement it?
Have you looked into how AARCH64 back-end handles this via OI, etc.
Like:
/* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */
INT_MODE (OI, 32);
/* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
(2 d-regs = 1 q-reg = TImode). */
INT_MODE (CI, 48);
INT_MODE (XI, 64);
And then it implements TARGET_ARRAY_MODE_SUPPORTED_P. target hook?
And the x2 types are defined as a struct of an array like:
typedef struct int8x8x2_t
{
int8x8_t val[2];
} int8x8x2_t;
Thanks,
Andrew
>
> Any comments or proposals will be appreciated, thanks.
>
>
> --
> WBR,
> Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC] Support register groups in inline asm
2016-11-16 5:02 ` Andrew Pinski
@ 2016-12-05 15:32 ` Andrew Senkevich
2017-03-15 14:59 ` Andrew Senkevich
0 siblings, 1 reply; 6+ messages in thread
From: Andrew Senkevich @ 2016-12-05 15:32 UTC (permalink / raw)
To: Andrew Pinski, Uros Bizjak; +Cc: GCC Mailing List, Jeff Law, Kirill Yukhin
2016-11-16 8:02 GMT+03:00 Andrew Pinski <pinskia@gmail.com>:
> On Tue, Nov 15, 2016 at 9:36 AM, Andrew Senkevich
> <andrew.n.senkevich@gmail.com> wrote:
>> Hi,
>>
>> new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use
>> of register groups.
>>
>> To support register groups feature in inline asm needed some extension
>> with new constraints.
>>
>> Current proposal is the following syntax:
>>
>> __asm__ (“SMTH %[group], %[single]" :
>> [single] "+x"(v0) :
>> [group]
>> "Yg4"(v1), “1+1"(v2), “1+2"(v3), “1+3"(v4));
>>
>> where "YgN" constraint specifies group of N consecutive registers
>> (which is started from register having number as "0 mod
>> 2^ceil(log2(N))"),
>> and "1+K" specifies the next registers in the group.
>>
>> Is this syntax ok? How to implement it?
>
>
> Have you looked into how AARCH64 back-end handles this via OI, etc.
> Like:
> /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */
> INT_MODE (OI, 32);
>
> /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
> (2 d-regs = 1 q-reg = TImode). */
> INT_MODE (CI, 48);
> INT_MODE (XI, 64);
>
>
> And then it implements TARGET_ARRAY_MODE_SUPPORTED_P. target hook?
> And the x2 types are defined as a struct of an array like:
> typedef struct int8x8x2_t
> {
> int8x8_t val[2];
> } int8x8x2_t;
Thanks!
We have to update proposal with changing "+" symbol to "#" specifying
offset in a group (to avoid overloading the other meaning of “+”
specifying that operand is both input and output).
So current proposal of syntax is:
__asm__ (“INSTR %[group], %[single]" :
[single] "+x"(v0) :
[group]
"Yg4"(v1), “1#1"(v2), “1#2"(v3), “1#3"(v4));
where "YgN" constraint specifies group of N consecutive registers
(which is started from register having number as "0 mod 2^ceil(log2(N))"),
and "1#K" specifies the next registers in the group.
Some other questions or comments?
What about consensus on this syntax?
--
WBR,
Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC] Support register groups in inline asm
2016-12-05 15:32 ` Andrew Senkevich
@ 2017-03-15 14:59 ` Andrew Senkevich
2017-03-16 8:50 ` Richard Biener
0 siblings, 1 reply; 6+ messages in thread
From: Andrew Senkevich @ 2017-03-15 14:59 UTC (permalink / raw)
To: Richard Biener; +Cc: GCC Mailing List, Uros Bizjak, Jeff Law
2016-12-05 16:31 GMT+01:00 Andrew Senkevich <andrew.n.senkevich@gmail.com>:
> 2016-11-16 8:02 GMT+03:00 Andrew Pinski <pinskia@gmail.com>:
>> On Tue, Nov 15, 2016 at 9:36 AM, Andrew Senkevich
>> <andrew.n.senkevich@gmail.com> wrote:
>>> Hi,
>>>
>>> new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use
>>> of register groups.
>>>
>>> To support register groups feature in inline asm needed some extension
>>> with new constraints.
>>>
>>> Current proposal is the following syntax:
>>>
>>> __asm__ (“SMTH %[group], %[single]" :
>>> [single] "+x"(v0) :
>>> [group]
>>> "Yg4"(v1), “1+1"(v2), “1+2"(v3), “1+3"(v4));
>>>
>>> where "YgN" constraint specifies group of N consecutive registers
>>> (which is started from register having number as "0 mod
>>> 2^ceil(log2(N))"),
>>> and "1+K" specifies the next registers in the group.
>>>
>>> Is this syntax ok? How to implement it?
>>
>>
>> Have you looked into how AARCH64 back-end handles this via OI, etc.
>> Like:
>> /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */
>> INT_MODE (OI, 32);
>>
>> /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
>> (2 d-regs = 1 q-reg = TImode). */
>> INT_MODE (CI, 48);
>> INT_MODE (XI, 64);
>>
>>
>> And then it implements TARGET_ARRAY_MODE_SUPPORTED_P. target hook?
>> And the x2 types are defined as a struct of an array like:
>> typedef struct int8x8x2_t
>> {
>> int8x8_t val[2];
>> } int8x8x2_t;
>
> Thanks!
>
> We have to update proposal with changing "+" symbol to "#" specifying
> offset in a group (to avoid overloading the other meaning of “+”
> specifying that operand is both input and output).
>
> So current proposal of syntax is:
>
> __asm__ (“INSTR %[group], %[single]" :
> [single] "+x"(v0) :
> [group]
> "Yg4"(v1), “1#1"(v2), “1#2"(v3), “1#3"(v4));
>
> where "YgN" constraint specifies group of N consecutive registers
> (which is started from register having number as "0 mod 2^ceil(log2(N))"),
> and "1#K" specifies the next registers in the group.
>
> Some other questions or comments?
>
> What about consensus on this syntax?
Hi Richard!
Can we have agreement on this syntax, what do you think?
--
WBR,
Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC] Support register groups in inline asm
2017-03-15 14:59 ` Andrew Senkevich
@ 2017-03-16 8:50 ` Richard Biener
2017-03-16 9:29 ` Andrew Senkevich
0 siblings, 1 reply; 6+ messages in thread
From: Richard Biener @ 2017-03-16 8:50 UTC (permalink / raw)
To: Andrew Senkevich; +Cc: GCC Mailing List, Uros Bizjak, Jeff Law
[-- Attachment #1: Type: text/plain, Size: 2862 bytes --]
On Wed, 15 Mar 2017, Andrew Senkevich wrote:
> 2016-12-05 16:31 GMT+01:00 Andrew Senkevich <andrew.n.senkevich@gmail.com>:
> > 2016-11-16 8:02 GMT+03:00 Andrew Pinski <pinskia@gmail.com>:
> >> On Tue, Nov 15, 2016 at 9:36 AM, Andrew Senkevich
> >> <andrew.n.senkevich@gmail.com> wrote:
> >>> Hi,
> >>>
> >>> new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use
> >>> of register groups.
> >>>
> >>> To support register groups feature in inline asm needed some extension
> >>> with new constraints.
> >>>
> >>> Current proposal is the following syntax:
> >>>
> >>> __asm__ (“SMTH %[group], %[single]" :
> >>> [single] "+x"(v0) :
> >>> [group]
> >>> "Yg4"(v1), “1+1"(v2), “1+2"(v3), “1+3"(v4));
> >>>
> >>> where "YgN" constraint specifies group of N consecutive registers
> >>> (which is started from register having number as "0 mod
> >>> 2^ceil(log2(N))"),
> >>> and "1+K" specifies the next registers in the group.
> >>>
> >>> Is this syntax ok? How to implement it?
> >>
> >>
> >> Have you looked into how AARCH64 back-end handles this via OI, etc.
> >> Like:
> >> /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */
> >> INT_MODE (OI, 32);
> >>
> >> /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
> >> (2 d-regs = 1 q-reg = TImode). */
> >> INT_MODE (CI, 48);
> >> INT_MODE (XI, 64);
> >>
> >>
> >> And then it implements TARGET_ARRAY_MODE_SUPPORTED_P. target hook?
> >> And the x2 types are defined as a struct of an array like:
> >> typedef struct int8x8x2_t
> >> {
> >> int8x8_t val[2];
> >> } int8x8x2_t;
> >
> > Thanks!
> >
> > We have to update proposal with changing "+" symbol to "#" specifying
> > offset in a group (to avoid overloading the other meaning of “+â€
> > specifying that operand is both input and output).
> >
> > So current proposal of syntax is:
> >
> > __asm__ (“INSTR %[group], %[single]" :
> > [single] "+x"(v0) :
> > [group]
> > "Yg4"(v1), “1#1"(v2), “1#2"(v3), “1#3"(v4));
> >
> > where "YgN" constraint specifies group of N consecutive registers
> > (which is started from register having number as "0 mod 2^ceil(log2(N))"),
> > and "1#K" specifies the next registers in the group.
> >
> > Some other questions or comments?
> >
> > What about consensus on this syntax?
>
> Hi Richard!
>
> Can we have agreement on this syntax, what do you think?
I have no expertise / opinion here.
Richard.
>
> --
> WBR,
> Andrew
>
>
--
Richard Biener <rguenther@suse.de>
SUSE LINUX GmbH, GF: Felix Imendoerffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nuernberg)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC] Support register groups in inline asm
2017-03-16 8:50 ` Richard Biener
@ 2017-03-16 9:29 ` Andrew Senkevich
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Senkevich @ 2017-03-16 9:29 UTC (permalink / raw)
To: Richard Biener; +Cc: GCC Mailing List, Uros Bizjak, Jeff Law, Jakub Jelinek
2017-03-16 9:50 GMT+01:00 Richard Biener <rguenther@suse.de>:
> On Wed, 15 Mar 2017, Andrew Senkevich wrote:
>
>> 2016-12-05 16:31 GMT+01:00 Andrew Senkevich <andrew.n.senkevich@gmail.com>:
>> > 2016-11-16 8:02 GMT+03:00 Andrew Pinski <pinskia@gmail.com>:
>> >> On Tue, Nov 15, 2016 at 9:36 AM, Andrew Senkevich
>> >> <andrew.n.senkevich@gmail.com> wrote:
>> >>> Hi,
>> >>>
>> >>> new Intel instructions AVX512_4FMAPS and AVX512_4VNNIW introduce use
>> >>> of register groups.
>> >>>
>> >>> To support register groups feature in inline asm needed some extension
>> >>> with new constraints.
>> >>>
>> >>> Current proposal is the following syntax:
>> >>>
>> >>> __asm__ (“SMTH %[group], %[single]" :
>> >>> [single] "+x"(v0) :
>> >>> [group]
>> >>> "Yg4"(v1), “1+1"(v2), “1+2"(v3), “1+3"(v4));
>> >>>
>> >>> where "YgN" constraint specifies group of N consecutive registers
>> >>> (which is started from register having number as "0 mod
>> >>> 2^ceil(log2(N))"),
>> >>> and "1+K" specifies the next registers in the group.
>> >>>
>> >>> Is this syntax ok? How to implement it?
>> >>
>> >>
>> >> Have you looked into how AARCH64 back-end handles this via OI, etc.
>> >> Like:
>> >> /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */
>> >> INT_MODE (OI, 32);
>> >>
>> >> /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
>> >> (2 d-regs = 1 q-reg = TImode). */
>> >> INT_MODE (CI, 48);
>> >> INT_MODE (XI, 64);
>> >>
>> >>
>> >> And then it implements TARGET_ARRAY_MODE_SUPPORTED_P. target hook?
>> >> And the x2 types are defined as a struct of an array like:
>> >> typedef struct int8x8x2_t
>> >> {
>> >> int8x8_t val[2];
>> >> } int8x8x2_t;
>> >
>> > Thanks!
>> >
>> > We have to update proposal with changing "+" symbol to "#" specifying
>> > offset in a group (to avoid overloading the other meaning of “+”
>> > specifying that operand is both input and output).
>> >
>> > So current proposal of syntax is:
>> >
>> > __asm__ (“INSTR %[group], %[single]" :
>> > [single] "+x"(v0) :
>> > [group]
>> > "Yg4"(v1), “1#1"(v2), “1#2"(v3), “1#3"(v4));
>> >
>> > where "YgN" constraint specifies group of N consecutive registers
>> > (which is started from register having number as "0 mod 2^ceil(log2(N))"),
>> > and "1#K" specifies the next registers in the group.
>> >
>> > Some other questions or comments?
>> >
>> > What about consensus on this syntax?
>>
>> Hi Richard!
>>
>> Can we have agreement on this syntax, what do you think?
>
> I have no expertise / opinion here.
Hi Jeff, are you proper person to ask?
--
WBR,
Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-11-15 17:37 [RFC] Support register groups in inline asm Andrew Senkevich
2016-11-16 5:02 ` Andrew Pinski
2016-12-05 15:32 ` Andrew Senkevich
2017-03-15 14:59 ` Andrew Senkevich
2017-03-16 8:50 ` Richard Biener
2017-03-16 9:29 ` Andrew Senkevich
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