* [PATCH 01/17] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 02/17] [gdb/aarch64] refactor: Rename SVE-specific files Luis Machado
` (16 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
I noticed we don't handle register reads/writes in the best way for native
AArch64 Linux. Some registers are fetched/stored even if upper level code
told us to fetch a particular register number.
Fix this by being more strict about which registers we touch when
reading/writing them in the native AArch64 Linux layer.
There should be no user-visible changes due to this patch.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-nat.c | 60 ++++++++++++++++++++++-------------------
1 file changed, 33 insertions(+), 27 deletions(-)
diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
index ecb2eeb9540..62656a7347b 100644
--- a/gdb/aarch64-linux-nat.c
+++ b/gdb/aarch64-linux-nat.c
@@ -504,6 +504,7 @@ aarch64_fetch_registers (struct regcache *regcache, int regno)
aarch64_gdbarch_tdep *tdep
= gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
+ /* Do we need to fetch all registers? */
if (regno == -1)
{
fetch_gregs_from_thread (regcache);
@@ -521,28 +522,28 @@ aarch64_fetch_registers (struct regcache *regcache, int regno)
if (tdep->has_tls ())
fetch_tlsregs_from_thread (regcache);
}
+ /* General purpose register? */
else if (regno < AARCH64_V0_REGNUM)
fetch_gregs_from_thread (regcache);
- else if (tdep->has_sve ())
+ /* SVE register? */
+ else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM)
fetch_sveregs_from_thread (regcache);
- else
+ /* FPSIMD register? */
+ else if (regno < AARCH64_FPCR_REGNUM)
fetch_fpregs_from_thread (regcache);
-
- if (tdep->has_pauth ())
- {
- if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
- || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
- fetch_pauth_masks_from_thread (regcache);
- }
-
- /* Fetch individual MTE registers. */
- if (tdep->has_mte ()
- && (regno == tdep->mte_reg_base))
+ /* PAuth register? */
+ else if (tdep->has_pauth ()
+ && (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
+ || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)))
+ fetch_pauth_masks_from_thread (regcache);
+ /* MTE register? */
+ else if (tdep->has_mte ()
+ && (regno == tdep->mte_reg_base))
fetch_mteregs_from_thread (regcache);
-
- if (tdep->has_tls ()
- && regno >= tdep->tls_regnum_base
- && regno < tdep->tls_regnum_base + tdep->tls_register_count)
+ /* TLS register? */
+ else if (tdep->has_tls ()
+ && regno >= tdep->tls_regnum_base
+ && regno < tdep->tls_regnum_base + tdep->tls_register_count)
fetch_tlsregs_from_thread (regcache);
}
@@ -592,6 +593,7 @@ aarch64_store_registers (struct regcache *regcache, int regno)
aarch64_gdbarch_tdep *tdep
= gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
+ /* Do we need to store all registers? */
if (regno == -1)
{
store_gregs_to_thread (regcache);
@@ -606,22 +608,26 @@ aarch64_store_registers (struct regcache *regcache, int regno)
if (tdep->has_tls ())
store_tlsregs_to_thread (regcache);
}
+ /* General purpose register? */
else if (regno < AARCH64_V0_REGNUM)
store_gregs_to_thread (regcache);
- else if (tdep->has_sve ())
+ /* SVE register? */
+ else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM)
store_sveregs_to_thread (regcache);
- else
+ /* FPSIMD register? */
+ else if (regno < AARCH64_FPCR_REGNUM)
store_fpregs_to_thread (regcache);
-
- /* Store MTE registers. */
- if (tdep->has_mte ()
- && (regno == tdep->mte_reg_base))
+ /* MTE register? */
+ else if (tdep->has_mte ()
+ && (regno == tdep->mte_reg_base))
store_mteregs_to_thread (regcache);
-
- if (tdep->has_tls ()
- && regno >= tdep->tls_regnum_base
- && regno < tdep->tls_regnum_base + tdep->tls_register_count)
+ /* TLS register? */
+ else if (tdep->has_tls ()
+ && regno >= tdep->tls_regnum_base
+ && regno < tdep->tls_regnum_base + tdep->tls_register_count)
store_tlsregs_to_thread (regcache);
+
+ /* PAuth registers are read-only. */
}
/* A version of the "store_registers" target_ops method used when running
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 02/17] [gdb/aarch64] refactor: Rename SVE-specific files
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-04-11 4:26 ` [PATCH 01/17] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 03/17] [gdb/gdbserver] refactor: Simplify SVE interface to read/write registers Luis Machado
` (15 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
In preparation to the SME support patches, rename the SVE-specific files to
something a bit more meaningful that can be shared with the SME code.
In this case, I've renamed the "sve" in the names to "scalable".
No functional changes.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/Makefile.in | 2 +-
gdb/aarch64-linux-nat.c | 2 +-
gdb/configure.nat | 2 +-
...ptrace.c => aarch64-scalable-linux-ptrace.c} | 17 +++++++++--------
...ptrace.h => aarch64-scalable-linux-ptrace.h} | 11 ++++++-----
...xt.h => aarch64-scalable-linux-sigcontext.h} | 11 +++++++----
gdbserver/Makefile.in | 2 +-
gdbserver/configure.srv | 2 +-
gdbserver/linux-aarch64-low.cc | 2 +-
9 files changed, 28 insertions(+), 23 deletions(-)
rename gdb/nat/{aarch64-sve-linux-ptrace.c => aarch64-scalable-linux-ptrace.c} (96%)
rename gdb/nat/{aarch64-sve-linux-ptrace.h => aarch64-scalable-linux-ptrace.h} (90%)
rename gdb/nat/{aarch64-sve-linux-sigcontext.h => aarch64-scalable-linux-sigcontext.h} (96%)
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 40497541880..bd9d8d0df10 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -1558,7 +1558,7 @@ HFILES_NO_SRCDIR = \
nat/aarch64-linux.h \
nat/aarch64-linux-hw-point.h \
nat/aarch64-mte-linux-ptrace.h \
- nat/aarch64-sve-linux-ptrace.h \
+ nat/aarch64-scalable-linux-ptrace.h \
nat/amd64-linux-siginfo.h \
nat/gdb_ptrace.h \
nat/gdb_thread_db.h \
diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
index 62656a7347b..0dd9652d001 100644
--- a/gdb/aarch64-linux-nat.c
+++ b/gdb/aarch64-linux-nat.c
@@ -35,7 +35,7 @@
#include "arch/arm.h"
#include "nat/aarch64-linux.h"
#include "nat/aarch64-linux-hw-point.h"
-#include "nat/aarch64-sve-linux-ptrace.h"
+#include "nat/aarch64-scalable-linux-ptrace.h"
#include "elf/external.h"
#include "elf/common.h"
diff --git a/gdb/configure.nat b/gdb/configure.nat
index aabcdeff989..8d26f521792 100644
--- a/gdb/configure.nat
+++ b/gdb/configure.nat
@@ -238,7 +238,7 @@ case ${gdb_host} in
aarch32-linux-nat.o nat/aarch64-hw-point.o \
nat/aarch64-linux-hw-point.o \
nat/aarch64-linux.o \
- nat/aarch64-sve-linux-ptrace.o \
+ nat/aarch64-scalable-linux-ptrace.o \
nat/aarch64-mte-linux-ptrace.o"
;;
arc)
diff --git a/gdb/nat/aarch64-sve-linux-ptrace.c b/gdb/nat/aarch64-scalable-linux-ptrace.c
similarity index 96%
rename from gdb/nat/aarch64-sve-linux-ptrace.c
rename to gdb/nat/aarch64-scalable-linux-ptrace.c
index 51146535672..cc43f510892 100644
--- a/gdb/nat/aarch64-sve-linux-ptrace.c
+++ b/gdb/nat/aarch64-scalable-linux-ptrace.c
@@ -1,4 +1,5 @@
-/* Common target dependent for AArch64 systems.
+/* Common target dependent routines for AArch64 Scalable Extensions
+ (SVE/SME).
Copyright (C) 2018-2023 Free Software Foundation, Inc.
@@ -22,13 +23,13 @@
#include "gdbsupport/common-defs.h"
#include "elf/external.h"
#include "elf/common.h"
-#include "aarch64-sve-linux-ptrace.h"
+#include "aarch64-scalable-linux-ptrace.h"
#include "arch/aarch64.h"
#include "gdbsupport/common-regcache.h"
#include "gdbsupport/byte-vector.h"
#include <endian.h>
-/* See nat/aarch64-sve-linux-ptrace.h. */
+/* See nat/aarch64-scalable-linux-ptrace.h. */
uint64_t
aarch64_sve_get_vq (int tid)
@@ -60,7 +61,7 @@ aarch64_sve_get_vq (int tid)
return vq;
}
-/* See nat/aarch64-sve-linux-ptrace.h. */
+/* See nat/aarch64-scalable-linux-ptrace.h. */
bool
aarch64_sve_set_vq (int tid, uint64_t vq)
@@ -88,7 +89,7 @@ aarch64_sve_set_vq (int tid, uint64_t vq)
return true;
}
-/* See nat/aarch64-sve-linux-ptrace.h. */
+/* See nat/aarch64-scalable-linux-ptrace.h. */
bool
aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf)
@@ -117,7 +118,7 @@ aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf)
return aarch64_sve_set_vq (tid, sve_vq_from_vg (reg_vg));
}
-/* See nat/aarch64-sve-linux-ptrace.h. */
+/* See nat/aarch64-scalable-linux-ptrace.h. */
std::unique_ptr<gdb_byte[]>
aarch64_sve_get_sveregs (int tid)
@@ -161,7 +162,7 @@ aarch64_maybe_swab128 (gdb_byte *dst, const gdb_byte *src, size_t size)
#endif
}
-/* See nat/aarch64-sve-linux-ptrace.h. */
+/* See nat/aarch64-scalable-linux-ptrace.h. */
void
aarch64_sve_regs_copy_to_reg_buf (struct reg_buffer_common *reg_buf,
@@ -250,7 +251,7 @@ aarch64_sve_regs_copy_to_reg_buf (struct reg_buffer_common *reg_buf,
}
}
-/* See nat/aarch64-sve-linux-ptrace.h. */
+/* See nat/aarch64-scalable-linux-ptrace.h. */
void
aarch64_sve_regs_copy_from_reg_buf (const struct reg_buffer_common *reg_buf,
diff --git a/gdb/nat/aarch64-sve-linux-ptrace.h b/gdb/nat/aarch64-scalable-linux-ptrace.h
similarity index 90%
rename from gdb/nat/aarch64-sve-linux-ptrace.h
rename to gdb/nat/aarch64-scalable-linux-ptrace.h
index 9539e199d34..2847c4e0263 100644
--- a/gdb/nat/aarch64-sve-linux-ptrace.h
+++ b/gdb/nat/aarch64-scalable-linux-ptrace.h
@@ -1,4 +1,5 @@
-/* Common target dependent for AArch64 systems.
+/* Common target dependent definitions for AArch64 Scalable Extensions
+ (SVE/SME).
Copyright (C) 2018-2023 Free Software Foundation, Inc.
@@ -17,8 +18,8 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
-#ifndef NAT_AARCH64_SVE_LINUX_PTRACE_H
-#define NAT_AARCH64_SVE_LINUX_PTRACE_H
+#ifndef NAT_AARCH64_SCALABLE_LINUX_PTRACE_H
+#define NAT_AARCH64_SCALABLE_LINUX_PTRACE_H
#include <signal.h>
#include <sys/utsname.h>
@@ -32,7 +33,7 @@
#include <asm/ptrace.h>
#ifndef SVE_SIG_ZREGS_SIZE
-#include "aarch64-sve-linux-sigcontext.h"
+#include "aarch64-scalable-linux-sigcontext.h"
#endif
/* Indicates whether a SVE ptrace header is followed by SVE registers or a
@@ -69,4 +70,4 @@ extern void
aarch64_sve_regs_copy_from_reg_buf (const struct reg_buffer_common *reg_buf,
void *buf);
-#endif /* NAT_AARCH64_SVE_LINUX_PTRACE_H */
+#endif /* NAT_AARCH64_SCALABLE_LINUX_PTRACE_H */
diff --git a/gdb/nat/aarch64-sve-linux-sigcontext.h b/gdb/nat/aarch64-scalable-linux-sigcontext.h
similarity index 96%
rename from gdb/nat/aarch64-sve-linux-sigcontext.h
rename to gdb/nat/aarch64-scalable-linux-sigcontext.h
index aba3c1595d0..e0120e093a0 100644
--- a/gdb/nat/aarch64-sve-linux-sigcontext.h
+++ b/gdb/nat/aarch64-scalable-linux-sigcontext.h
@@ -1,4 +1,7 @@
-/* Copyright (C) 2018-2023 Free Software Foundation, Inc.
+/* Linux Kernel sigcontext definitions for AArch64 Scalable Extensions
+ (SVE/SME).
+
+ Copyright (C) 2018-2023 Free Software Foundation, Inc.
Contributed by Arm Ltd.
This file is part of GDB.
@@ -16,8 +19,8 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
-#ifndef NAT_AARCH64_SVE_LINUX_SIGCONTEXT_H
-#define NAT_AARCH64_SVE_LINUX_SIGCONTEXT_H
+#ifndef NAT_AARCH64_SCALABLE_LINUX_SIGCONTEXT_H
+#define NAT_AARCH64_SCALABLE_LINUX_SIGCONTEXT_H
#define SVE_MAGIC 0x53564501
@@ -264,4 +267,4 @@ struct user_sve_header {
SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \
: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
-#endif /* NAT_AARCH64_SVE_LINUX_SIGCONTEXT_H */
+#endif /* NAT_AARCH64_SCALABLE_LINUX_SIGCONTEXT_H */
diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in
index 39cb9e7a151..b597515d428 100644
--- a/gdbserver/Makefile.in
+++ b/gdbserver/Makefile.in
@@ -218,7 +218,7 @@ SFILES = \
$(srcdir)/../gdb/arch/ppc-linux-common.c \
$(srcdir)/../gdb/arch/riscv.c \
$(srcdir)/../gdb/nat/aarch64-mte-linux-ptrace.c \
- $(srcdir)/../gdb/nat/aarch64-sve-linux-ptrace.c \
+ $(srcdir)/../gdb/nat/aarch64-scalable-linux-ptrace.c \
$(srcdir)/../gdb/nat/linux-btrace.c \
$(srcdir)/../gdb/nat/linux-namespaces.c \
$(srcdir)/../gdb/nat/linux-osdata.c \
diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
index f0101994529..f625c808859 100644
--- a/gdbserver/configure.srv
+++ b/gdbserver/configure.srv
@@ -51,7 +51,7 @@ case "${gdbserver_host}" in
srv_tgtobj="$srv_tgtobj arch/aarch64-mte-linux.o"
srv_tgtobj="$srv_tgtobj linux-aarch64-tdesc.o"
srv_tgtobj="$srv_tgtobj nat/aarch64-mte-linux-ptrace.o"
- srv_tgtobj="$srv_tgtobj nat/aarch64-sve-linux-ptrace.o"
+ srv_tgtobj="$srv_tgtobj nat/aarch64-scalable-linux-ptrace.o"
srv_tgtobj="${srv_tgtobj} $srv_linux_obj"
srv_linux_regsets=yes
srv_linux_thread_db=yes
diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc
index 2ed6e95562c..a20a3485ebc 100644
--- a/gdbserver/linux-aarch64-low.cc
+++ b/gdbserver/linux-aarch64-low.cc
@@ -44,7 +44,7 @@
#include "linux-aarch32-tdesc.h"
#include "linux-aarch64-tdesc.h"
#include "nat/aarch64-mte-linux-ptrace.h"
-#include "nat/aarch64-sve-linux-ptrace.h"
+#include "nat/aarch64-scalable-linux-ptrace.h"
#include "tdesc.h"
#ifdef HAVE_SYS_REG_H
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 03/17] [gdb/gdbserver] refactor: Simplify SVE interface to read/write registers
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-04-11 4:26 ` [PATCH 01/17] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux Luis Machado
2023-04-11 4:26 ` [PATCH 02/17] [gdb/aarch64] refactor: Rename SVE-specific files Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 04/17] [gdb/aarch64] sve: Fix return command when using V registers in a SVE-enabled target Luis Machado
` (14 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
This is a patch in preparation to upcoming patches enabling SME support. It
attempts to simplify the gdb/gdbserver shared interface used to read/write
SVE registers.
Where the current code makes use of unique_ptr, allocating a new buffer by
hand and passing a buffer around, this patch makes that code use
gdb::byte_vector and passes a reference to this byte vector to the functions,
allowing the functions to have ready access to the size of the buffer.
It also shares a bit more code between gdb and gdbserver, in particular around
handling of ptrace get/set requests for SVE.
I think gdbserver could be refactored to handle register reads/writes more
like gdb's native layer as opposed to letting the generic linux-low layer do
the ptrace calls. This is not very flexible and assumes one size for the
responses. If you have something like NT_ARM_SVE, where you can have either
FPSIMD or SVE contents, it doesn't work that well.
I didn't want to change that interface right now as it is a bit too much work
and touches all the targets, some of which I can't easily test.
Hence the reason why the buffer the generic linux-now passes down to
linux-aarch64-low is unused or ignored.
No user-visible changes should happen as part of this refactor other than a
slightly reworded warning message.
While doing the refactor, I also noticed what seems to be a mistake in checking
if the register cache contains active (non-zero) SVE data.
For instance, the original code did something like this in
aarch64_sve_regs_copy_from_reg_buf:
has_sve_state |= reg_buf->raw_compare (AARCH64_SVE_Z0_REGNUM + i
reg, sizeof (__int128_t));
"reg" is a zeroed-out buffer that we compare the Z register contents
past the first 128 bits. The problem here is that raw_compare returns
1 if the contents compare the same, which means has_sve_state will be
true. But if we compared the Z register contents to 0, it means we
*do not* have SVE state, and therefore has_sve_state should be false.
The consequence of this mistake is that we convert the initial
FPSIMD-formatted data we get from ptrace for the NT_ARM_SVE register
set to a SVE-formatted one.
In the end, this doesn't cause user-visible differences because the
values of both the Z and V registers will still be the same. But the
logic is not correct.
I used the opportunity to fix this, and it gets tested later on by
the additional SME tests.
I do plan on submitting some SVE-specific tests to make sure we have
a bit more coverage in GDB's testsuite.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-nat.c | 30 +---
gdb/nat/aarch64-scalable-linux-ptrace.c | 203 +++++++++++++++---------
gdb/nat/aarch64-scalable-linux-ptrace.h | 28 ++--
gdbserver/linux-aarch64-low.cc | 24 ++-
4 files changed, 175 insertions(+), 110 deletions(-)
diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
index 0dd9652d001..a775631e9ec 100644
--- a/gdb/aarch64-linux-nat.c
+++ b/gdb/aarch64-linux-nat.c
@@ -319,9 +319,8 @@ store_fpregs_to_thread (const struct regcache *regcache)
static void
fetch_sveregs_from_thread (struct regcache *regcache)
{
- std::unique_ptr<gdb_byte[]> base
- = aarch64_sve_get_sveregs (regcache->ptid ().lwp ());
- aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ());
+ /* Fetch SVE state from the thread and copy it into the register cache. */
+ aarch64_sve_regs_copy_to_reg_buf (regcache->ptid ().lwp (), regcache);
}
/* Store to the current thread the valid sve register
@@ -330,28 +329,9 @@ fetch_sveregs_from_thread (struct regcache *regcache)
static void
store_sveregs_to_thread (struct regcache *regcache)
{
- int ret;
- struct iovec iovec;
- int tid = regcache->ptid ().lwp ();
-
- /* First store vector length to the thread. This is done first to ensure the
- ptrace buffers read from the kernel are the correct size. */
- if (!aarch64_sve_set_vq (tid, regcache))
- perror_with_name (_("Unable to set VG register"));
-
- /* Obtain a dump of SVE registers from ptrace. */
- std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid);
-
- /* Overwrite with regcache state. */
- aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ());
-
- /* Write back to the kernel. */
- iovec.iov_base = base.get ();
- iovec.iov_len = ((struct user_sve_header *) base.get ())->size;
- ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec);
-
- if (ret < 0)
- perror_with_name (_("Unable to store sve registers"));
+ /* Fetch SVE state from the register cache and update the thread TID with
+ it. */
+ aarch64_sve_regs_copy_from_reg_buf (regcache->ptid ().lwp (), regcache);
}
/* Fill GDB's register array with the pointer authentication mask values from
diff --git a/gdb/nat/aarch64-scalable-linux-ptrace.c b/gdb/nat/aarch64-scalable-linux-ptrace.c
index cc43f510892..192eebcda19 100644
--- a/gdb/nat/aarch64-scalable-linux-ptrace.c
+++ b/gdb/nat/aarch64-scalable-linux-ptrace.c
@@ -120,28 +120,44 @@ aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf)
/* See nat/aarch64-scalable-linux-ptrace.h. */
-std::unique_ptr<gdb_byte[]>
-aarch64_sve_get_sveregs (int tid)
+gdb::byte_vector
+aarch64_fetch_sve_regset (int tid)
{
- struct iovec iovec;
uint64_t vq = aarch64_sve_get_vq (tid);
if (vq == 0)
- perror_with_name (_("Unable to fetch SVE register header"));
+ perror_with_name (_("Unable to fetch SVE vector length"));
/* A ptrace call with NT_ARM_SVE will return a header followed by either a
dump of all the SVE and FP registers, or an fpsimd structure (identical to
the one returned by NT_FPREGSET) if the kernel has not yet executed any
SVE code. Make sure we allocate enough space for a full SVE dump. */
- iovec.iov_len = SVE_PT_SIZE (vq, SVE_PT_REGS_SVE);
- std::unique_ptr<gdb_byte[]> buf (new gdb_byte[iovec.iov_len]);
- iovec.iov_base = buf.get ();
+ gdb::byte_vector sve_state (SVE_PT_SIZE (vq, SVE_PT_REGS_SVE), 0);
+
+ struct iovec iovec;
+ iovec.iov_base = sve_state.data ();
+ iovec.iov_len = sve_state.size ();
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
perror_with_name (_("Unable to fetch SVE registers"));
- return buf;
+ return sve_state;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+aarch64_store_sve_regset (int tid, const gdb::byte_vector &sve_state)
+{
+ struct iovec iovec;
+ iovec.iov_base = (void *) sve_state.data ();
+ iovec.iov_len = sve_state.size ();
+
+ if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
+ perror_with_name (_("Unable to store SVE registers"));
+
+ return true;
}
/* If we are running in BE mode, byteswap the contents
@@ -165,11 +181,13 @@ aarch64_maybe_swab128 (gdb_byte *dst, const gdb_byte *src, size_t size)
/* See nat/aarch64-scalable-linux-ptrace.h. */
void
-aarch64_sve_regs_copy_to_reg_buf (struct reg_buffer_common *reg_buf,
- const void *buf)
+aarch64_sve_regs_copy_to_reg_buf (int tid, struct reg_buffer_common *reg_buf)
{
- char *base = (char *) buf;
- struct user_sve_header *header = (struct user_sve_header *) buf;
+ gdb::byte_vector sve_state = aarch64_fetch_sve_regset (tid);
+
+ char *base = (char *) sve_state.data ();
+ struct user_sve_header *header
+ = (struct user_sve_header *) sve_state.data ();
uint64_t vq = sve_vq_from_vl (header->vl);
uint64_t vg = sve_vg_from_vl (header->vl);
@@ -249,18 +267,33 @@ aarch64_sve_regs_copy_to_reg_buf (struct reg_buffer_common *reg_buf,
reg_buf->raw_supply (AARCH64_SVE_FFR_REGNUM, reg);
}
+
+ /* At this point we have updated the register cache with the contents of
+ the NT_ARM_SVE register set. */
}
/* See nat/aarch64-scalable-linux-ptrace.h. */
void
-aarch64_sve_regs_copy_from_reg_buf (const struct reg_buffer_common *reg_buf,
- void *buf)
+aarch64_sve_regs_copy_from_reg_buf (int tid,
+ struct reg_buffer_common *reg_buf)
{
- struct user_sve_header *header = (struct user_sve_header *) buf;
- char *base = (char *) buf;
+ /* First store the vector length to the thread. This is done first to
+ ensure the ptrace buffers read from the kernel are the correct size. */
+ if (!aarch64_sve_set_vq (tid, reg_buf))
+ perror_with_name (_("Unable to set VG register"));
+
+ /* Obtain a dump of SVE registers from ptrace. */
+ gdb::byte_vector sve_state = aarch64_fetch_sve_regset (tid);
+
+ struct user_sve_header *header = (struct user_sve_header *) sve_state.data ();
uint64_t vq = sve_vq_from_vl (header->vl);
+ gdb::byte_vector new_state (SVE_PT_SIZE (32, SVE_PT_REGS_SVE), 0);
+ memcpy (new_state.data (), sve_state.data (), sve_state.size ());
+ header = (struct user_sve_header *) new_state.data ();
+ char *base = (char *) new_state.data ();
+
/* Sanity check the data in the header. */
if (!sve_vl_valid (header->vl)
|| SVE_PT_SIZE (vq, header->flags) != header->size)
@@ -275,36 +308,40 @@ aarch64_sve_regs_copy_from_reg_buf (const struct reg_buffer_common *reg_buf,
resulting in the initialization of SVE state written back to the
kernel, which is why we try to avoid it. */
- bool has_sve_state = false;
- gdb_byte *reg = (gdb_byte *) alloca (SVE_PT_SVE_ZREG_SIZE (vq));
- struct user_fpsimd_state *fpsimd
- = (struct user_fpsimd_state *)(base + SVE_PT_FPSIMD_OFFSET);
-
- memset (reg, 0, SVE_PT_SVE_ZREG_SIZE (vq));
+ /* Buffer (using the maximum size a Z register) used to look for zeroed
+ out sve state. */
+ gdb_byte reg[256];
+ memset (reg, 0, sizeof (reg));
/* Check in the reg_buf if any of the Z registers are set after the
first 128 bits, or if any of the other SVE registers are set. */
-
+ bool has_sve_state = false;
for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
{
- has_sve_state |= reg_buf->raw_compare (AARCH64_SVE_Z0_REGNUM + i,
- reg, sizeof (__int128_t));
- if (has_sve_state)
- break;
+ if (!reg_buf->raw_compare (AARCH64_SVE_Z0_REGNUM + i, reg,
+ V_REGISTER_SIZE))
+ {
+ has_sve_state = true;
+ break;
+ }
}
if (!has_sve_state)
for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
{
- has_sve_state |= reg_buf->raw_compare (AARCH64_SVE_P0_REGNUM + i,
- reg, 0);
- if (has_sve_state)
- break;
+ if (!reg_buf->raw_compare (AARCH64_SVE_P0_REGNUM + i, reg, 0))
+ {
+ has_sve_state = true;
+ break;
+ }
}
if (!has_sve_state)
- has_sve_state |= reg_buf->raw_compare (AARCH64_SVE_FFR_REGNUM,
- reg, 0);
+ has_sve_state
+ = !reg_buf->raw_compare (AARCH64_SVE_FFR_REGNUM, reg, 0);
+
+ struct user_fpsimd_state *fpsimd
+ = (struct user_fpsimd_state *)(base + SVE_PT_FPSIMD_OFFSET);
/* If no SVE state exists, then use the existing fpsimd structure to
write out state and return. */
@@ -344,50 +381,74 @@ aarch64_sve_regs_copy_from_reg_buf (const struct reg_buffer_common *reg_buf,
if (REG_VALID == reg_buf->get_register_status (AARCH64_FPCR_REGNUM))
reg_buf->raw_collect (AARCH64_FPCR_REGNUM, &fpsimd->fpcr);
- return;
- }
-
- /* Otherwise, reformat the fpsimd structure into a full SVE set, by
- expanding the V registers (working backwards so we don't splat
- registers before they are copied) and using null for everything else.
- Note that enough space for a full SVE dump was originally allocated
- for base. */
+ /* At this point we have collected all the data from the register
+ cache and we are ready to update the FPSIMD register content
+ of the thread. */
- header->flags |= SVE_PT_REGS_SVE;
- header->size = SVE_PT_SIZE (vq, SVE_PT_REGS_SVE);
+ /* Fall through so we can update the thread's contents with the
+ FPSIMD register cache values. */
+ }
+ else
+ {
+ /* Otherwise, reformat the fpsimd structure into a full SVE set, by
+ expanding the V registers (working backwards so we don't splat
+ registers before they are copied) and using zero for everything
+ else.
+ Note that enough space for a full SVE dump was originally allocated
+ for base. */
+
+ header->flags |= SVE_PT_REGS_SVE;
+ header->size = SVE_PT_SIZE (vq, SVE_PT_REGS_SVE);
+
+ memcpy (base + SVE_PT_SVE_FPSR_OFFSET (vq), &fpsimd->fpsr,
+ sizeof (uint32_t));
+ memcpy (base + SVE_PT_SVE_FPCR_OFFSET (vq), &fpsimd->fpcr,
+ sizeof (uint32_t));
+
+ for (int i = AARCH64_SVE_Z_REGS_NUM; i >= 0 ; i--)
+ {
+ memcpy (base + SVE_PT_SVE_ZREG_OFFSET (vq, i), &fpsimd->vregs[i],
+ sizeof (__int128_t));
+ }
- memcpy (base + SVE_PT_SVE_FPSR_OFFSET (vq), &fpsimd->fpsr,
- sizeof (uint32_t));
- memcpy (base + SVE_PT_SVE_FPCR_OFFSET (vq), &fpsimd->fpcr,
- sizeof (uint32_t));
+ /* At this point we have converted the FPSIMD layout to an SVE
+ layout and copied the register data.
- for (int i = AARCH64_SVE_Z_REGS_NUM; i >= 0 ; i--)
- {
- memcpy (base + SVE_PT_SVE_ZREG_OFFSET (vq, i), &fpsimd->vregs[i],
- sizeof (__int128_t));
+ Fall through so we can update the thread's contents with the SVE
+ register cache values. */
}
}
+ else
+ {
+ /* We already have SVE state for this thread, so we just need to update
+ the values of the registers. */
+ for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
+ if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_Z0_REGNUM
+ + i))
+ reg_buf->raw_collect (AARCH64_SVE_Z0_REGNUM + i,
+ base + SVE_PT_SVE_ZREG_OFFSET (vq, i));
- /* Replace the kernel values with those from reg_buf. */
-
- for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
- if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_Z0_REGNUM + i))
- reg_buf->raw_collect (AARCH64_SVE_Z0_REGNUM + i,
- base + SVE_PT_SVE_ZREG_OFFSET (vq, i));
-
- for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
- if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_P0_REGNUM + i))
- reg_buf->raw_collect (AARCH64_SVE_P0_REGNUM + i,
- base + SVE_PT_SVE_PREG_OFFSET (vq, i));
+ for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
+ if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_P0_REGNUM
+ + i))
+ reg_buf->raw_collect (AARCH64_SVE_P0_REGNUM + i,
+ base + SVE_PT_SVE_PREG_OFFSET (vq, i));
+
+ if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_FFR_REGNUM))
+ reg_buf->raw_collect (AARCH64_SVE_FFR_REGNUM,
+ base + SVE_PT_SVE_FFR_OFFSET (vq));
+ if (REG_VALID == reg_buf->get_register_status (AARCH64_FPSR_REGNUM))
+ reg_buf->raw_collect (AARCH64_FPSR_REGNUM,
+ base + SVE_PT_SVE_FPSR_OFFSET (vq));
+ if (REG_VALID == reg_buf->get_register_status (AARCH64_FPCR_REGNUM))
+ reg_buf->raw_collect (AARCH64_FPCR_REGNUM,
+ base + SVE_PT_SVE_FPCR_OFFSET (vq));
+ }
- if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_FFR_REGNUM))
- reg_buf->raw_collect (AARCH64_SVE_FFR_REGNUM,
- base + SVE_PT_SVE_FFR_OFFSET (vq));
- if (REG_VALID == reg_buf->get_register_status (AARCH64_FPSR_REGNUM))
- reg_buf->raw_collect (AARCH64_FPSR_REGNUM,
- base + SVE_PT_SVE_FPSR_OFFSET (vq));
- if (REG_VALID == reg_buf->get_register_status (AARCH64_FPCR_REGNUM))
- reg_buf->raw_collect (AARCH64_FPCR_REGNUM,
- base + SVE_PT_SVE_FPCR_OFFSET (vq));
+ /* At this point we have collected all the data from the register cache and
+ we are ready to update the SVE/FPSIMD register contents of the thread.
+ sve_state should contain all the data in the correct format, ready to be
+ passed on to ptrace. */
+ aarch64_store_sve_regset (tid, new_state);
}
diff --git a/gdb/nat/aarch64-scalable-linux-ptrace.h b/gdb/nat/aarch64-scalable-linux-ptrace.h
index 2847c4e0263..3215103c88a 100644
--- a/gdb/nat/aarch64-scalable-linux-ptrace.h
+++ b/gdb/nat/aarch64-scalable-linux-ptrace.h
@@ -52,22 +52,28 @@ uint64_t aarch64_sve_get_vq (int tid);
bool aarch64_sve_set_vq (int tid, uint64_t vq);
bool aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf);
-/* Read the current SVE register set using ptrace, allocating space as
- required. */
+/* Read the current SVE register set from thread TID and return its data
+ through a byte vector. */
-extern std::unique_ptr<gdb_byte[]> aarch64_sve_get_sveregs (int tid);
+extern gdb::byte_vector aarch64_fetch_sve_regset (int tid);
-/* Put the registers from linux structure buf into register buffer. Assumes the
- vector lengths in the register buffer match the size in the kernel. */
+/* Write the SVE contents from SVE_STATE to thread TID. Return true if
+ successful and false otherwise. */
-extern void aarch64_sve_regs_copy_to_reg_buf (struct reg_buffer_common *reg_buf,
- const void *buf);
+extern bool
+aarch64_store_sve_regset (int tid, const gdb::byte_vector &sve_state);
-/* Put the registers from register buffer into linux structure buf. Assumes the
- vector lengths in the register buffer match the size in the kernel. */
+/* Given a thread id TID and a register buffer REG_BUF, update the register
+ buffer with the SVE state from thread TID. */
extern void
-aarch64_sve_regs_copy_from_reg_buf (const struct reg_buffer_common *reg_buf,
- void *buf);
+aarch64_sve_regs_copy_to_reg_buf (int tid, struct reg_buffer_common *reg_buf);
+
+/* Given a thread id TID and a register buffer REG_BUF containing SVE
+ register data, write the SVE data to thread TID. */
+
+extern void
+aarch64_sve_regs_copy_from_reg_buf (int tid,
+ struct reg_buffer_common *reg_buf);
#endif /* NAT_AARCH64_SCALABLE_LINUX_PTRACE_H */
diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc
index a20a3485ebc..af2e0fd9c10 100644
--- a/gdbserver/linux-aarch64-low.cc
+++ b/gdbserver/linux-aarch64-low.cc
@@ -719,9 +719,18 @@ aarch64_target::low_new_fork (process_info *parent,
/* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
static void
-aarch64_sve_regs_copy_to_regcache (struct regcache *regcache, const void *buf)
+aarch64_sve_regs_copy_to_regcache (struct regcache *regcache,
+ ATTRIBUTE_UNUSED const void *buf)
{
- return aarch64_sve_regs_copy_to_reg_buf (regcache, buf);
+ /* BUF is unused here since we collect the data straight from a ptrace
+ request in aarch64_sve_regs_copy_to_reg_buf, therefore bypassing
+ gdbserver's own call to ptrace. */
+
+ int tid = lwpid_of (current_thread);
+
+ /* Update the register cache. aarch64_sve_regs_copy_to_reg_buf handles
+ fetching the NT_ARM_SVE state from thread TID. */
+ aarch64_sve_regs_copy_to_reg_buf (tid, regcache);
}
/* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */
@@ -729,7 +738,16 @@ aarch64_sve_regs_copy_to_regcache (struct regcache *regcache, const void *buf)
static void
aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf)
{
- return aarch64_sve_regs_copy_from_reg_buf (regcache, buf);
+ int tid = lwpid_of (current_thread);
+
+ /* Update the thread SVE state. aarch64_sve_regs_copy_from_reg_buf
+ handles writing the SVE/FPSIMD state back to thread TID. */
+ aarch64_sve_regs_copy_from_reg_buf (tid, regcache);
+
+ /* We need to return the expected data in BUF, so copy whatever the kernel
+ already has to BUF. */
+ gdb::byte_vector sve_state = aarch64_fetch_sve_regset (tid);
+ memcpy (buf, sve_state.data (), sve_state.size ());
}
/* Array containing all the possible register sets for AArch64/Linux. During
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 04/17] [gdb/aarch64] sve: Fix return command when using V registers in a SVE-enabled target
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (2 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 03/17] [gdb/gdbserver] refactor: Simplify SVE interface to read/write registers Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 05/17] [gdb/aarch64] sme: Enable SME registers and pseudo-registers Luis Machado
` (13 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
In a target without SVE support, the V registers have a size of 16 bytes,
otherwise they may have a size bigger than 16 bytes (depending on the current
vector length for the Z registers, as they overlap the V registers).
In aarch64-tdep.c:aarch64_store_return_value, the code is laid
out in a way that allocates the buffer with the size of the register, but
only updates the amount of bytes for the particular type we're returning.
This may cause a situation where we have a register size of 32 bytes but
are returning a floating point value of 8 bytes. The temporary buffer
will therefore have 32 bytes, but we'll only update 8 bytes of it.
When we write the entire register back, it will have potentially 24 bytes
of garbage in it.
Fix this by first reading the original contents of the register and then
overriding only the bytes that we need for the return value.
Tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-tdep.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index d8349e4ccdb..ea0d8ce2e27 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2411,6 +2411,11 @@ aarch64_store_return_value (struct type *type, struct regcache *regs,
("write HFA or HVA return value element %d to %s",
i + 1, gdbarch_register_name (gdbarch, regno));
+ /* Depending on whether the target supports SVE or not, the V
+ registers may report a size > 16 bytes. In that case, read the
+ original contents of the register before overriding it with a new
+ value that has a potential size <= 16 bytes. */
+ regs->cooked_read (regno, tmpbuf);
memcpy (tmpbuf, valbuf,
len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
regs->cooked_write (regno, tmpbuf);
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 05/17] [gdb/aarch64] sme: Enable SME registers and pseudo-registers
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (3 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 04/17] [gdb/aarch64] sve: Fix return command when using V registers in a SVE-enabled target Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 06/17] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically Luis Machado
` (12 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
The SME (Scalable Matrix Extension) [1] exposes a new matrix register ZA with
variable sizes. It also exposes a new mode called streaming mode.
Similarly to SVE, the ZA register size is dictated by a vector length, but the
SME vector length is called streaming vetor length. The total size for
ZA in a given moment is svl x svl.
In streaming mode, the SVE registers have their sizes based on svl rather than
the regular vector length (vl).
The feature detection is controlled by the HWCAP2_SME bit, but actual support
should be validated by attempting a ptrace call for one of the new register
sets: NT_ARM_ZA and NT_ARM_SSVE.
Due to its large size, the ZA register is exposed as a vector of bytes, but we
introduce a number of pseudo-registers that gives various different views
into the ZA contents. These can be arranged in a couple categories: tiles and
tile slices.
Tiles are matrices the same size or smaller than ZA. Tile slices are vectors
which map to ZA's rows/columns in different ways.
A new dynamic target description is provided containing the ZA register, the SVG
register and the SVCR register. The size of ZA, like the SVE vector registers,
is based on the vector length register SVG (VG for SVE).
This patch enables SME register support for gdb.
[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture
Co-Authored-By: Ezra Sitorus <ezra.sitorus@arm.com>
---
gdb/Makefile.in | 4 +
gdb/aarch64-linux-nat.c | 101 ++-
gdb/aarch64-tdep.c | 719 +++++++++++++++++++-
gdb/aarch64-tdep.h | 47 ++
gdb/arch/aarch64-scalable-linux.c | 21 +
gdb/arch/aarch64-scalable-linux.h | 38 ++
gdb/arch/aarch64.c | 5 +
gdb/arch/aarch64.h | 57 +-
gdb/configure.tgt | 1 +
gdb/features/aarch64-sme.c | 63 ++
gdb/nat/aarch64-scalable-linux-ptrace.c | 573 +++++++++++++++-
gdb/nat/aarch64-scalable-linux-ptrace.h | 109 ++-
gdb/nat/aarch64-scalable-linux-sigcontext.h | 57 +-
gdbserver/configure.srv | 1 +
14 files changed, 1742 insertions(+), 54 deletions(-)
create mode 100644 gdb/arch/aarch64-scalable-linux.c
create mode 100644 gdb/arch/aarch64-scalable-linux.h
create mode 100644 gdb/features/aarch64-sme.c
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index bd9d8d0df10..100760cfecf 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -727,6 +727,7 @@ ALL_64_TARGET_OBS = \
arch/aarch64.o \
arch/aarch64-insn.o \
arch/aarch64-mte-linux.o \
+ arch/aarch64-scalable-linux.o \
arch/amd64.o \
arch/riscv.o \
bpf-tdep.o \
@@ -1521,6 +1522,7 @@ HFILES_NO_SRCDIR = \
arch/aarch64.h \
arch/aarch64-insn.h \
arch/aarch64-mte-linux.h \
+ arch/aarch64-scalable-linux.h \
arch/arc.h \
arch/arm.h \
arch/i386.h \
@@ -1559,6 +1561,7 @@ HFILES_NO_SRCDIR = \
nat/aarch64-linux-hw-point.h \
nat/aarch64-mte-linux-ptrace.h \
nat/aarch64-scalable-linux-ptrace.h \
+ nat/aarch64-scalable-linux-sigcontext.h \
nat/amd64-linux-siginfo.h \
nat/gdb_ptrace.h \
nat/gdb_thread_db.h \
@@ -1624,6 +1627,7 @@ ALLDEPFILES = \
arch/aarch64.c \
arch/aarch64-insn.c \
arch/aarch64-mte-linux.c \
+ arch/aarch64-scalable-linux.c \
arch/amd64.c \
arch/arc.c \
arch/arm.c \
diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
index a775631e9ec..cb97b205c86 100644
--- a/gdb/aarch64-linux-nat.c
+++ b/gdb/aarch64-linux-nat.c
@@ -55,6 +55,7 @@
#include "arch/aarch64-mte-linux.h"
#include "nat/aarch64-mte-linux-ptrace.h"
+#include "arch/aarch64-scalable-linux.h"
#include <string.h>
@@ -313,8 +314,11 @@ store_fpregs_to_thread (const struct regcache *regcache)
}
}
-/* Fill GDB's register array with the sve register values
- from the current thread. */
+/* Fill GDB's REGCACHE with the valid SVE register values from the current
+ thread.
+
+ This function handles reading data from SVE or SSVE states, depending
+ on which state is active at the moment. */
static void
fetch_sveregs_from_thread (struct regcache *regcache)
@@ -323,8 +327,11 @@ fetch_sveregs_from_thread (struct regcache *regcache)
aarch64_sve_regs_copy_to_reg_buf (regcache->ptid ().lwp (), regcache);
}
-/* Store to the current thread the valid sve register
- values in the GDB's register array. */
+/* Store the valid SVE register values from GDB's REGCACHE to the current
+ thread.
+
+ This function handles writing data to SVE or SSVE states, depending
+ on which state is active at the moment. */
static void
store_sveregs_to_thread (struct regcache *regcache)
@@ -334,6 +341,41 @@ store_sveregs_to_thread (struct regcache *regcache)
aarch64_sve_regs_copy_from_reg_buf (regcache->ptid ().lwp (), regcache);
}
+/* Fill GDB's REGCACHE with the ZA register set contents from the
+ current thread. If there is no active ZA registe state, make the
+ ZA register contents zero. */
+
+static void
+fetch_za_from_thread (struct regcache *regcache)
+{
+ aarch64_gdbarch_tdep *tdep
+ = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
+
+ /* Read ZA state from the thread to the register cache. */
+ aarch64_za_regs_copy_to_reg_buf (regcache->ptid ().lwp (),
+ regcache,
+ tdep->sme_za_regnum,
+ tdep->sme_svg_regnum,
+ tdep->sme_svcr_regnum);
+}
+
+/* Store the NT_ARM_ZA register set contents from GDB's REGCACHE to the current
+ thread. */
+
+static void
+store_za_to_thread (struct regcache *regcache)
+{
+ aarch64_gdbarch_tdep *tdep
+ = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
+
+ /* Write ZA state from the register cache to the thread. */
+ aarch64_za_regs_copy_from_reg_buf (regcache->ptid ().lwp (),
+ regcache,
+ tdep->sme_za_regnum,
+ tdep->sme_svg_regnum,
+ tdep->sme_svcr_regnum);
+}
+
/* Fill GDB's register array with the pointer authentication mask values from
the current thread. */
@@ -488,7 +530,10 @@ aarch64_fetch_registers (struct regcache *regcache, int regno)
if (regno == -1)
{
fetch_gregs_from_thread (regcache);
- if (tdep->has_sve ())
+
+ /* We attempt to fetch SVE registers if there is support for either
+ SVE or SME (due to the SSVE state of SME). */
+ if (tdep->has_sve () || tdep->has_sme ())
fetch_sveregs_from_thread (regcache);
else
fetch_fpregs_from_thread (regcache);
@@ -501,12 +546,16 @@ aarch64_fetch_registers (struct regcache *regcache, int regno)
if (tdep->has_tls ())
fetch_tlsregs_from_thread (regcache);
+
+ if (tdep->has_sme ())
+ fetch_za_from_thread (regcache);
}
/* General purpose register? */
else if (regno < AARCH64_V0_REGNUM)
fetch_gregs_from_thread (regcache);
/* SVE register? */
- else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM)
+ else if ((tdep->has_sve () || tdep->has_sme ())
+ && regno <= AARCH64_SVE_VG_REGNUM)
fetch_sveregs_from_thread (regcache);
/* FPSIMD register? */
else if (regno < AARCH64_FPCR_REGNUM)
@@ -516,6 +565,10 @@ aarch64_fetch_registers (struct regcache *regcache, int regno)
&& (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
|| regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)))
fetch_pauth_masks_from_thread (regcache);
+ /* SME register? */
+ else if (tdep->has_sme () && regno >= tdep->sme_reg_base
+ && regno < tdep->sme_reg_base + 3)
+ fetch_za_from_thread (regcache);
/* MTE register? */
else if (tdep->has_mte ()
&& (regno == tdep->mte_reg_base))
@@ -577,7 +630,10 @@ aarch64_store_registers (struct regcache *regcache, int regno)
if (regno == -1)
{
store_gregs_to_thread (regcache);
- if (tdep->has_sve ())
+
+ /* We attempt to store SVE registers if there is support for either
+ SVE or SME (due to the SSVE state of SME). */
+ if (tdep->has_sve () || tdep->has_sme ())
store_sveregs_to_thread (regcache);
else
store_fpregs_to_thread (regcache);
@@ -587,16 +643,24 @@ aarch64_store_registers (struct regcache *regcache, int regno)
if (tdep->has_tls ())
store_tlsregs_to_thread (regcache);
+
+ if (tdep->has_sme ())
+ store_za_to_thread (regcache);
}
/* General purpose register? */
else if (regno < AARCH64_V0_REGNUM)
store_gregs_to_thread (regcache);
/* SVE register? */
- else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM)
+ else if ((tdep->has_sve () || tdep->has_sme ())
+ && regno <= AARCH64_SVE_VG_REGNUM)
store_sveregs_to_thread (regcache);
/* FPSIMD register? */
else if (regno < AARCH64_FPCR_REGNUM)
store_fpregs_to_thread (regcache);
+ /* SME register? */
+ else if (tdep->has_sme () && regno >= tdep->sme_reg_base
+ && regno < tdep->sme_reg_base + 3)
+ store_za_to_thread (regcache);
/* MTE register? */
else if (tdep->has_mte ()
&& (regno == tdep->mte_reg_base))
@@ -784,10 +848,15 @@ aarch64_linux_nat_target::read_description ()
CORE_ADDR hwcap2 = linux_get_hwcap2 ();
aarch64_features features;
+ /* SVE/SSVE check. Reading VQ may return either the regular vector length
+ or the streaming vector length, depending on whether streaming mode is
+ active or not. */
features.vq = aarch64_sve_get_vq (tid);
features.pauth = hwcap & AARCH64_HWCAP_PACA;
features.mte = hwcap2 & HWCAP2_MTE;
features.tls = aarch64_tls_register_count (tid);
+ /* SME feature check. */
+ features.svq = aarch64_za_get_svq (tid);
return aarch64_read_description (features);
}
@@ -890,21 +959,27 @@ aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
if (gdbarch_bfd_arch_info (inf->gdbarch)->bits_per_word == 32)
return inf->gdbarch;
- /* Only return it if the current vector length matches the one in the tdep. */
+ /* Only return the inferior's gdbarch if both vq and svq match the ones in
+ the tdep. */
aarch64_gdbarch_tdep *tdep
= gdbarch_tdep<aarch64_gdbarch_tdep> (inf->gdbarch);
uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
- if (vq == tdep->vq)
+ uint64_t svq = aarch64_za_get_svq (ptid.lwp ());
+ if (vq == tdep->vq && svq == tdep->sme_svq)
return inf->gdbarch;
- /* We reach here if the vector length for the thread is different from its
+ /* We reach here if any vector length for the thread is different from its
value at process start. Lookup gdbarch via info (potentially creating a
- new one) by using a target description that corresponds to the new vq value
- and the current architecture features. */
+ new one) by using a target description that corresponds to the new vq/svq
+ value and the current architecture features. */
const struct target_desc *tdesc = gdbarch_target_desc (inf->gdbarch);
aarch64_features features = aarch64_features_from_target_desc (tdesc);
features.vq = vq;
+ /* We cast to uint8_t here because the features struct can get large, and it
+ is important to store the information in as little storage as
+ possible. */
+ features.svq = (uint8_t) svq;
struct gdbarch_info info;
info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index ea0d8ce2e27..c12856881cb 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -57,6 +57,8 @@
/* For inferior_ptid and current_inferior (). */
#include "inferior.h"
+/* For std::sqrt and std::pow. */
+#include <cmath>
/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
four members. */
@@ -190,6 +192,43 @@ struct aarch64_prologue_cache
trad_frame_saved_reg *saved_regs;
};
+/* Holds information used to read/write from/to ZA
+ pseudo-registers.
+
+ With this information, the read/write code can be simplified so it
+ deals only with the required information to map a ZA pseudo-register
+ to the exact bytes into the ZA contents buffer. Otherwise we'd need
+ to use a lot of conditionals. */
+
+struct za_offsets
+{
+ /* Offset, into ZA, of the starting byte of the pseudo-register. */
+ size_t starting_offset;
+ /* The size of the contiguous chunks of the pseudo-register. */
+ size_t chunk_size;
+ /* The number of pseudo-register chunks contained in ZA. */
+ size_t chunks;
+ /* The offset between each contiguous chunk. */
+ size_t stride_size;
+};
+
+/* Holds data that is helpful to determine the individual fields that make
+ up the names of the ZA pseudo-registers. It is also very helpful to
+ determine offsets, stride and sizes for reading ZA tiles and tile
+ slices. */
+
+struct za_pseudo_encoding
+{
+ /* The slice index (0 ~ svl). Only used for tile slices. */
+ uint8_t slice_index;
+ /* The tile number (0 ~ 15). */
+ uint8_t tile_index;
+ /* Direction (horizontal/vertical). Only used for tile slices. */
+ bool horizontal;
+ /* Qualifier index (0 ~ 4). These map to B, H, S, D and Q. */
+ uint8_t qualifier_index;
+};
+
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
@@ -2141,6 +2180,214 @@ aarch64_vnb_type (struct gdbarch *gdbarch)
return tdep->vnb_type;
}
+/* Return TRUE if REGNUM is a ZA tile slice pseudo-register number. Return
+ FALSE otherwise. */
+
+static bool
+is_sme_tile_slice_pseudo_register (struct gdbarch *gdbarch, int regnum)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_svq > 0);
+ gdb_assert (tdep->sme_pseudo_base <= regnum);
+ gdb_assert (regnum < tdep->sme_pseudo_base + tdep->sme_pseudo_count);
+
+ if (tdep->sme_tile_slice_pseudo_base <= regnum
+ && regnum < tdep->sme_tile_slice_pseudo_base
+ + tdep->sme_tile_slice_pseudo_count)
+ return true;
+
+ return false;
+}
+
+/* Given REGNUM, a ZA pseudo-register number, return, in ENCODING, the
+ decoded fields that make up its name. */
+
+static void
+aarch64_za_decode_pseudos (struct gdbarch *gdbarch, int regnum,
+ struct za_pseudo_encoding &encoding)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_svq > 0);
+ gdb_assert (tdep->sme_pseudo_base <= regnum);
+ gdb_assert (regnum < tdep->sme_pseudo_base + tdep->sme_pseudo_count);
+
+ if (is_sme_tile_slice_pseudo_register (gdbarch, regnum))
+ {
+ /* Calculate the tile slice pseudo-register offset relative to the other
+ tile slice pseudo-registers. */
+ int offset = regnum - tdep->sme_tile_slice_pseudo_base;
+
+ /* Fetch the qualifier. We can have 160 to 2560 possible tile slice
+ pseudo-registers. Each qualifier (we have 5 of them: B, H, S, D
+ and Q) covers 32 * svq pseudo-registers, so we divide the offset by
+ that constant. */
+ size_t qualifier = offset / (tdep->sme_svq * 32);
+ encoding.qualifier_index = qualifier;
+
+ /* Prepare to fetch the direction (d), tile number (t) and slice
+ number (s). */
+ int dts = offset % (tdep->sme_svq * 32);
+
+ /* The direction is represented by the even/odd numbers. Even-numbered
+ pseudo-registers are horizontal tile slices and odd-numbered
+ pseudo-registers are vertical tile slices. */
+ encoding.horizontal = !(dts & 1);
+
+ /* Fetch the tile number. The tile number is closely related to the
+ qualifier. B has 1 tile, H has 2 tiles, S has 4 tiles, D has 8 tiles
+ and Q has 16 tiles. */
+ encoding.tile_index = (dts >> 1) & ((1 << qualifier) - 1);
+
+ /* Fetch the slice number. The slice number is closely related to the
+ qualifier and the svl. */
+ encoding.slice_index = dts >> (qualifier + 1);
+ }
+ else
+ {
+ /* Calculate the tile pseudo-register offset relative to the other
+ tile pseudo-registers. */
+ int offset = regnum - tdep->sme_tile_pseudo_base;
+
+ encoding.qualifier_index = std::floor (std::log2 (offset + 1));
+ /* Calculate the tile number. */
+ encoding.tile_index = (offset + 1) - (1 << encoding.qualifier_index);
+ /* Direction and slice index don't get used for tiles. Set them to
+ 0/false values. */
+ encoding.slice_index = 0;
+ encoding.horizontal = false;
+ }
+}
+
+/* Return the type for a ZA tile slice pseudo-register based on ENCODING. */
+
+static struct type *
+aarch64_za_tile_slice_type (struct gdbarch *gdbarch,
+ const struct za_pseudo_encoding &encoding)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_svq > 0);
+
+ if (tdep->sme_tile_slice_type_q == nullptr)
+ {
+ /* Q tile slice type. */
+ tdep->sme_tile_slice_type_q
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint128,
+ tdep->sme_svq);
+ /* D tile slice type. */
+ tdep->sme_tile_slice_type_d
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint64,
+ tdep->sme_svq * 2);
+ /* S tile slice type. */
+ tdep->sme_tile_slice_type_s
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint32,
+ tdep->sme_svq * 4);
+ /* H tile slice type. */
+ tdep->sme_tile_slice_type_h
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint16,
+ tdep->sme_svq * 8);
+ /* B tile slice type. */
+ tdep->sme_tile_slice_type_b
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint8,
+ tdep->sme_svq * 16);
+ }
+
+ switch (encoding.qualifier_index)
+ {
+ case 4:
+ return tdep->sme_tile_slice_type_q;
+ case 3:
+ return tdep->sme_tile_slice_type_d;
+ case 2:
+ return tdep->sme_tile_slice_type_s;
+ case 1:
+ return tdep->sme_tile_slice_type_h;
+ case 0:
+ return tdep->sme_tile_slice_type_b;
+ default:
+ error (_("Invalid qualifier index %s for tile slice pseudo register."),
+ pulongest (encoding.qualifier_index));
+ }
+
+ gdb_assert_not_reached ("Unknown qualifier for ZA tile slice register");
+}
+
+/* Return the type for a ZA tile pseudo-register based on ENCODING. */
+
+static struct type *
+aarch64_za_tile_type (struct gdbarch *gdbarch,
+ const struct za_pseudo_encoding &encoding)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_svq > 0);
+
+ if (tdep->sme_tile_type_q == nullptr)
+ {
+ struct type *inner_vectors_type;
+
+ /* Q tile type. */
+ inner_vectors_type
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint128,
+ tdep->sme_svq);
+ tdep->sme_tile_type_q
+ = init_vector_type (inner_vectors_type, tdep->sme_svq);
+
+ /* D tile type. */
+ inner_vectors_type
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint64,
+ tdep->sme_svq * 2);
+ tdep->sme_tile_type_d
+ = init_vector_type (inner_vectors_type, tdep->sme_svq * 2);
+
+ /* S tile type. */
+ inner_vectors_type
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint32,
+ tdep->sme_svq * 4);
+ tdep->sme_tile_type_s
+ = init_vector_type (inner_vectors_type, tdep->sme_svq * 4);
+
+ /* H tile type. */
+ inner_vectors_type
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint16,
+ tdep->sme_svq * 8);
+ tdep->sme_tile_type_h
+ = init_vector_type (inner_vectors_type, tdep->sme_svq * 8);
+
+ /* B tile type. */
+ inner_vectors_type
+ = init_vector_type (builtin_type (gdbarch)->builtin_uint8,
+ tdep->sme_svq * 16);
+ tdep->sme_tile_type_b
+ = init_vector_type (inner_vectors_type, tdep->sme_svq * 16);
+ }
+
+ switch (encoding.qualifier_index)
+ {
+ case 4:
+ return tdep->sme_tile_type_q;
+ case 3:
+ return tdep->sme_tile_type_d;
+ case 2:
+ return tdep->sme_tile_type_s;
+ case 1:
+ return tdep->sme_tile_type_h;
+ case 0:
+ return tdep->sme_tile_type_b;
+ default:
+ error (_("Invalid qualifier index %s for ZA tile pseudo register."),
+ pulongest (encoding.qualifier_index));
+ }
+
+ gdb_assert_not_reached ("unknown qualifier for tile pseudo-register");
+}
+
/* Return the type for an AdvSISD V register. */
static struct type *
@@ -2573,6 +2820,73 @@ is_w_pseudo_register (struct gdbarch *gdbarch, int regnum)
return false;
}
+/* Return TRUE if REGNUM is a SME pseudo-register number. Return FALSE
+ otherwise. */
+
+static bool
+is_sme_pseudo_register (struct gdbarch *gdbarch, int regnum)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ if (tdep->has_sme () && tdep->sme_pseudo_base <= regnum
+ && regnum < tdep->sme_pseudo_base + tdep->sme_pseudo_count)
+ return true;
+
+ return false;
+}
+
+/* Convert ENCODING into a ZA tile slice name. */
+
+static const std::string
+aarch64_za_tile_slice_name (const struct za_pseudo_encoding &encoding)
+{
+ gdb_assert (encoding.qualifier_index >= 0);
+ gdb_assert (encoding.qualifier_index <= 4);
+ gdb_assert (encoding.tile_index >= 0);
+ gdb_assert (encoding.tile_index <= 15);
+ gdb_assert (encoding.slice_index >= 0);
+ gdb_assert (encoding.slice_index <= 255);
+
+ const char orientation = encoding.horizontal ? 'h' : 'v';
+
+ const char qualifiers[6] = "bhsdq";
+ const char qualifier = qualifiers [encoding.qualifier_index];
+ return string_printf ("za%d%c%c%d", encoding.tile_index, orientation,
+ qualifier, encoding.slice_index);
+}
+
+/* Convert ENCODING into a ZA tile name. */
+
+static const std::string
+aarch64_za_tile_name (const struct za_pseudo_encoding &encoding)
+{
+ /* Tiles don't use the slice number and the direction fields. */
+ gdb_assert (encoding.qualifier_index >= 0);
+ gdb_assert (encoding.qualifier_index <= 4);
+ gdb_assert (encoding.tile_index >= 0);
+ gdb_assert (encoding.tile_index <= 15);
+
+ const char qualifiers[6] = "bhsdq";
+ const char qualifier = qualifiers [encoding.qualifier_index];
+ return (string_printf ("za%d%c", encoding.tile_index, qualifier));
+}
+
+/* Given a SME pseudo-register REGNUM, return its type. */
+
+static struct type *
+aarch64_sme_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
+{
+ struct za_pseudo_encoding encoding;
+
+ /* Decode the SME pseudo-register number. */
+ aarch64_za_decode_pseudos (gdbarch, regnum, encoding);
+
+ if (is_sme_tile_slice_pseudo_register (gdbarch, regnum))
+ return aarch64_za_tile_slice_type (gdbarch, encoding);
+ else
+ return aarch64_za_tile_type (gdbarch, encoding);
+}
+
/* Return the pseudo register name corresponding to register regnum. */
static const char *
@@ -2693,6 +3007,9 @@ aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
}
+ if (is_sme_pseudo_register (gdbarch, regnum))
+ return tdep->sme_pseudo_names[regnum - tdep->sme_pseudo_base].c_str ();
+
/* RA_STATE is used for unwinding only. Do not assign it a name - this
prevents it from being read by methods such as
mi_cmd_trace_frame_collected. */
@@ -2735,6 +3052,9 @@ aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
if (is_w_pseudo_register (gdbarch, regnum))
return builtin_type (gdbarch)->builtin_uint32;
+ if (is_sme_pseudo_register (gdbarch, regnum))
+ return aarch64_sme_pseudo_register_type (gdbarch, regnum);
+
if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum)
return builtin_type (gdbarch)->builtin_uint64;
@@ -2767,6 +3087,8 @@ aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
&& p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
return group == all_reggroup || group == vector_reggroup;
+ else if (is_sme_pseudo_register (gdbarch, regnum))
+ return group == all_reggroup || group == vector_reggroup;
/* RA_STATE is used for unwinding only. Do not assign it to any groups. */
if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum)
return 0;
@@ -2796,6 +3118,122 @@ aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
return result_value;
}
+/* Helper function for reading/writing ZA pseudo-registers. Given REGNUM,
+ a ZA pseudo-register number, return, in OFFSETS, the information on positioning
+ of the bytes that must be read from/written to. */
+
+static void
+aarch64_za_offsets_from_regnum (struct gdbarch *gdbarch, int regnum,
+ struct za_offsets &offsets)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_svq > 0);
+ gdb_assert (tdep->sme_pseudo_base <= regnum);
+ gdb_assert (regnum < tdep->sme_pseudo_base + tdep->sme_pseudo_count);
+
+ struct za_pseudo_encoding encoding;
+
+ /* Decode the ZA pseudo-register number. */
+ aarch64_za_decode_pseudos (gdbarch, regnum, encoding);
+
+ /* Fetch the streaming vector length. */
+ size_t svl = sve_vl_from_vq (tdep->sme_svq);
+
+ if (is_sme_tile_slice_pseudo_register (gdbarch, regnum))
+ {
+ if (encoding.horizontal)
+ {
+ /* Horizontal tile slices are contiguous ranges of svl bytes. */
+
+ /* The starting offset depends on the tile index (to locate the tile
+ in the ZA buffer), the slice index (to locate the slice within the
+ tile) and the qualifier. */
+ offsets.starting_offset
+ = encoding.tile_index * svl + encoding.slice_index
+ * (svl >> encoding.qualifier_index);
+ /* Horizontal tile slice data is contiguous and thus doesn't have
+ a stride. */
+ offsets.stride_size = 0;
+ /* Horizontal tile slice data is contiguous and thus only has 1
+ chunk. */
+ offsets.chunks = 1;
+ /* The chunk size is always svl bytes. */
+ offsets.chunk_size = svl;
+ }
+ else
+ {
+ /* Vertical tile slices are non-contiguous ranges of
+ (1 << qualifier_index) bytes. */
+
+ /* The starting offset depends on the tile number (to locate the
+ tile in the ZA buffer), the slice index (to locate the element
+ within the tile slice) and the qualifier. */
+ offsets.starting_offset
+ = encoding.tile_index * svl + encoding.slice_index
+ * (1 << encoding.qualifier_index);
+ /* The offset between vertical tile slices depends on the qualifier
+ and svl. */
+ offsets.stride_size = svl << (encoding.qualifier_index);
+ /* The number of chunks depends on svl and the qualifier size. */
+ offsets.chunks = svl >> encoding.qualifier_index;
+ /* The chunk size depends on the qualifier. */
+ offsets.chunk_size = 1 << encoding.qualifier_index;
+ }
+ }
+ else
+ {
+ /* ZA tile pseudo-register. */
+
+ /* Starting offset depends on the tile index and qualifier. */
+ offsets.starting_offset = (encoding.tile_index) * svl;
+ /* The offset between tile slices depends on the qualifier and svl. */
+ offsets.stride_size = svl << (encoding.qualifier_index);
+ /* The number of chunks depends on the qualifier and svl. */
+ offsets.chunks = svl >> encoding.qualifier_index;
+ /* The chunk size is always svl bytes. */
+ offsets.chunk_size = svl;
+ }
+}
+
+/* Given REGNUM, a SME pseudo-register number, return its value in RESULT. */
+
+static struct value *
+aarch64_sme_pseudo_register_read (struct gdbarch *gdbarch,
+ readable_regcache *regcache, int regnum,
+ struct value *result)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_svq > 0);
+ gdb_assert (tdep->sme_pseudo_base <= regnum);
+ gdb_assert (regnum < tdep->sme_pseudo_base + tdep->sme_pseudo_count);
+
+ /* Fetch the offsets that we need in order to read from the correct blocks
+ of ZA. */
+ struct za_offsets offsets;
+ aarch64_za_offsets_from_regnum (gdbarch, regnum, offsets);
+
+ /* Fetch the contents of ZA. */
+ size_t svl = sve_vl_from_vq (tdep->sme_svq);
+ gdb::byte_vector za (std::pow (svl, 2));
+ regcache->raw_read (tdep->sme_za_regnum, za.data ());
+
+ /* Copy the requested data. */
+ for (int chunks = 0; chunks < offsets.chunks; chunks++)
+ {
+ const gdb_byte *source
+ = za.data () + offsets.starting_offset + chunks * offsets.stride_size;
+ gdb_byte *destination
+ = result->contents_raw ().data () + chunks * offsets.chunk_size;
+
+ memcpy (destination, source, offsets.chunk_size);
+ }
+ return result;
+}
+
/* Implement the "pseudo_register_read_value" gdbarch method. */
static struct value *
@@ -2829,6 +3267,9 @@ aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
return result_value;
}
+ else if (is_sme_pseudo_register (gdbarch, regnum))
+ return aarch64_sme_pseudo_register_read (gdbarch, regcache, regnum,
+ result_value);
regnum -= gdbarch_num_regs (gdbarch);
@@ -2888,6 +3329,44 @@ aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
regcache->raw_write (v_regnum, reg_buf);
}
+/* Given REGNUM, a SME pseudo-register number, store the bytes from DATA to the
+ pseudo-register. */
+
+static void
+aarch64_sme_pseudo_register_write (struct gdbarch *gdbarch,
+ struct regcache *regcache,
+ int regnum, const gdb_byte *data)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_svq > 0);
+ gdb_assert (tdep->sme_pseudo_base <= regnum);
+ gdb_assert (regnum < tdep->sme_pseudo_base + tdep->sme_pseudo_count);
+
+ /* Fetch the offsets that we need in order to write to the correct blocks
+ of ZA. */
+ struct za_offsets offsets;
+ aarch64_za_offsets_from_regnum (gdbarch, regnum, offsets);
+
+ /* Fetch the contents of ZA. */
+ size_t svl = sve_vl_from_vq (tdep->sme_svq);
+ gdb::byte_vector za (std::pow (svl, 2));
+
+ /* Copy the requested data. */
+ for (int chunks = 0; chunks < offsets.chunks; chunks++)
+ {
+ const gdb_byte *source = data + chunks * offsets.chunk_size;
+ gdb_byte *destination
+ = za.data () + offsets.starting_offset + chunks * offsets.stride_size;
+
+ memcpy (destination, source, offsets.chunk_size);
+ }
+
+ /* Write back to ZA. */
+ regcache->raw_write (tdep->sme_za_regnum, za.data ());
+}
+
/* Implement the "pseudo_register_write" gdbarch method. */
static void
@@ -2915,6 +3394,11 @@ aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
regcache->raw_write_part (x_regnum, offset, 4, buf);
return;
}
+ else if (is_sme_pseudo_register (gdbarch, regnum))
+ {
+ aarch64_sme_pseudo_register_write (gdbarch, regcache, regnum, buf);
+ return;
+ }
regnum -= gdbarch_num_regs (gdbarch);
@@ -3494,6 +3978,33 @@ aarch64_get_tdesc_vq (const struct target_desc *tdesc)
return sve_vq_from_vl (vl);
}
+
+/* Return the svq (streaming vector quotient) used when creating the target
+ description TDESC. */
+
+static uint64_t
+aarch64_get_tdesc_svq (const struct target_desc *tdesc)
+{
+ const struct tdesc_feature *feature_sme;
+
+ if (!tdesc_has_registers (tdesc))
+ return 0;
+
+ feature_sme = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sme");
+
+ if (feature_sme == nullptr)
+ return 0;
+
+ size_t svl_squared = tdesc_register_bitsize (feature_sme, "za");
+
+ /* We have the total size of the ZA matrix, in bits. Figure out the svl
+ value. */
+ size_t svl = std::sqrt (svl_squared / 8);
+
+ /* Now extract svq. */
+ return sve_vq_from_vl (svl);
+}
+
/* Get the AArch64 features present in the given target description. */
aarch64_features
@@ -3522,6 +4033,8 @@ aarch64_features_from_target_desc (const struct target_desc *tdesc)
features.tls = 1;
}
+ features.svq = aarch64_get_tdesc_svq (tdesc);
+
return features;
}
@@ -3641,6 +4154,35 @@ aarch64_remove_non_address_bits (struct gdbarch *gdbarch, CORE_ADDR pointer)
return aarch64_remove_top_bits (pointer, mask);
}
+/* Given NAMES, a vector of strings, initialize it with all the SME
+ pseudo-register names for the current streaming vector length. */
+
+static void
+aarch64_initialize_sme_pseudo_names (struct gdbarch *gdbarch,
+ std::vector<std::string> &names)
+{
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ gdb_assert (tdep->has_sme ());
+ gdb_assert (tdep->sme_tile_slice_pseudo_base > 0);
+ gdb_assert (tdep->sme_tile_pseudo_base > 0);
+
+ for (int i = 0; i < tdep->sme_tile_slice_pseudo_count; i++)
+ {
+ int regnum = tdep->sme_tile_slice_pseudo_base + i;
+ struct za_pseudo_encoding encoding;
+ aarch64_za_decode_pseudos (gdbarch, regnum, encoding);
+ names.push_back (aarch64_za_tile_slice_name (encoding));
+ }
+ for (int i = 0; i < AARCH64_ZA_TILES_NUM; i++)
+ {
+ int regnum = tdep->sme_tile_pseudo_base + i;
+ struct za_pseudo_encoding encoding;
+ aarch64_za_decode_pseudos (gdbarch, regnum, encoding);
+ names.push_back (aarch64_za_tile_name (encoding));
+ }
+}
+
/* Initialize the current architecture based on INFO. If possible,
re-use an architecture from ARCHES, which is a list of
architectures already created during this debugging session.
@@ -3658,11 +4200,17 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
int first_pauth_regnum = -1, ra_sign_state_offset = -1;
int first_mte_regnum = -1, first_tls_regnum = -1;
uint64_t vq = aarch64_get_tdesc_vq (info.target_desc);
+ uint64_t svq = aarch64_get_tdesc_svq (info.target_desc);
if (vq > AARCH64_MAX_SVE_VQ)
internal_error (_("VQ out of bounds: %s (max %d)"),
pulongest (vq), AARCH64_MAX_SVE_VQ);
+ if (svq > AARCH64_MAX_SVE_VQ)
+ internal_error (_("Streaming vector quotient (svq) out of bounds: %s"
+ " (max %d)"),
+ pulongest (svq), AARCH64_MAX_SVE_VQ);
+
/* If there is already a candidate, use it. */
for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
best_arch != nullptr;
@@ -3670,15 +4218,21 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
aarch64_gdbarch_tdep *tdep
= gdbarch_tdep<aarch64_gdbarch_tdep> (best_arch->gdbarch);
- if (tdep && tdep->vq == vq)
+ if (tdep && tdep->vq == vq && tdep->sme_svq == svq)
return best_arch->gdbarch;
}
/* Ensure we always have a target descriptor, and that it is for the given VQ
value. */
const struct target_desc *tdesc = info.target_desc;
- if (!tdesc_has_registers (tdesc))
- tdesc = aarch64_read_description ({});
+ if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc)
+ || svq != aarch64_get_tdesc_svq (tdesc))
+ {
+ aarch64_features features;
+ features.vq = vq;
+ features.svq = svq;
+ tdesc = aarch64_read_description (features);
+ }
gdb_assert (tdesc);
feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
@@ -3743,6 +4297,35 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
}
+ int first_sme_regnum = -1;
+ int first_sme_pseudo_regnum = -1;
+ const struct tdesc_feature *feature_sme
+ = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sme");
+ if (feature_sme != nullptr)
+ {
+ /* Record the first SME register. */
+ first_sme_regnum = num_regs;
+
+ valid_p &= tdesc_numbered_register (feature_sme, tdesc_data.get (),
+ num_regs++, "svg");
+
+ valid_p &= tdesc_numbered_register (feature_sme, tdesc_data.get (),
+ num_regs++, "svcr");
+
+ valid_p &= tdesc_numbered_register (feature_sme, tdesc_data.get (),
+ num_regs++, "za");
+
+ /* Record the first SME pseudo register. */
+ first_sme_pseudo_regnum = num_pseudo_regs;
+
+ /* Add the ZA tile slice pseudo registers. The number of tile slice
+ pseudo-registers depend on the svl, and is always a multiple of 5. */
+ num_pseudo_regs += (svq << 5) * 5;
+
+ /* Add the ZA tile pseudo registers. */
+ num_pseudo_regs += AARCH64_ZA_TILES_NUM;
+ }
+
/* Add the TLS register. */
int tls_register_count = 0;
if (feature_tls != nullptr)
@@ -3849,6 +4432,14 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->tls_regnum_base = first_tls_regnum;
tdep->tls_register_count = tls_register_count;
+ /* Set the SME register set details. The pseudo-registers will be adjusted
+ later. */
+ tdep->sme_reg_base = first_sme_regnum;
+ tdep->sme_svg_regnum = first_sme_regnum;
+ tdep->sme_svcr_regnum = first_sme_regnum + 1;
+ tdep->sme_za_regnum = first_sme_regnum + 2;
+ tdep->sme_svq = svq;
+
set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
@@ -3965,6 +4556,86 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
set_gdbarch_remove_non_address_bits (gdbarch,
aarch64_remove_non_address_bits);
+ /* SME pseudo-registers. */
+ if (tdep->has_sme ())
+ {
+ tdep->sme_pseudo_base = num_regs + first_sme_pseudo_regnum;
+ tdep->sme_tile_slice_pseudo_base = tdep->sme_pseudo_base;
+ tdep->sme_tile_slice_pseudo_count = (svq * 32) * 5;
+ tdep->sme_tile_pseudo_base
+ = tdep->sme_pseudo_base + tdep->sme_tile_slice_pseudo_count;
+ tdep->sme_pseudo_count
+ = tdep->sme_tile_slice_pseudo_count + AARCH64_ZA_TILES_NUM;
+
+ /* The SME ZA pseudo-registers are a set of 160 to 2560 pseudo-registers
+ depending on the value of svl.
+
+ The tile pseudo-registers are organized around their qualifiers
+ (b, h, s, d and q). Their numbers are distributed as follows:
+
+ b 0
+ h 1~2
+ s 3~6
+ d 7~14
+ q 15~30
+
+ The naming of the tile pseudo-registers follows the pattern za<t><q>,
+ where:
+
+ <t> is the tile number, with the following possible values based on
+ the qualifiers:
+
+ Qualifier - Allocated indexes
+
+ b - 0
+ h - 0~1
+ s - 0~3
+ d - 0~7
+ q - 0~15
+
+ <q> is the qualifier: b, h, s, d and q.
+
+ The tile slice pseudo-registers are organized around their
+ qualifiers as well (b, h, s, d and q), but also around their
+ direction (h - horizontal and v - vertical).
+
+ Even-numbered tile slice pseudo-registers are horizontally-oriented
+ and odd-numbered tile slice pseudo-registers are vertically-oriented.
+
+ Their numbers are distributed as follows:
+
+ Qualifier - Allocated indexes
+
+ b tile slices - 0~511
+ h tile slices - 512~1023
+ s tile slices - 1024~1535
+ d tile slices - 1536~2047
+ q tile slices - 2048~2559
+
+ The naming of the tile slice pseudo-registers follows the pattern
+ za<t><d><q><s>, where:
+
+ <t> is the tile number as described for the tile pseudo-registers.
+ <d> is the direction of the tile slice (h or v)
+ <q> is the qualifier of the tile slice (b, h, s, d or q)
+ <s> is the slice number, defined as follows:
+
+ Qualifier - Allocated indexes
+
+ b - 0~15
+ h - 0~7
+ s - 0~3
+ d - 0~1
+ q - 0
+
+ We have helper functions to translate to/from register index from/to
+ the set of fields that make the pseudo-register names. */
+
+ /* Build the array of pseudo-register names available for this
+ particular gdbarch configuration. */
+ aarch64_initialize_sme_pseudo_names (gdbarch, tdep->sme_pseudo_names);
+ }
+
/* Add standard register aliases. */
for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
user_reg_add (gdbarch, aarch64_register_aliases[i].name,
@@ -3986,6 +4657,48 @@ aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
gdb_printf (file, _("aarch64_dump_tdep: Lowest pc = 0x%s\n"),
paddress (gdbarch, tdep->lowest_pc));
+
+ /* SME fields. */
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_type_q = %s\n"),
+ host_address_to_string (tdep->sme_tile_type_q));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_type_d = %s\n"),
+ host_address_to_string (tdep->sme_tile_type_d));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_type_s = %s\n"),
+ host_address_to_string (tdep->sme_tile_type_s));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_type_h = %s\n"),
+ host_address_to_string (tdep->sme_tile_type_h));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_type_n = %s\n"),
+ host_address_to_string (tdep->sme_tile_type_b));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_slice_type_q = %s\n"),
+ host_address_to_string (tdep->sme_tile_slice_type_q));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_slice_type_d = %s\n"),
+ host_address_to_string (tdep->sme_tile_slice_type_d));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_slice_type_s = %s\n"),
+ host_address_to_string (tdep->sme_tile_slice_type_s));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_slice_type_h = %s\n"),
+ host_address_to_string (tdep->sme_tile_slice_type_h));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_slice_type_b = %s\n"),
+ host_address_to_string (tdep->sme_tile_slice_type_b));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_reg_base = %s\n"),
+ pulongest (tdep->sme_reg_base));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_svg_regnum = %s\n"),
+ pulongest (tdep->sme_svg_regnum));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_svcr_regnum = %s\n"),
+ pulongest (tdep->sme_svcr_regnum));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_za_regnum = %s\n"),
+ pulongest (tdep->sme_za_regnum));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_pseudo_base = %s\n"),
+ pulongest (tdep->sme_pseudo_base));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_pseudo_count = %s\n"),
+ pulongest (tdep->sme_pseudo_count));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_slice_pseudo_base = %s\n"),
+ pulongest (tdep->sme_tile_slice_pseudo_base));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_slice_pseudo_count = %s\n"),
+ pulongest (tdep->sme_tile_slice_pseudo_count));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_tile_pseudo_base = %s\n"),
+ pulongest (tdep->sme_tile_pseudo_base));
+ gdb_printf (file, _("aarch64_dump_tdep: sme_svq = %s\n"),
+ pulongest (tdep->sme_svq));
}
#if GDB_SELF_TEST
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index 505e050ba48..9297487a584 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -80,6 +80,22 @@ struct aarch64_gdbarch_tdep : gdbarch_tdep_base
struct type *vnb_type = nullptr;
struct type *vnv_type = nullptr;
+ /* Types for SME ZA tiles and tile slices pseudo-registers. */
+ struct type *sme_tile_type_q = nullptr;
+ struct type *sme_tile_type_d = nullptr;
+ struct type *sme_tile_type_s = nullptr;
+ struct type *sme_tile_type_h = nullptr;
+ struct type *sme_tile_type_b = nullptr;
+ struct type *sme_tile_slice_type_q = nullptr;
+ struct type *sme_tile_slice_type_d = nullptr;
+ struct type *sme_tile_slice_type_s = nullptr;
+ struct type *sme_tile_slice_type_h = nullptr;
+ struct type *sme_tile_slice_type_b = nullptr;
+
+ /* Vector of names for SME pseudo-registers. The number of elements is
+ different for each distinct svl value. */
+ std::vector<std::string> sme_pseudo_names;
+
/* syscall record. */
int (*aarch64_syscall_record) (struct regcache *regcache,
unsigned long svc_number) = nullptr;
@@ -125,6 +141,37 @@ struct aarch64_gdbarch_tdep : gdbarch_tdep_base
/* The W pseudo-registers. */
int w_pseudo_base = 0;
int w_pseudo_count = 0;
+
+ /* SME feature fields. */
+
+ /* Index of the first SME register. This is -1 if SME is not supported. */
+ int sme_reg_base = 0;
+ /* svg register index. */
+ int sme_svg_regnum = 0;
+ /* svcr register index. */
+ int sme_svcr_regnum = 0;
+ /* ZA register index. */
+ int sme_za_regnum = 0;
+ /* Index of the first SME pseudo-register. This is -1 if SME is not
+ supported. */
+ int sme_pseudo_base = 0;
+ /* Total number of SME pseudo-registers. */
+ int sme_pseudo_count = 0;
+ /* First tile slice pseudo-register index. */
+ int sme_tile_slice_pseudo_base = 0;
+ /* Total number of tile slice pseudo-registers. */
+ int sme_tile_slice_pseudo_count = 0;
+ /* First tile pseudo-register index. */
+ int sme_tile_pseudo_base = 0;
+ /* The streaming vector quotient (svq) for SME, or zero if SME is not
+ supported. */
+ size_t sme_svq = 0;
+
+ /* Return true if the target supports SME, and false otherwise. */
+ bool has_sme () const
+ {
+ return sme_svq != 0;
+ }
};
const target_desc *aarch64_read_description (const aarch64_features &features);
diff --git a/gdb/arch/aarch64-scalable-linux.c b/gdb/arch/aarch64-scalable-linux.c
new file mode 100644
index 00000000000..3803acfd9a8
--- /dev/null
+++ b/gdb/arch/aarch64-scalable-linux.c
@@ -0,0 +1,21 @@
+/* Common Linux arch-specific functionality for AArch64 scalable
+ extensions: SVE and SME.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "arch/aarch64-scalable-linux.h"
diff --git a/gdb/arch/aarch64-scalable-linux.h b/gdb/arch/aarch64-scalable-linux.h
new file mode 100644
index 00000000000..df1741004ed
--- /dev/null
+++ b/gdb/arch/aarch64-scalable-linux.h
@@ -0,0 +1,38 @@
+/* Common AArch64 Linux arch-specific definitions for the scalable
+ extensions: SVE and SME.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef ARCH_AARCH64_SCALABLE_LINUX_H
+#define ARCH_AARCH64_SCALABLE_LINUX_H
+
+#include "gdbsupport/common-defs.h"
+
+/* Feature check for Scalable Matrix Extension. */
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
+/* Streaming mode enabled/disabled bit. */
+#define SVCR_SM_BIT (1 << 0)
+/* ZA enabled/disabled bit. */
+#define SVCR_ZA_BIT (1 << 1)
+/* Mask including all valid SVCR bits. */
+#define SVCR_BIT_MASK (SVCR_SM_BIT | SVCR_ZA_BIT)
+
+#endif /* ARCH_AARCH64_SCALABLE_LINUX_H */
diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c
index 8644b9afcef..e1f4948aa25 100644
--- a/gdb/arch/aarch64.c
+++ b/gdb/arch/aarch64.c
@@ -24,6 +24,7 @@
#include "../features/aarch64-sve.c"
#include "../features/aarch64-pauth.c"
#include "../features/aarch64-mte.c"
+#include "../features/aarch64-sme.c"
#include "../features/aarch64-tls.c"
/* See arch/aarch64.h. */
@@ -57,6 +58,10 @@ aarch64_create_target_description (const aarch64_features &features)
if (features.tls > 0)
regnum = create_feature_aarch64_tls (tdesc.get (), regnum, features.tls);
+ if (features.svq)
+ regnum = create_feature_aarch64_sme (tdesc.get (), regnum,
+ sve_vl_from_vq (features.svq));
+
return tdesc.release ();
}
diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h
index 4b3f1b8eff8..c1cd233c51e 100644
--- a/gdb/arch/aarch64.h
+++ b/gdb/arch/aarch64.h
@@ -27,15 +27,27 @@
struct aarch64_features
{
/* A non zero VQ value indicates both the presence of SVE and the
- Vector Quotient - the number of 128bit chunks in an SVE Z
- register. */
- uint64_t vq = 0;
+ Vector Quotient - the number of 128-bit chunks in an SVE Z
+ register.
+ The maximum value for VQ is 16 (5 bits). */
+ uint64_t vq = 0;
bool pauth = false;
bool mte = false;
/* A positive TLS value indicates the number of TLS registers available. */
uint8_t tls = 0;
+ /* The allowed values for SVQ are the following:
+
+ 0 - SME is not supported/available.
+ 1 - SME is available, SVL is 16 bytes / 128-bit.
+ 2 - SME is available, SVL is 32 bytes / 256-bit.
+ 4 - SME is available, SVL is 64 bytes / 512-bit.
+ 8 - SME is available, SVL is 128 bytes / 1024-bit.
+ 16 - SME is available, SVL is 256 bytes / 2048-bit.
+
+ These use at most 5 bits to represent. */
+ uint8_t svq = 0;
};
inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs)
@@ -43,7 +55,8 @@ inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs)
return lhs.vq == rhs.vq
&& lhs.pauth == rhs.pauth
&& lhs.mte == rhs.mte
- && lhs.tls == rhs.tls;
+ && lhs.tls == rhs.tls
+ && lhs.svq == rhs.svq;
}
namespace std
@@ -61,6 +74,11 @@ namespace std
/* Shift by two bits for now. We may need to increase this in the future
if more TLS registers get added. */
h = h << 2 | features.tls;
+
+ /* Make sure the SVQ values are within the limits. */
+ gdb_assert (features.svq >= 0);
+ gdb_assert (features.svq <= 16);
+ h = h << 5 | (features.svq & 0x5);
return h;
}
};
@@ -171,4 +189,35 @@ enum aarch64_regnum
/* Maximum supported VQ value. Increase if required. */
#define AARCH64_MAX_SVE_VQ 16
+/* SME definitions
+
+ Some of these definitions are not found in the Architecture Reference
+ Manual, but we use them so we can keep a similar standard compared to the
+ SVE definitions that the Linux Kernel uses. Otherwise it can get
+ confusing.
+
+ SVL : Streaming Vector Length.
+ Although the documentation handles SVL in bits, we do it in
+ bytes to match what we do for SVE.
+
+ The streaming vector length dictates the size of the ZA register and
+ the size of the SVE registers when in streaming mode.
+
+ SVQ : Streaming Vector Quotient.
+ The number of 128-bit chunks in an SVE Z register or the size of
+ each dimension of the SME ZA matrix.
+
+ SVG : Streaming Vector Granule.
+ The number of 64-bit chunks in an SVE Z register or the size of
+ half a SME ZA matrix dimension. The SVG definition was added so
+ we keep a familiar definition when dealing with SVE registers in
+ streaming mode. */
+
+/* The total number of tiles. This is always fixed regardless of the
+ streaming vector length (svl). */
+#define AARCH64_ZA_TILES_NUM 31
+/* svl limits for SME. */
+#define AARCH64_SME_MIN_SVL 128
+#define AARCH64_SME_MAX_SVL 2048
+
#endif /* ARCH_AARCH64_H */
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index d5b7dd1e7d7..47a674201f9 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -146,6 +146,7 @@ aarch64*-*-linux*)
# Target: AArch64 linux
gdb_target_obs="aarch64-linux-tdep.o arch/aarch64.o\
arch/aarch64-mte-linux.o \
+ arch/aarch64-scalable-linux.o \
arch/arm.o arch/arm-linux.o arch/arm-get-next-pcs.o \
arm-tdep.o arm-linux-tdep.o \
glibc-tdep.o linux-tdep.o solib-svr4.o \
diff --git a/gdb/features/aarch64-sme.c b/gdb/features/aarch64-sme.c
new file mode 100644
index 00000000000..697a3014093
--- /dev/null
+++ b/gdb/features/aarch64-sme.c
@@ -0,0 +1,63 @@
+/* Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "gdbsupport/tdesc.h"
+#include <cmath>
+
+/* This function is NOT auto generated from xml. Create the AArch64 SME
+ feature into RESULT. SVL is the streaming vector length in bytes.
+
+ The ZA register has a total size of SVL x SVL.
+
+ When in Streaming SVE mode, the effective SVE vector length, VL, is equal
+ to SVL. */
+
+static int
+create_feature_aarch64_sme (struct target_desc *result, long regnum,
+ size_t svl)
+{
+ struct tdesc_feature *feature;
+ tdesc_type *element_type;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.sme");
+
+ /* The SVG register. */
+ tdesc_create_reg (feature, "svg", regnum++, 1, nullptr, 64, "int");
+
+ /* SVCR flags type. */
+ tdesc_type_with_fields *type_with_fields
+ = tdesc_create_flags (feature, "svcr_flags", 8);
+ tdesc_add_flag (type_with_fields, 0, "SM");
+ tdesc_add_flag (type_with_fields, 1, "ZA");
+
+ /* The SVCR register. */
+ tdesc_create_reg (feature, "svcr", regnum++, 1, nullptr, 64, "svcr_flags");
+
+ /* Byte type. */
+ element_type = tdesc_named_type (feature, "uint8");
+ /* Vector of bytes. */
+ element_type = tdesc_create_vector (feature, "sme_bv", element_type,
+ svl);
+ /* Vector of vector of bytes (Matrix). */
+ element_type = tdesc_create_vector (feature, "sme_bvv", element_type,
+ svl);
+
+ /* The following is the ZA register set. */
+ tdesc_create_reg (feature, "za", regnum++, 1, nullptr,
+ std::pow (svl, 2) * 8, "sme_bvv");
+ return regnum;
+}
diff --git a/gdb/nat/aarch64-scalable-linux-ptrace.c b/gdb/nat/aarch64-scalable-linux-ptrace.c
index 192eebcda19..4c78d788e1a 100644
--- a/gdb/nat/aarch64-scalable-linux-ptrace.c
+++ b/gdb/nat/aarch64-scalable-linux-ptrace.c
@@ -1,5 +1,4 @@
-/* Common target dependent routines for AArch64 Scalable Extensions
- (SVE/SME).
+/* Common native Linux code for the AArch64 scalable extensions: SVE and SME.
Copyright (C) 2018-2023 Free Software Foundation, Inc.
@@ -28,6 +27,193 @@
#include "gdbsupport/common-regcache.h"
#include "gdbsupport/byte-vector.h"
#include <endian.h>
+#include "arch/aarch64-scalable-linux.h"
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+aarch64_has_sve_state (int tid)
+{
+ struct user_sve_header header;
+
+ if (!read_sve_header (tid, header))
+ return false;
+
+ if ((header.flags & SVE_PT_REGS_SVE) == 0)
+ return false;
+
+ if (sizeof (header) == header.size)
+ return false;
+
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+aarch64_has_ssve_state (int tid)
+{
+ struct user_sve_header header;
+
+ if (!read_ssve_header (tid, header))
+ return false;
+
+ if ((header.flags & SVE_PT_REGS_SVE) == 0)
+ return false;
+
+ if (sizeof (header) == header.size)
+ return false;
+
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+aarch64_has_za_state (int tid)
+{
+ struct user_za_header header;
+
+ if (!read_za_header (tid, header))
+ return false;
+
+ if (sizeof (header) == header.size)
+ return false;
+
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+read_sve_header (int tid, struct user_sve_header &header)
+{
+ struct iovec iovec;
+
+ iovec.iov_len = sizeof (header);
+ iovec.iov_base = &header;
+
+ if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
+ {
+ /* SVE is not supported. */
+ return false;
+ }
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+write_sve_header (int tid, const struct user_sve_header &header)
+{
+ struct iovec iovec;
+
+ iovec.iov_len = sizeof (header);
+ iovec.iov_base = (void *) &header;
+
+ if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
+ {
+ /* SVE is not supported. */
+ return false;
+ }
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+read_ssve_header (int tid, struct user_sve_header &header)
+{
+ struct iovec iovec;
+
+ iovec.iov_len = sizeof (header);
+ iovec.iov_base = &header;
+
+ if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SSVE, &iovec) < 0)
+ {
+ /* SSVE is not supported. */
+ return false;
+ }
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+write_ssve_header (int tid, const struct user_sve_header &header)
+{
+ struct iovec iovec;
+
+ iovec.iov_len = sizeof (header);
+ iovec.iov_base = (void *) &header;
+
+ if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_SSVE, &iovec) < 0)
+ {
+ /* SSVE is not supported. */
+ return false;
+ }
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+read_za_header (int tid, struct user_za_header &header)
+{
+ struct iovec iovec;
+
+ iovec.iov_len = sizeof (header);
+ iovec.iov_base = &header;
+
+ if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_ZA, &iovec) < 0)
+ {
+ /* ZA is not supported. */
+ return false;
+ }
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+write_za_header (int tid, const struct user_za_header &header)
+{
+ struct iovec iovec;
+
+ iovec.iov_len = sizeof (header);
+ iovec.iov_base = (void *) &header;
+
+ if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_ZA, &iovec) < 0)
+ {
+ /* ZA is not supported. */
+ return false;
+ }
+ return true;
+}
+
+/* Given VL, the streaming vector length for SME, return true if it is valid
+ and false otherwise. */
+
+static bool
+aarch64_sme_vl_valid (size_t vl)
+{
+ return (vl == 16 || vl == 32 || vl == 64 || vl == 128 || vl == 256);
+}
+
+/* Given VL, the vector length for SVE, return true if it is valid and false
+ otherwise. SVE_state is true when the check is for the SVE register set.
+ Otherwise the check is for the SSVE register set. */
+
+static bool
+aarch64_sve_vl_valid (const bool sve_state, size_t vl)
+{
+ if (sve_state)
+ return sve_vl_valid (vl);
+
+ /* We have an active SSVE state, where the valid vector length values are
+ more restrictive. */
+ return aarch64_sme_vl_valid (vl);
+}
/* See nat/aarch64-scalable-linux-ptrace.h. */
@@ -36,23 +222,25 @@ aarch64_sve_get_vq (int tid)
{
struct iovec iovec;
struct user_sve_header header;
-
iovec.iov_len = sizeof (header);
iovec.iov_base = &header;
- /* Ptrace gives the vector length in bytes. Convert it to VQ, the number of
- 128bit chunks in a Z register. We use VQ because 128bits is the minimum
- a Z register can increase in size. */
-
- if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
+ /* Figure out which register set to use for the request. The vector length
+ for SVE can be different from the vector length for SSVE. */
+ bool has_sve_state = !aarch64_has_ssve_state (tid);
+ if (ptrace (PTRACE_GETREGSET, tid, has_sve_state? NT_ARM_SVE : NT_ARM_SSVE,
+ &iovec) < 0)
{
/* SVE is not supported. */
return 0;
}
+ /* Ptrace gives the vector length in bytes. Convert it to VQ, the number of
+ 128bit chunks in a Z register. We use VQ because 128 bits is the minimum
+ a Z register can increase in size. */
uint64_t vq = sve_vq_from_vl (header.vl);
- if (!sve_vl_valid (header.vl))
+ if (!aarch64_sve_vl_valid (has_sve_state, header.vl))
{
warning (_("Invalid SVE state from kernel; SVE disabled."));
return 0;
@@ -72,15 +260,20 @@ aarch64_sve_set_vq (int tid, uint64_t vq)
iovec.iov_len = sizeof (header);
iovec.iov_base = &header;
- if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
+ /* Figure out which register set to use for the request. The vector length
+ for SVE can be different from the vector length for SSVE. */
+ bool has_sve_state = !aarch64_has_ssve_state (tid);
+ if (ptrace (PTRACE_GETREGSET, tid, has_sve_state? NT_ARM_SVE : NT_ARM_SSVE,
+ &iovec) < 0)
{
- /* SVE is not supported. */
+ /* SVE/SSVE is not supported. */
return false;
}
header.vl = sve_vl_from_vq (vq);
- if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
+ if (ptrace (PTRACE_SETREGSET, tid, has_sve_state? NT_ARM_SVE : NT_ARM_SSVE,
+ &iovec) < 0)
{
/* Vector length change failed. */
return false;
@@ -120,13 +313,108 @@ aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf)
/* See nat/aarch64-scalable-linux-ptrace.h. */
+uint64_t
+aarch64_za_get_svq (int tid)
+{
+ struct user_za_header header;
+ if (!read_za_header (tid, header))
+ return 0;
+
+ uint64_t vq = sve_vq_from_vl (header.vl);
+
+ if (!aarch64_sve_vl_valid (false, header.vl))
+ {
+ warning (_("Invalid ZA state from kernel; ZA disabled."));
+ return 0;
+ }
+
+ return vq;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+aarch64_za_set_svq (int tid, uint64_t vq)
+{
+ struct iovec iovec;
+
+ /* Read the NT_ARM_ZA header. */
+ struct user_za_header header;
+ if (!read_za_header (tid, header))
+ {
+ /* ZA is not supported. */
+ return false;
+ }
+
+ /* If the size is the correct one already, don't update it. If we do
+ update the streaming vector length, we will invalidate the register
+ state for ZA, and we do not want that. */
+ if (header.vl == sve_vl_from_vq (vq))
+ return true;
+
+ /* The streaming vector length is about to get updated. Set the new value
+ in the NT_ARM_ZA header and adjust the size as well. */
+
+ header.vl = sve_vl_from_vq (vq);
+ header.size = sizeof (struct user_za_header);
+
+ /* Update the NT_ARM_ZA register set with the new streaming vector
+ length. */
+ iovec.iov_len = sizeof (header);
+ iovec.iov_base = &header;
+
+ if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_ZA, &iovec) < 0)
+ {
+ /* Streaming vector length change failed. */
+ return false;
+ }
+
+ /* At this point we have successfully adjusted the streaming vector length
+ for the NT_ARM_ZA register set, and it should have no payload
+ (no ZA state). */
+
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+aarch64_za_set_svq (int tid, const struct reg_buffer_common *reg_buf,
+ int svg_regnum)
+{
+ uint64_t reg_svg = 0;
+
+ /* The svg register may not be valid if we've not collected any value yet.
+ This can happen, for example, if we're restoring the regcache after an
+ inferior function call, and the svg register comes after the Z
+ registers. */
+ if (reg_buf->get_register_status (svg_regnum) != REG_VALID)
+ {
+ /* If svg is not available yet, fetch it from ptrace. The svg value from
+ ptrace is likely the correct one. */
+ uint64_t svq = aarch64_za_get_svq (tid);
+
+ /* If something went wrong, just bail out. */
+ if (svq == 0)
+ return false;
+
+ reg_svg = sve_vg_from_vq (svq);
+ }
+ else
+ reg_buf->raw_collect (svg_regnum, ®_svg);
+
+ return aarch64_za_set_svq (tid, sve_vq_from_vg (reg_svg));
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
gdb::byte_vector
aarch64_fetch_sve_regset (int tid)
{
uint64_t vq = aarch64_sve_get_vq (tid);
if (vq == 0)
- perror_with_name (_("Unable to fetch SVE vector length"));
+ perror_with_name (_("Unable to fetch SVE/SSVE vector length"));
/* A ptrace call with NT_ARM_SVE will return a header followed by either a
dump of all the SVE and FP registers, or an fpsimd structure (identical to
@@ -139,8 +427,10 @@ aarch64_fetch_sve_regset (int tid)
iovec.iov_base = sve_state.data ();
iovec.iov_len = sve_state.size ();
- if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
- perror_with_name (_("Unable to fetch SVE registers"));
+ bool has_sve_state = !aarch64_has_ssve_state (tid);
+ if (ptrace (PTRACE_GETREGSET, tid, has_sve_state? NT_ARM_SVE : NT_ARM_SSVE,
+ &iovec) < 0)
+ perror_with_name (_("Unable to fetch SVE/SSVE registers"));
return sve_state;
}
@@ -154,12 +444,87 @@ aarch64_store_sve_regset (int tid, const gdb::byte_vector &sve_state)
iovec.iov_base = (void *) sve_state.data ();
iovec.iov_len = sve_state.size ();
- if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
- perror_with_name (_("Unable to store SVE registers"));
+ bool has_sve_state = !aarch64_has_ssve_state (tid);
+ if (ptrace (PTRACE_SETREGSET, tid, has_sve_state? NT_ARM_SVE : NT_ARM_SSVE,
+ &iovec) < 0)
+ perror_with_name (_("Unable to store SVE/SSVE registers"));
return true;
}
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+gdb::byte_vector
+aarch64_fetch_za_regset (int tid)
+{
+ struct user_za_header header;
+ if (!read_za_header (tid, header))
+ error (_("Failed to read NT_ARM_ZA header."));
+
+ if (!aarch64_sme_vl_valid (header.vl))
+ error (_("Found invalid vector length for NT_ARM_ZA."));
+
+ struct iovec iovec;
+ iovec.iov_len = header.size;
+ gdb::byte_vector za_state (header.size);
+ iovec.iov_base = za_state.data ();
+
+ if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_ZA, &iovec) < 0)
+ perror_with_name (_("Failed to fetch NT_ARM_ZA register set."));
+
+ return za_state;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+bool
+aarch64_store_za_regset (int tid, const gdb::byte_vector &za_state)
+{
+ struct iovec iovec;
+ iovec.iov_len = za_state.size ();
+ iovec.iov_base = (void *) za_state.data ();
+
+ if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_ZA, &iovec) < 0)
+ perror_with_name (_("Failed to write to the NT_ARM_ZA register set."));
+
+ return true;
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+void
+aarch64_initialize_za_regset (int tid)
+{
+ /* First fetch the NT_ARM_ZA header so we can fetch the streaming vector
+ length. */
+ struct user_za_header header;
+ if (!read_za_header (tid, header))
+ error (_("Failed to read NT_ARM_ZA header."));
+
+ /* The vector should be default-initialized to zero, and we should account
+ for the payload as well. */
+ std::vector<gdb_byte> za_new_state (ZA_PT_SIZE (sve_vq_from_vl (header.vl)));
+
+ /* Adjust the header size since we are adding the initialized ZA
+ payload. */
+ header.size = ZA_PT_SIZE (sve_vq_from_vl (header.vl));
+
+ /* Overlay the modified header onto the new ZA state. */
+ const gdb_byte *base = (gdb_byte *) &header;
+ memcpy (za_new_state.data (), base, sizeof (user_za_header));
+
+ /* Set the ptrace request up and update the NT_ARM_ZA register set. */
+ struct iovec iovec;
+ iovec.iov_len = za_new_state.size ();
+ iovec.iov_base = (void *) za_new_state.data ();
+
+ if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_ZA, &iovec) < 0)
+ perror_with_name (_("Failed to initialize the NT_ARM_ZA register set."));
+
+ /* The NT_ARM_ZA register set should now contain a zero-initialized ZA
+ payload. */
+}
+
/* If we are running in BE mode, byteswap the contents
of SRC to DST for SIZE bytes. Other, just copy the contents
from SRC to DST. */
@@ -452,3 +817,177 @@ aarch64_sve_regs_copy_from_reg_buf (int tid,
passed on to ptrace. */
aarch64_store_sve_regset (tid, new_state);
}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+void
+aarch64_za_regs_copy_to_reg_buf (int tid, struct reg_buffer_common *reg_buf,
+ int za_regnum, int svg_regnum,
+ int svcr_regnum)
+{
+ /* Fetch the current ZA state from the thread. */
+ gdb::byte_vector za_state = aarch64_fetch_za_regset (tid);
+
+ /* Sanity check. */
+ gdb_assert (!za_state.empty ());
+
+ char *base = (char *) za_state.data ();
+ struct user_za_header *header = (struct user_za_header *) base;
+
+ /* If we have ZA state, read it. Otherwise, make the contents of ZA
+ in the register cache all zeroes. This is how we present the ZA
+ state when it is not initialized. */
+ uint64_t svcr_value = 0;
+ if (aarch64_has_za_state (tid))
+ {
+ /* Sanity check the data in the header. */
+ if (!sve_vl_valid (header->vl)
+ || ZA_PT_SIZE (sve_vq_from_vl (header->vl)) != header->size)
+ {
+ error (_("Found invalid streaming vector length in NT_ARM_ZA"
+ " register set"));
+ }
+
+ reg_buf->raw_supply (za_regnum, base + ZA_PT_ZA_OFFSET);
+ svcr_value |= SVCR_ZA_BIT;
+ }
+ else
+ {
+ size_t za_bytes = header->vl * header->vl;
+ gdb_byte za_zeroed[za_bytes];
+ memset (za_zeroed, 0, za_bytes);
+ reg_buf->raw_supply (za_regnum, za_zeroed);
+ }
+
+ /* Handle the svg and svcr registers separately. We need to calculate
+ their values manually, as the Linux Kernel doesn't expose those
+ explicitly. */
+ svcr_value |= aarch64_has_ssve_state (tid)? SVCR_SM_BIT : 0;
+ uint64_t svg_value = sve_vg_from_vl (header->vl);
+
+ /* Update the contents of svg and svcr registers. */
+ reg_buf->raw_supply (svg_regnum, &svg_value);
+ reg_buf->raw_supply (svcr_regnum, &svcr_value);
+
+ /* The register buffer should now contain the updated copy of the NT_ARM_ZA
+ state. */
+}
+
+/* See nat/aarch64-scalable-linux-ptrace.h. */
+
+void
+aarch64_za_regs_copy_from_reg_buf (int tid,
+ struct reg_buffer_common *reg_buf,
+ int za_regnum, int svg_regnum,
+ int svcr_regnum)
+{
+ /* REG_BUF contains the updated ZA state. We need to extract that state
+ and write it to the thread TID. */
+
+
+ /* First check if there is a change to the streaming vector length. Two
+ outcomes are possible here:
+
+ 1 - The streaming vector length in the register cache differs from the
+ one currently on the thread state. This means that we will need to
+ update the NT_ARM_ZA register set to reflect the new streaming vector
+ length.
+
+ 2 - The streaming vector length in the register cache is the same as in
+ the thread state. This means we do not need to update the NT_ARM_ZA
+ register set for a new streaming vector length, and we only need to
+ deal with changes to za, svg and svcr.
+
+ None of the two possibilities above imply that the ZA state actually
+ exists. They only determine what needs to be done with any ZA content
+ based on the state of the streaming vector length. */
+
+ /* First fetch the NT_ARM_ZA header so we can fetch the streaming vector
+ length. */
+ struct user_za_header header;
+ if (!read_za_header (tid, header))
+ error (_("Failed to read NT_ARM_ZA header."));
+
+ /* Fetch the current streaming vector length. */
+ uint64_t old_svg = sve_vg_from_vl (header.vl);
+
+ /* Fetch the (potentially) new streaming vector length. */
+ uint64_t new_svg;
+ reg_buf->raw_collect (svg_regnum, &new_svg);
+
+ /* Did the streaming vector length change? */
+ bool svg_changed = new_svg != old_svg;
+
+ /* First store the streaming vector length to the thread. This is done
+ first to ensure the ptrace buffers read from the kernel are the correct
+ size. If the streaming vector length is the same as the current one, it
+ won't be updated. */
+ if (!aarch64_za_set_svq (tid, reg_buf, svg_regnum))
+ error (_("Unable to set svg register"));
+
+ bool has_za_state = aarch64_has_za_state (tid);
+
+ size_t za_bytes = sve_vl_from_vg (old_svg) * sve_vl_from_vg (old_svg);
+ gdb_byte za_zeroed[za_bytes];
+ memset (za_zeroed, 0, za_bytes);
+
+ /* If the streaming vector length changed, zero out the contents of ZA in
+ the register cache. Otherwise, we will need to update the ZA contents
+ in the thread with the ZA contents from the register cache, and they will
+ differ in size. */
+ if (svg_changed)
+ reg_buf->raw_supply (za_regnum, za_zeroed);
+
+ /* When we update svg, we don't automatically initialize the ZA buffer. If
+ we have no ZA state and the ZA register contents in the register cache are
+ zero, just return and leave the ZA register cache contents as zero. */
+ if (!has_za_state
+ && reg_buf->raw_compare (za_regnum, za_zeroed, 0))
+ {
+ /* No ZA state in the thread or in the register cache. This was lilely
+ just an adjustment of the streaming vector length. Let this fall
+ through and update svcr and svg in the register cache. */
+ }
+ else
+ {
+ /* If there is no ZA state but the register cache contains ZA data, we
+ need to initialize the ZA data through ptrace. First we initialize
+ all the bytes of ZA to zero. */
+ if (!has_za_state
+ && !reg_buf->raw_compare (za_regnum, za_zeroed, 0))
+ aarch64_initialize_za_regset (tid);
+
+ /* From this point onwards, it is assumed we have a ZA payload in
+ the NT_ARM_ZA register set for this thread, and we need to update
+ such state based on the contents of the register cache. */
+
+ /* Fetch the current ZA state from the thread. */
+ gdb::byte_vector za_state = aarch64_fetch_za_regset (tid);
+
+ char *base = (char *) za_state.data ();
+ struct user_za_header *za_header = (struct user_za_header *) base;
+ uint64_t svq = sve_vq_from_vl (za_header->vl);
+
+ /* Sanity check the data in the header. */
+ if (!sve_vl_valid (za_header->vl)
+ || ZA_PT_SIZE (svq) != za_header->size)
+ error (_("Invalid vector length or payload size when reading ZA."));
+
+ /* Overwrite the ZA state contained in the thread with the ZA state from
+ the register cache. */
+ if (REG_VALID == reg_buf->get_register_status (za_regnum))
+ reg_buf->raw_collect (za_regnum, base + ZA_PT_ZA_OFFSET);
+
+ /* Write back the ZA state to the thread's NT_ARM_ZA register set. */
+ aarch64_store_za_regset (tid, za_state);
+ }
+
+ /* Update svcr and svg accordingly. */
+ uint64_t svcr_value = 0;
+ svcr_value |= aarch64_has_ssve_state (tid)? SVCR_SM_BIT : 0;
+ svcr_value |= aarch64_has_za_state (tid)? SVCR_ZA_BIT : 0;
+ reg_buf->raw_supply (svcr_regnum, &svcr_value);
+
+ /* At this point we have written the data contained in the register cache to
+ the thread's NT_ARM_ZA register set. */
+}
diff --git a/gdb/nat/aarch64-scalable-linux-ptrace.h b/gdb/nat/aarch64-scalable-linux-ptrace.h
index 3215103c88a..5fac51ca98b 100644
--- a/gdb/nat/aarch64-scalable-linux-ptrace.h
+++ b/gdb/nat/aarch64-scalable-linux-ptrace.h
@@ -1,5 +1,5 @@
-/* Common target dependent definitions for AArch64 Scalable Extensions
- (SVE/SME).
+/* Common native Linux definitions for the AArch64 scalable
+ extensions: SVE and SME.
Copyright (C) 2018-2023 Free Software Foundation, Inc.
@@ -31,19 +31,58 @@
result when <asm/ptrace.h> is included before <sys/ptrace.h>. */
#include <sys/ptrace.h>
#include <asm/ptrace.h>
-
-#ifndef SVE_SIG_ZREGS_SIZE
+#include <stdarg.h>
+#include "aarch64-scalable-linux-ptrace.h"
#include "aarch64-scalable-linux-sigcontext.h"
-#endif
/* Indicates whether a SVE ptrace header is followed by SVE registers or a
fpsimd structure. */
-
#define HAS_SVE_STATE(header) ((header).flags & SVE_PT_REGS_SVE)
+/* Return true if there is an active SVE state in TID.
+ Return false otherwise. */
+bool aarch64_has_sve_state (int tid);
+
+/* Return true if there is an active SSVE state in TID.
+ Return false otherwise. */
+bool aarch64_has_ssve_state (int tid);
+
+/* Return true if there is an active ZA state in TID.
+ Return false otherwise. */
+bool aarch64_has_za_state (int tid);
+
+/* Given TID, read the SVE header into HEADER.
+
+ Return true if successful, false otherwise. */
+bool read_sve_header (int tid, struct user_sve_header &header);
+
+/* Given TID, store the SVE HEADER.
+
+ Return true if successful, false otherwise. */
+bool write_sve_header (int tid, const struct user_sve_header &header);
+
+/* Given TID, read the SSVE header into HEADER.
+
+ Return true if successful, false otherwise. */
+bool read_ssve_header (int tid, struct user_sve_header &header);
+
+/* Given TID, store the SSVE HEADER.
+
+ Return true if successful, false otherwise. */
+bool write_ssve_header (int tid, const struct user_sve_header &header);
+
+/* Given TID, read the ZA header into HEADER.
+
+ Return true if successful, false otherwise. */
+bool read_za_header (int tid, struct user_za_header &header);
+
+/* Given TID, store the ZA HEADER.
+
+ Return true if successful, false otherwise. */
+bool write_za_header (int tid, const struct user_za_header &header);
+
/* Read VQ for the given tid using ptrace. If SVE is not supported then zero
is returned (on a system that supports SVE, then VQ cannot be zero). */
-
uint64_t aarch64_sve_get_vq (int tid);
/* Set VQ in the kernel for the given tid, using either the value VQ or
@@ -52,28 +91,66 @@ uint64_t aarch64_sve_get_vq (int tid);
bool aarch64_sve_set_vq (int tid, uint64_t vq);
bool aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf);
-/* Read the current SVE register set from thread TID and return its data
- through a byte vector. */
+/* Read the streaming mode vq (svq) for the given TID. If the ZA state is not
+ supported or active, return 0. */
+uint64_t aarch64_za_get_svq (int tid);
+/* Set the vector quotient (vq) in the kernel for the given TID using the
+ value VQ.
+
+ Return true if successful, false otherwise. */
+bool aarch64_za_set_svq (int tid, uint64_t vq);
+bool aarch64_za_set_svq (int tid, const struct reg_buffer_common *reg_buf,
+ int svg_regnum);
+
+/* Given TID, return the SVE/SSVE data as a vector of bytes. */
extern gdb::byte_vector aarch64_fetch_sve_regset (int tid);
-/* Write the SVE contents from SVE_STATE to thread TID. Return true if
+/* Write the SVE/SSVE contents from SVE_STATE to TID. Return true if
successful and false otherwise. */
+extern bool aarch64_store_sve_regset (int tid,
+ const gdb::byte_vector &sve_state);
-extern bool
-aarch64_store_sve_regset (int tid, const gdb::byte_vector &sve_state);
+/* Given TID, return the ZA data as a vector of bytes. */
+extern gdb::byte_vector aarch64_fetch_za_regset (int tid);
-/* Given a thread id TID and a register buffer REG_BUF, update the register
- buffer with the SVE state from thread TID. */
+/* Write ZA_STATE for TID. Return true if successful and false
+ otherwise. */
+extern bool aarch64_store_za_regset (int tid, const gdb::byte_vector &za_state);
+/* Given TID, initialize the ZA register set so the header contains the right
+ size. The bytes of the ZA register are initialized to zero. */
+extern void aarch64_initialize_za_regset (int tid);
+
+/* Given a register buffer REG_BUF, update it with SVE/SSVE register data
+ from SVE_STATE. */
extern void
aarch64_sve_regs_copy_to_reg_buf (int tid, struct reg_buffer_common *reg_buf);
-/* Given a thread id TID and a register buffer REG_BUF containing SVE
+/* Given a thread id TID and a register buffer REG_BUF containing SVE/SSVE
register data, write the SVE data to thread TID. */
-
extern void
aarch64_sve_regs_copy_from_reg_buf (int tid,
struct reg_buffer_common *reg_buf);
+/* Given a thread id TID and a register buffer REG_BUF, update the register
+ buffer with the ZA state from thread TID.
+
+ ZA_REGNUM, SVG_REGNUM and SVCR_REGNUM are the register numbers for ZA,
+ SVG and SVCR registers. */
+extern void aarch64_za_regs_copy_to_reg_buf (int tid,
+ struct reg_buffer_common *reg_buf,
+ int za_regnum, int svg_regnum,
+ int svcr_regnum);
+
+/* Given a thread id TID and a register buffer REG_BUF containing ZA register
+ data, write the ZA data to thread TID.
+
+ ZA_REGNUM, SVG_REGNUM and SVCR_REGNUM are the register numbers for ZA,
+ SVG and SVCR registers. */
+extern void
+aarch64_za_regs_copy_from_reg_buf (int tid,
+ struct reg_buffer_common *reg_buf,
+ int za_regnum, int svg_regnum,
+ int svcr_regnum);
#endif /* NAT_AARCH64_SCALABLE_LINUX_PTRACE_H */
diff --git a/gdb/nat/aarch64-scalable-linux-sigcontext.h b/gdb/nat/aarch64-scalable-linux-sigcontext.h
index e0120e093a0..74407bd266a 100644
--- a/gdb/nat/aarch64-scalable-linux-sigcontext.h
+++ b/gdb/nat/aarch64-scalable-linux-sigcontext.h
@@ -22,8 +22,11 @@
#ifndef NAT_AARCH64_SCALABLE_LINUX_SIGCONTEXT_H
#define NAT_AARCH64_SCALABLE_LINUX_SIGCONTEXT_H
+#ifndef SVE_SIG_ZREGS_SIZE
+
#define SVE_MAGIC 0x53564501
+
struct sve_context {
struct _aarch64_ctx head;
__u16 vl;
@@ -132,7 +135,7 @@ struct sve_context {
#define SVE_SIG_CONTEXT_SIZE(vq) (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
-/* SVE/FP/SIMD state (NT_ARM_SVE) */
+/* SVE/FP/SIMD state (NT_ARM_SVE and NT_ARM_SSVE) */
struct user_sve_header {
__u32 size; /* total meaningful regset content in bytes */
@@ -242,6 +245,7 @@ struct user_sve_header {
(SVE_PT_SVE_PREG_OFFSET(vq, SVE_NUM_PREGS) - \
SVE_PT_SVE_PREGS_OFFSET(vq))
+/* For streaming mode SVE (SSVE) FFR must be read and written as zero. */
#define SVE_PT_SVE_FFR_OFFSET(vq) \
__SVE_SIG_TO_PT(SVE_SIG_FFR_OFFSET(vq))
@@ -267,4 +271,55 @@ struct user_sve_header {
SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \
: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
+#endif /* SVE_SIG_ZREGS_SIZE */
+
+/* Scalable Matrix Extensions (SME) definitions. */
+
+/* Make sure we only define these if the kernel header doesn't. */
+#ifndef ZA_PT_SIZE
+
+/* ZA state (NT_ARM_ZA) */
+struct user_za_header {
+ __u32 size; /* total meaningful regset content in bytes */
+ __u32 max_size; /* maximum possible size for this thread */
+ __u16 vl; /* current vector length */
+ __u16 max_vl; /* maximum possible vector length */
+ __u16 flags;
+ __u16 __reserved;
+};
+
+/* The remainder of the ZA state follows struct user_za_header. The
+ total size of the ZA state (including header) depends on the
+ metadata in the header: ZA_PT_SIZE(vq, flags) gives the total size
+ of the state in bytes, including the header.
+
+ Refer to arch/arm64/include/uapi/asm/sigcontext.h from the Linux kernel
+ for details of how to pass the correct "vq" argument to these macros. */
+
+/* Offset from the start of struct user_za_header to the register data */
+#define ZA_PT_ZA_OFFSET \
+ ((sizeof (struct user_za_header) + (__SVE_VQ_BYTES - 1)) \
+ / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
+
+/* The payload starts at offset ZA_PT_ZA_OFFSET, and is of size
+ ZA_PT_ZA_SIZE(vq, flags).
+
+ The ZA array is stored as a sequence of horizontal vectors ZAV of SVL/8
+ bytes each, starting from vector 0.
+
+ Additional data might be appended in the future.
+
+ The ZA matrix is represented in memory in an endianness-invariant layout
+ which differs from the layout used for the FPSIMD V-registers on big-endian
+ systems: see sigcontext.h for more explanation. */
+
+#define ZA_PT_ZAV_OFFSET(vq, n) \
+ (ZA_PT_ZA_OFFSET + ((vq * __SVE_VQ_BYTES) * n))
+
+#define ZA_PT_ZA_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
+
+#define ZA_PT_SIZE(vq) \
+ (ZA_PT_ZA_OFFSET + ZA_PT_ZA_SIZE(vq))
+#endif /* ZA_PT_SIZE */
+
#endif /* NAT_AARCH64_SCALABLE_LINUX_SIGCONTEXT_H */
diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
index f625c808859..6edcad03aaf 100644
--- a/gdbserver/configure.srv
+++ b/gdbserver/configure.srv
@@ -49,6 +49,7 @@ case "${gdbserver_host}" in
srv_tgtobj="$srv_tgtobj arch/aarch64-insn.o"
srv_tgtobj="$srv_tgtobj arch/aarch64.o"
srv_tgtobj="$srv_tgtobj arch/aarch64-mte-linux.o"
+ srv_tgtobj="$srv_tgtobj arch/aarch64-scalable-linux.o"
srv_tgtobj="$srv_tgtobj linux-aarch64-tdesc.o"
srv_tgtobj="$srv_tgtobj nat/aarch64-mte-linux-ptrace.o"
srv_tgtobj="$srv_tgtobj nat/aarch64-scalable-linux-ptrace.o"
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 06/17] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (4 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 05/17] [gdb/aarch64] sme: Enable SME registers and pseudo-registers Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 07/17] [gdbserver/aarch64] sme: Add support for SME Luis Machado
` (11 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
Instead of using static arrays, build the list of expedited registers
dynamically using a std::vector.
This refactor shouldn't cause any user-visible changes.
Regression-tested for aarch64-linux Ubuntu 22.04/20.04.
---
gdbserver/linux-aarch64-tdesc.cc | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/gdbserver/linux-aarch64-tdesc.cc b/gdbserver/linux-aarch64-tdesc.cc
index 633134955e5..3c60e1a4db0 100644
--- a/gdbserver/linux-aarch64-tdesc.cc
+++ b/gdbserver/linux-aarch64-tdesc.cc
@@ -30,6 +30,8 @@
/* All possible aarch64 target descriptors. */
static std::unordered_map<aarch64_features, target_desc *> tdesc_aarch64_map;
+static std::vector<const char *> expedited_registers;
+
/* Create the aarch64 target description. */
const target_desc *
@@ -44,15 +46,20 @@ aarch64_linux_read_description (const aarch64_features &features)
if (tdesc == NULL)
{
tdesc = aarch64_create_target_description (features);
+ expedited_registers.clear ();
+
+ /* Configure the expedited registers. By default we include x29, sp and
+ pc. */
+ expedited_registers.push_back ("x29");
+ expedited_registers.push_back ("sp");
+ expedited_registers.push_back ("pc");
+
+ if (features.vq > 0)
+ expedited_registers.push_back ("vg");
- static const char *expedite_regs_aarch64[] = { "x29", "sp", "pc", NULL };
- static const char *expedite_regs_aarch64_sve[] = { "x29", "sp", "pc",
- "vg", NULL };
+ expedited_registers.push_back (nullptr);
- if (features.vq == 0)
- init_target_desc (tdesc, expedite_regs_aarch64);
- else
- init_target_desc (tdesc, expedite_regs_aarch64_sve);
+ init_target_desc (tdesc, (const char **) expedited_registers.data ());
tdesc_aarch64_map[features] = tdesc;
}
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 07/17] [gdbserver/aarch64] sme: Add support for SME
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (5 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 06/17] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 08/17] [gdb/aarch64] sve: Fix signal frame z/v register restore Luis Machado
` (10 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
Enable SME support in gdbserver by adjusting the usual fields. There is
not much to this patch because the code is either in gdb or it is shared
between gdbserver and gdb. One exception is the bump to gdbserver's
PBUFSIZ from 18432 to 131104.
Since the ZA register can be quite big (256 * 256 bytes), the g/G remote
packet will also become quite big
From gdbserver/tdesc.cc:init_target_desc, I estimated the new size should
be at least (2 * 256 * 256 + 32), which yields 131104.
It is also unlikely we will find a process starting up with SVL set to 256.
Ideally we'd adjust the packet size dynamically based on what we need, but
for now this should do.
Please note we have the same limitation for SME that we have for SVE, and
that is the fact gdbserver cannot communicate vector length changes to gdb
via the remote protocol.
Thiago is working on this improvement, which hopefully will be able to be
adapted to SME in an easy way.
Co-Authored-By: Ezra Sitorus <ezra.sitorus@arm.com>
---
gdbserver/linux-aarch64-low.cc | 74 ++++++++++++++++++++++++++++++++
gdbserver/linux-aarch64-tdesc.cc | 7 +++
gdbserver/server.h | 2 +-
3 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc
index af2e0fd9c10..93f5f4bb499 100644
--- a/gdbserver/linux-aarch64-low.cc
+++ b/gdbserver/linux-aarch64-low.cc
@@ -41,6 +41,7 @@
#include "gdb_proc_service.h"
#include "arch/aarch64.h"
#include "arch/aarch64-mte-linux.h"
+#include "arch/aarch64-scalable-linux.h"
#include "linux-aarch32-tdesc.h"
#include "linux-aarch64-tdesc.h"
#include "nat/aarch64-mte-linux-ptrace.h"
@@ -750,6 +751,66 @@ aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf)
memcpy (buf, sve_state.data (), sve_state.size ());
}
+/* Wrapper for aarch64_za_regs_copy_to_reg_buf, to help copying NT_ARM_ZA
+ state from the thread (BUF) to the register cache. */
+
+static void
+aarch64_za_regs_copy_to_regcache (struct regcache *regcache,
+ ATTRIBUTE_UNUSED const void *buf)
+{
+ /* BUF is unused here since we collect the data straight from a ptrace
+ request, therefore bypassing gdbserver's own call to ptrace. */
+ int tid = lwpid_of (current_thread);
+
+ gdb::optional<int> za_regnum
+ = find_regno_no_throw (regcache->tdesc, "za");
+ gdb::optional<int> svg_regnum
+ = find_regno_no_throw (regcache->tdesc, "svg");
+ gdb::optional<int> svcr_regnum
+ = find_regno_no_throw (regcache->tdesc, "svcr");
+
+ gdb_assert (za_regnum.has_value ());
+ gdb_assert (svg_regnum.has_value ());
+ gdb_assert (svcr_regnum.has_value ());
+
+ /* Update the register cache. aarch64_za_regs_copy_to_reg_buf handles
+ fetching the NT_ARM_ZA state from thread TID. */
+ aarch64_za_regs_copy_to_reg_buf (tid, regcache, *za_regnum, *svg_regnum,
+ *svcr_regnum);
+}
+
+/* Wrapper for aarch64_za_regs_copy_from_reg_buf, to help copying NT_ARM_ZA
+ state from the register cache to the thread (BUF). */
+
+static void
+aarch64_za_regs_copy_from_regcache (struct regcache *regcache, void *buf)
+{
+ int tid = lwpid_of (current_thread);
+
+ gdb::optional<int> za_regnum
+ = find_regno_no_throw (regcache->tdesc, "za");
+ gdb::optional<int> svg_regnum
+ = find_regno_no_throw (regcache->tdesc, "svg");
+ gdb::optional<int> svcr_regnum
+ = find_regno_no_throw (regcache->tdesc, "svcr");
+
+ gdb_assert (za_regnum.has_value ());
+ gdb_assert (svg_regnum.has_value ());
+ gdb_assert (svcr_regnum.has_value ());
+
+ /* Update the thread NT_ARM_ZA state. aarch64_za_regs_copy_from_reg_buf
+ handles writing the ZA state back to thread TID. */
+ aarch64_za_regs_copy_from_reg_buf (tid, regcache, *za_regnum, *svg_regnum,
+ *svcr_regnum);
+
+ /* We need to return the expected data in BUF, so copy whatever the kernel
+ already has to BUF. */
+
+ /* Obtain a dump of ZA from ptrace. */
+ gdb::byte_vector za_state = aarch64_fetch_za_regset (tid);
+ memcpy (buf, za_state.data (), za_state.size ());
+}
+
/* Array containing all the possible register sets for AArch64/Linux. During
architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
validity and enabled/disabled accordingly.
@@ -772,6 +833,11 @@ static struct regset_info aarch64_regsets[] =
0, EXTENDED_REGS,
aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
},
+ /* Scalable Matrix Extension (SME) ZA register. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_ZA,
+ 0, EXTENDED_REGS,
+ aarch64_za_regs_copy_from_regcache, aarch64_za_regs_copy_to_regcache
+ },
/* PAC registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
0, OPTIONAL_REGS,
@@ -839,6 +905,10 @@ aarch64_adjust_register_sets (const struct aarch64_features &features)
if (features.tls > 0)
regset->size = AARCH64_TLS_REGISTER_SIZE * features.tls;
break;
+ case NT_ARM_ZA:
+ if (features.svq > 0)
+ regset->size = ZA_PT_SIZE (features.svq);
+ break;
default:
gdb_assert_not_reached ("Unknown register set found.");
}
@@ -873,6 +943,10 @@ aarch64_target::low_arch_setup ()
features.mte = linux_get_hwcap2 (pid, 8) & HWCAP2_MTE;
features.tls = aarch64_tls_register_count (tid);
+ /* Scalable Matrix Extension feature and size check. */
+ if (linux_get_hwcap2 (pid, 8) & HWCAP2_SME)
+ features.svq = aarch64_za_get_svq (tid);
+
current_process ()->tdesc = aarch64_linux_read_description (features);
/* Adjust the register sets we should use for this particular set of
diff --git a/gdbserver/linux-aarch64-tdesc.cc b/gdbserver/linux-aarch64-tdesc.cc
index 3c60e1a4db0..b6b622ba4f2 100644
--- a/gdbserver/linux-aarch64-tdesc.cc
+++ b/gdbserver/linux-aarch64-tdesc.cc
@@ -41,6 +41,11 @@ aarch64_linux_read_description (const aarch64_features &features)
error (_("VQ is %" PRIu64 ", maximum supported value is %d"), features.vq,
AARCH64_MAX_SVE_VQ);
+ if (features.svq > AARCH64_MAX_SVE_VQ)
+ error (_("Streaming svq is %" PRIu8 ", maximum supported value is %d"),
+ features.svq,
+ AARCH64_MAX_SVE_VQ);
+
struct target_desc *tdesc = tdesc_aarch64_map[features];
if (tdesc == NULL)
@@ -56,6 +61,8 @@ aarch64_linux_read_description (const aarch64_features &features)
if (features.vq > 0)
expedited_registers.push_back ("vg");
+ if (features.svq > 0)
+ expedited_registers.push_back ("svg");
expedited_registers.push_back (nullptr);
diff --git a/gdbserver/server.h b/gdbserver/server.h
index 730ec146530..dc8e04413f1 100644
--- a/gdbserver/server.h
+++ b/gdbserver/server.h
@@ -104,7 +104,7 @@ extern int in_queued_stop_replies (ptid_t ptid);
/* Buffer sizes for transferring memory, registers, etc. Set to a constant
value to accomodate multiple register formats. This value must be at least
as large as the largest register set supported by gdbserver. */
-#define PBUFSIZ 18432
+#define PBUFSIZ 131104
/* Definition for an unknown syscall, used basically in error-cases. */
#define UNKNOWN_SYSCALL (-1)
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 08/17] [gdb/aarch64] sve: Fix signal frame z/v register restore
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (6 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 07/17] [gdbserver/aarch64] sme: Add support for SME Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 09/17] [gdb/aarch64] sme: Signal frame support Luis Machado
` (9 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
While doing some SME work, I ran into the situation where the Z register
contents restored from a signal frame are incorrect if the signal frame
only contains fpsimd state and no sve state.
This happens because we only restore the v register values in that case,
and don't do anything for the z registers.
Fix this by initializing the z registers to 0 and then copying over the
overlapping part of the v registers to the z registers.
While at it, refactor the code a bit to simplify it and make it smaller.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-tdep.c | 108 +++++++++++++++++++++++----------------
1 file changed, 63 insertions(+), 45 deletions(-)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index b183a3c9a38..eecf5bf13bd 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -196,14 +196,13 @@ read_aarch64_ctx (CORE_ADDR ctx_addr, enum bfd_endian byte_order,
/* Given CACHE, use the trad_frame* functions to restore the FPSIMD
registers from a signal frame.
- VREG_NUM is the number of the V register being restored, OFFSET is the
- address containing the register value, BYTE_ORDER is the endianness and
- HAS_SVE tells us if we have a valid SVE context or not. */
+ FPSIMD_CONTEXT is the address of the signal frame context containing FPSIMD
+ data. */
static void
-aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs,
- int vreg_num, CORE_ADDR offset,
- enum bfd_endian byte_order, bool has_sve)
+aarch64_linux_restore_vregs (struct gdbarch *gdbarch,
+ struct trad_frame_cache *cache,
+ CORE_ADDR fpsimd_context)
{
/* WARNING: SIMD state is laid out in memory in target-endian format.
@@ -215,11 +214,22 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs,
2 - If the target is little endian, then SIMD state is little endian, so
no byteswap is needed. */
- if (byte_order == BFD_ENDIAN_BIG)
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ int num_regs = gdbarch_num_regs (gdbarch);
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ for (int i = 0; i < 32; i++)
{
+ CORE_ADDR offset = (fpsimd_context + AARCH64_FPSIMD_V0_OFFSET
+ + (i * AARCH64_FPSIMD_VREG_SIZE));
+
gdb_byte buf[V_REGISTER_SIZE];
- if (target_read_memory (offset, buf, V_REGISTER_SIZE) != 0)
+ /* Read the contents of the V register. */
+ if (target_read_memory (offset, buf, V_REGISTER_SIZE))
+ error (_("Failed to read fpsimd register from signal context."));
+
+ if (byte_order == BFD_ENDIAN_BIG)
{
size_t size = V_REGISTER_SIZE/2;
@@ -234,50 +244,67 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs,
store_unsigned_integer (buf + size , size, BFD_ENDIAN_LITTLE, u64);
/* Now we can store the correct bytes for the V register. */
- trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + vreg_num,
+ trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + i,
{buf, V_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_Q0_REGNUM
- + vreg_num, {buf, Q_REGISTER_SIZE});
+ + i, {buf, Q_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_D0_REGNUM
- + vreg_num, {buf, D_REGISTER_SIZE});
+ + i, {buf, D_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_S0_REGNUM
- + vreg_num, {buf, S_REGISTER_SIZE});
+ + i, {buf, S_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_H0_REGNUM
- + vreg_num, {buf, H_REGISTER_SIZE});
+ + i, {buf, H_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_B0_REGNUM
- + vreg_num, {buf, B_REGISTER_SIZE});
+ + i, {buf, B_REGISTER_SIZE});
- if (has_sve)
+ if (tdep->has_sve ())
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_SVE_V0_REGNUM
- + vreg_num, {buf, V_REGISTER_SIZE});
+ + i, {buf, V_REGISTER_SIZE});
}
- return;
- }
+ else
+ {
+ /* Little endian, just point at the address containing the register
+ value. */
+ trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + i, offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + i,
+ offset);
- /* Little endian, just point at the address containing the register
- value. */
- trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + vreg_num, offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + vreg_num,
- offset);
-
- if (has_sve)
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM
- + vreg_num, offset);
+ if (tdep->has_sve ())
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM
+ + i, offset);
+ }
+ if (tdep->has_sve ())
+ {
+ /* If SVE is supported for this target, zero out the Z
+ registers then copy the first 16 bytes of each of the V
+ registers to the associated Z register. Otherwise the Z
+ registers will contain uninitialized data. */
+ std::vector<gdb_byte> z_buffer (tdep->vq * 16);
+
+ /* We have already handled the endianness swap above, so we don't need
+ to worry about it here. */
+ memcpy (z_buffer.data (), buf, V_REGISTER_SIZE);
+ trad_frame_set_reg_value_bytes (cache,
+ AARCH64_SVE_Z0_REGNUM + i,
+ {z_buffer.data (),
+ z_buffer.size ()});
+ }
+ }
}
/* Implement the "init" method of struct tramp_frame. */
@@ -432,16 +459,7 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
/* If there was no SVE section then set up the V registers. */
if (sve_regs == 0)
- {
- for (int i = 0; i < 32; i++)
- {
- CORE_ADDR offset = (fpsimd + AARCH64_FPSIMD_V0_OFFSET
- + (i * AARCH64_FPSIMD_VREG_SIZE));
-
- aarch64_linux_restore_vreg (this_cache, num_regs, i, offset,
- byte_order, tdep->has_sve ());
- }
- }
+ aarch64_linux_restore_vregs (gdbarch, this_cache, fpsimd);
}
trad_frame_set_id (this_cache, frame_id_build (sp, func));
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 09/17] [gdb/aarch64] sme: Signal frame support
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (7 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 08/17] [gdb/aarch64] sve: Fix signal frame z/v register restore Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 10/17] [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes Luis Machado
` (8 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
Teach gdb about the ZA/SSVE state on signal frames and how to restore
the contents of the registers.
There is a new ZA_MAGIC context that the Linux Kernel uses to communicate
the ZA register state to gdb.
The SVE_MAGIC context has also been adjusted to contain a flag indicating
whether it is a SVE or SSVE state.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-tdep.c | 88 +++++++++++++++++++--
gdb/nat/aarch64-scalable-linux-sigcontext.h | 5 +-
2 files changed, 84 insertions(+), 9 deletions(-)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index eecf5bf13bd..1e12a8f0279 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -48,6 +48,7 @@
#include "linux-record.h"
#include "arch/aarch64-mte-linux.h"
+#include "arch/aarch64-scalable-linux.h"
#include "arch-utils.h"
#include "value.h"
@@ -152,6 +153,7 @@
#define AARCH64_EXTRA_MAGIC 0x45585401
#define AARCH64_FPSIMD_MAGIC 0x46508001
#define AARCH64_SVE_MAGIC 0x53564501
+#define AARCH64_ZA_MAGIC 0x54366345
/* Defines for the extra_context that follows an AARCH64_EXTRA_MAGIC. */
#define AARCH64_EXTRA_DATAP_OFFSET 8
@@ -164,13 +166,23 @@
/* Defines for the sve structure that follows an AARCH64_SVE_MAGIC. */
#define AARCH64_SVE_CONTEXT_VL_OFFSET 8
+#define AARCH64_SVE_CONTEXT_FLAGS_OFFSET 10
#define AARCH64_SVE_CONTEXT_REGS_OFFSET 16
#define AARCH64_SVE_CONTEXT_P_REGS_OFFSET(vq) (32 * vq * 16)
#define AARCH64_SVE_CONTEXT_FFR_OFFSET(vq) \
(AARCH64_SVE_CONTEXT_P_REGS_OFFSET (vq) + (16 * vq * 2))
#define AARCH64_SVE_CONTEXT_SIZE(vq) \
(AARCH64_SVE_CONTEXT_FFR_OFFSET (vq) + (vq * 2))
+/* Flag indicating the SVE Context describes streaming mode. */
+#define SVE_SIG_FLAG_SM 0x1
+/* SME constants. */
+#define AARCH64_SME_CONTEXT_SVL_OFFSET 8
+#define AARCH64_SME_CONTEXT_REGS_OFFSET 16
+#define AARCH64_SME_CONTEXT_ZA_SIZE(svq) \
+ ((sve_vl_from_vq (svq) * sve_vl_from_vq (svq)))
+#define AARCH64_SME_CONTEXT_SIZE(svq) \
+ (AARCH64_SME_CONTEXT_REGS_OFFSET + AARCH64_SME_CONTEXT_ZA_SIZE (svq))
/* Read an aarch64_ctx, returning the magic value, and setting *SIZE to the
size, or return 0 on error. */
@@ -325,7 +337,10 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
CORE_ADDR section_end = section + AARCH64_SIGCONTEXT_RESERVED_SIZE;
CORE_ADDR fpsimd = 0;
CORE_ADDR sve_regs = 0;
+ CORE_ADDR za_state = 0;
+ uint64_t svcr = 0;
uint32_t size, magic;
+ size_t vq = 0, svq = 0;
bool extra_found = false;
int num_regs = gdbarch_num_regs (gdbarch);
@@ -361,7 +376,7 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
/* Check if the section is followed by a full SVE dump, and set
sve_regs if it is. */
gdb_byte buf[4];
- uint16_t vq;
+ uint16_t flags;
if (!tdep->has_sve ())
break;
@@ -374,9 +389,23 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
}
vq = sve_vq_from_vl (extract_unsigned_integer (buf, 2, byte_order));
- if (vq != tdep->vq)
- error (_("Invalid vector length in signal frame %d vs %s."), vq,
- pulongest (tdep->vq));
+ /* If SME is supported, also read the flags field. It may
+ indicate if this SVE context is for streaming mode (SSVE). */
+ if (tdep->has_sme ())
+ {
+ if (target_read_memory (section
+ + AARCH64_SVE_CONTEXT_FLAGS_OFFSET,
+ buf, 2) != 0)
+ {
+ section += size;
+ break;
+ }
+ flags = extract_unsigned_integer (buf, 2, byte_order);
+
+ /* Is this SSVE data? If so, enable the SM bit in SVCR. */
+ if (flags & SVE_SIG_FLAG_SM)
+ svcr |= SVCR_SM_BIT;
+ }
if (size >= AARCH64_SVE_CONTEXT_SIZE (vq))
sve_regs = section + AARCH64_SVE_CONTEXT_REGS_OFFSET;
@@ -385,6 +414,38 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
break;
}
+ case AARCH64_ZA_MAGIC:
+ {
+ if (!tdep->has_sme ())
+ {
+ section += size;
+ break;
+ }
+
+ /* Check if the section is followed by a full ZA dump, and set
+ za_state if it is. */
+ gdb_byte buf[2];
+
+ if (target_read_memory (section + AARCH64_SVE_CONTEXT_VL_OFFSET,
+ buf, 2) != 0)
+ {
+ section += size;
+ break;
+ }
+ svq = sve_vq_from_vl (extract_unsigned_integer (buf, 2,
+ byte_order));
+
+ if (size >= AARCH64_SME_CONTEXT_SIZE (svq))
+ {
+ za_state = section + AARCH64_SME_CONTEXT_REGS_OFFSET;
+ /* We have ZA data. Enable the ZA bit in SVCR. */
+ svcr |= SVCR_ZA_BIT;
+ }
+
+ section += size;
+ break;
+ }
+
case AARCH64_EXTRA_MAGIC:
{
/* Extra is always the last valid section in reserved and points to
@@ -423,7 +484,7 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
for (int i = 0; i < 32; i++)
{
- offset = sve_regs + (i * tdep->vq * 16);
+ offset = sve_regs + (i * vq * 16);
trad_frame_set_reg_addr (this_cache, AARCH64_SVE_Z0_REGNUM + i,
offset);
trad_frame_set_reg_addr (this_cache,
@@ -441,12 +502,12 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
offset);
}
- offset = sve_regs + AARCH64_SVE_CONTEXT_P_REGS_OFFSET (tdep->vq);
+ offset = sve_regs + AARCH64_SVE_CONTEXT_P_REGS_OFFSET (vq);
for (int i = 0; i < 16; i++)
trad_frame_set_reg_addr (this_cache, AARCH64_SVE_P0_REGNUM + i,
- offset + (i * tdep->vq * 2));
+ offset + (i * vq * 2));
- offset = sve_regs + AARCH64_SVE_CONTEXT_FFR_OFFSET (tdep->vq);
+ offset = sve_regs + AARCH64_SVE_CONTEXT_FFR_OFFSET (vq);
trad_frame_set_reg_addr (this_cache, AARCH64_SVE_FFR_REGNUM, offset);
}
@@ -462,6 +523,17 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
aarch64_linux_restore_vregs (gdbarch, this_cache, fpsimd);
}
+ if (za_state != 0)
+ {
+ /* Restore the ZA state. */
+ trad_frame_set_reg_addr (this_cache, tdep->sme_za_regnum,
+ za_state);
+ }
+
+ /* If SME is supported, set SVCR as well. */
+ if (tdep->has_sme ())
+ trad_frame_set_reg_value (this_cache, tdep->sme_svcr_regnum, svcr);
+
trad_frame_set_id (this_cache, frame_id_build (sp, func));
}
diff --git a/gdb/nat/aarch64-scalable-linux-sigcontext.h b/gdb/nat/aarch64-scalable-linux-sigcontext.h
index 74407bd266a..18623443744 100644
--- a/gdb/nat/aarch64-scalable-linux-sigcontext.h
+++ b/gdb/nat/aarch64-scalable-linux-sigcontext.h
@@ -30,7 +30,10 @@
struct sve_context {
struct _aarch64_ctx head;
__u16 vl;
- __u16 __reserved[3];
+ /* Holds flags. This field was defined for SME support. Prior to it,
+ this used to be a reserved 16-bit value. */
+ __u16 flags;
+ __u16 __reserved[2];
};
/*
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 10/17] [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (8 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 09/17] [gdb/aarch64] sme: Signal frame support Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 11/17] [gdb/aarch64] sme: Support TPIDR2 signal frame context Luis Machado
` (7 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
With SME, where you have two different vector lengths (vl and svl), it may be
the case that the current frame has a set of vector lengths (A) but the signal
context has a distinct set of vector lengths (B).
In this case, we may run into a situation where GDB attempts to use a gdbarch
created for set A, but it is really dealing with a frame that was using set
B.
This is problematic, specially with SME, because now we have a different
number of pseudo-registers and types that gets cached on creation of each
gdbarch variation.
For AArch64 we really need to be able to use the correct gdbarch for each
frame, and I noticed the signal frame (tramp-frame) doesn't have a settable
prev_arch field. So it ends up using the default frame_unwind_arch function
and eventually calling get_frame_arch (next_frame). That means the previous
frame will always have the same gdbarch as the current frame.
This patch first refactors the AArch64/Linux signal context code, simplifying
it and making it reusable for our purposes of calculating the previous frame's
gdbarch.
I introduced a struct that holds information that we have found in the signal
context, and with which we can make various decisions.
Finally, a small change to tramp-frame.c and tramp-frame.h to expose a
prev_arch hook that the architecture can set.
With this new field, AArch64/Linux can implement a hook that looks at the
signal context and infers the gdbarch for the previous frame.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-tdep.c | 279 +++++++++++++++++++++++++++------------
gdb/tramp-frame.c | 1 +
gdb/tramp-frame.h | 12 ++
3 files changed, 206 insertions(+), 86 deletions(-)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index 1e12a8f0279..c973a790f62 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -184,6 +184,39 @@
#define AARCH64_SME_CONTEXT_SIZE(svq) \
(AARCH64_SME_CONTEXT_REGS_OFFSET + AARCH64_SME_CONTEXT_ZA_SIZE (svq))
+/* Holds information about the signal frame. */
+struct aarch64_linux_sigframe
+{
+ /* The stack pointer value. */
+ CORE_ADDR sp = 0;
+ /* The sigcontext address. */
+ CORE_ADDR sigcontext_address = 0;
+ /* The start/end signal frame section addresses. */
+ CORE_ADDR section = 0;
+ CORE_ADDR section_end = 0;
+
+ /* Starting address of the section containing the general purpose
+ registers. */
+ CORE_ADDR gpr_section = 0;
+ /* Starting address of the section containing the FPSIMD registers. */
+ CORE_ADDR fpsimd_section = 0;
+ /* Starting address of the section containing the SVE registers. */
+ CORE_ADDR sve_section = 0;
+ /* Starting address of the section containing the ZA register. */
+ CORE_ADDR za_section = 0;
+ /* Starting address of the section containing extra information. */
+ CORE_ADDR extra_section = 0;
+
+ /* The vector length (SVE or SSVE). */
+ ULONGEST vl = 0;
+ /* The streaming vector length (SSVE/ZA). */
+ ULONGEST svl = 0;
+ /* True if we are in streaming mode, false otherwise. */
+ bool streaming_mode = false;
+ /* True if we have a ZA payload, false otherwise. */
+ bool za_payload = false;
+};
+
/* Read an aarch64_ctx, returning the magic value, and setting *SIZE to the
size, or return 0 on error. */
@@ -319,129 +352,115 @@ aarch64_linux_restore_vregs (struct gdbarch *gdbarch,
}
}
-/* Implement the "init" method of struct tramp_frame. */
+/* Given a signal frame THIS_FRAME, read the signal frame information into
+ SIGNAL_FRAME. */
static void
-aarch64_linux_sigframe_init (const struct tramp_frame *self,
- frame_info_ptr this_frame,
- struct trad_frame_cache *this_cache,
- CORE_ADDR func)
+aarch64_linux_read_signal_frame_info (frame_info_ptr this_frame,
+ struct aarch64_linux_sigframe &signal_frame)
{
- struct gdbarch *gdbarch = get_frame_arch (this_frame);
- enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
- CORE_ADDR sp = get_frame_register_unsigned (this_frame, AARCH64_SP_REGNUM);
- CORE_ADDR sigcontext_addr = (sp + AARCH64_RT_SIGFRAME_UCONTEXT_OFFSET
- + AARCH64_UCONTEXT_SIGCONTEXT_OFFSET );
- CORE_ADDR section = sigcontext_addr + AARCH64_SIGCONTEXT_RESERVED_OFFSET;
- CORE_ADDR section_end = section + AARCH64_SIGCONTEXT_RESERVED_SIZE;
- CORE_ADDR fpsimd = 0;
- CORE_ADDR sve_regs = 0;
- CORE_ADDR za_state = 0;
- uint64_t svcr = 0;
+ signal_frame.sp = get_frame_register_unsigned (this_frame, AARCH64_SP_REGNUM);
+ signal_frame.sigcontext_address
+ = signal_frame.sp + AARCH64_RT_SIGFRAME_UCONTEXT_OFFSET
+ + AARCH64_UCONTEXT_SIGCONTEXT_OFFSET;
+ signal_frame.section
+ = signal_frame.sigcontext_address + AARCH64_SIGCONTEXT_RESERVED_OFFSET;
+ signal_frame.section_end
+ = signal_frame.section + AARCH64_SIGCONTEXT_RESERVED_SIZE;
+
+ signal_frame.gpr_section
+ = signal_frame.sigcontext_address + AARCH64_SIGCONTEXT_XO_OFFSET;
+
+ /* Search for all the other sections, stopping at null. */
+ CORE_ADDR section = signal_frame.section;
+ CORE_ADDR section_end = signal_frame.section_end;
uint32_t size, magic;
- size_t vq = 0, svq = 0;
bool extra_found = false;
- int num_regs = gdbarch_num_regs (gdbarch);
-
- /* Read in the integer registers. */
+ enum bfd_endian byte_order
+ = gdbarch_byte_order (get_frame_arch (this_frame));
- for (int i = 0; i < 31; i++)
- {
- trad_frame_set_reg_addr (this_cache,
- AARCH64_X0_REGNUM + i,
- sigcontext_addr + AARCH64_SIGCONTEXT_XO_OFFSET
- + i * AARCH64_SIGCONTEXT_REG_SIZE);
- }
- trad_frame_set_reg_addr (this_cache, AARCH64_SP_REGNUM,
- sigcontext_addr + AARCH64_SIGCONTEXT_XO_OFFSET
- + 31 * AARCH64_SIGCONTEXT_REG_SIZE);
- trad_frame_set_reg_addr (this_cache, AARCH64_PC_REGNUM,
- sigcontext_addr + AARCH64_SIGCONTEXT_XO_OFFSET
- + 32 * AARCH64_SIGCONTEXT_REG_SIZE);
-
- /* Search for the FP and SVE sections, stopping at null. */
while ((magic = read_aarch64_ctx (section, byte_order, &size)) != 0
&& size != 0)
{
switch (magic)
{
case AARCH64_FPSIMD_MAGIC:
- fpsimd = section;
- section += size;
- break;
+ {
+ signal_frame.fpsimd_section = section;
+ section += size;
+ break;
+ }
case AARCH64_SVE_MAGIC:
{
/* Check if the section is followed by a full SVE dump, and set
sve_regs if it is. */
gdb_byte buf[4];
- uint16_t flags;
-
- if (!tdep->has_sve ())
- break;
+ /* Extract the vector length. */
if (target_read_memory (section + AARCH64_SVE_CONTEXT_VL_OFFSET,
buf, 2) != 0)
{
+ warning (_("Failed to read the vector length from the SVE "
+ " signal frame context."));
section += size;
break;
}
- vq = sve_vq_from_vl (extract_unsigned_integer (buf, 2, byte_order));
- /* If SME is supported, also read the flags field. It may
- indicate if this SVE context is for streaming mode (SSVE). */
- if (tdep->has_sme ())
+ signal_frame.vl = extract_unsigned_integer (buf, 2, byte_order);
+
+ /* Extract the flags to check if we are in streaming mode. */
+ if (target_read_memory (section
+ + AARCH64_SVE_CONTEXT_FLAGS_OFFSET,
+ buf, 2) != 0)
{
- if (target_read_memory (section
- + AARCH64_SVE_CONTEXT_FLAGS_OFFSET,
- buf, 2) != 0)
- {
- section += size;
- break;
- }
- flags = extract_unsigned_integer (buf, 2, byte_order);
-
- /* Is this SSVE data? If so, enable the SM bit in SVCR. */
- if (flags & SVE_SIG_FLAG_SM)
- svcr |= SVCR_SM_BIT;
+ warning (_("Failed to read the flags from the SVE signal frame"
+ " context."));
+ section += size;
+ break;
}
- if (size >= AARCH64_SVE_CONTEXT_SIZE (vq))
- sve_regs = section + AARCH64_SVE_CONTEXT_REGS_OFFSET;
+ uint16_t flags = extract_unsigned_integer (buf, 2, byte_order);
+ /* Is this SSVE data? If so, we are in streaming mode. */
+ signal_frame.streaming_mode
+ = (flags & SVE_SIG_FLAG_SM) ? true : false;
+
+ ULONGEST vq = sve_vq_from_vl (signal_frame.vl);
+ if (size >= AARCH64_SVE_CONTEXT_SIZE (vq))
+ {
+ signal_frame.sve_section
+ = section + AARCH64_SVE_CONTEXT_REGS_OFFSET;
+ }
section += size;
break;
}
case AARCH64_ZA_MAGIC:
{
- if (!tdep->has_sme ())
- {
- section += size;
- break;
- }
-
/* Check if the section is followed by a full ZA dump, and set
za_state if it is. */
gdb_byte buf[2];
+ /* Extract the streaming vector length. */
if (target_read_memory (section + AARCH64_SVE_CONTEXT_VL_OFFSET,
buf, 2) != 0)
{
+ warning (_("Failed to read the streaming vector length from "
+ " ZA signal frame context."));
section += size;
break;
}
- svq = sve_vq_from_vl (extract_unsigned_integer (buf, 2,
- byte_order));
+
+ signal_frame.svl = extract_unsigned_integer (buf, 2, byte_order);
+ ULONGEST svq = sve_vq_from_vl (signal_frame.svl);
if (size >= AARCH64_SME_CONTEXT_SIZE (svq))
{
- za_state = section + AARCH64_SME_CONTEXT_REGS_OFFSET;
- /* We have ZA data. Enable the ZA bit in SVCR. */
- svcr |= SVCR_ZA_BIT;
+ signal_frame.za_section
+ = section + AARCH64_SME_CONTEXT_REGS_OFFSET;
+ signal_frame.za_payload = true;
}
-
section += size;
break;
}
@@ -457,11 +476,14 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
if (target_read_memory (section + AARCH64_EXTRA_DATAP_OFFSET,
buf, 8) != 0)
{
+ warning (_("Failed to read the extra section address from the"
+ " signal frame context."));
section += size;
break;
}
section = extract_unsigned_integer (buf, 8, byte_order);
+ signal_frame.extra_section = section;
extra_found = true;
break;
}
@@ -477,11 +499,49 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
if (!extra_found && section > section_end)
break;
}
+}
+
+/* Implement the "init" method of struct tramp_frame. */
+
+static void
+aarch64_linux_sigframe_init (const struct tramp_frame *self,
+ frame_info_ptr this_frame,
+ struct trad_frame_cache *this_cache,
+ CORE_ADDR func)
+{
+ /* Read the signal context information. */
+ struct aarch64_linux_sigframe signal_frame;
+ aarch64_linux_read_signal_frame_info (this_frame, signal_frame);
+
+ /* Now we have all the data required to restore the registers from the
+ signal frame. */
+
+ /* Restore the general purpose registers. */
+ CORE_ADDR offset
+ = signal_frame.sigcontext_address + AARCH64_SIGCONTEXT_XO_OFFSET;
+ for (int i = 0; i < 31; i++)
+ {
+ trad_frame_set_reg_addr (this_cache, AARCH64_X0_REGNUM + i, offset);
+ offset += AARCH64_SIGCONTEXT_REG_SIZE;
+ }
+ trad_frame_set_reg_addr (this_cache, AARCH64_SP_REGNUM, offset);
+ offset += AARCH64_SIGCONTEXT_REG_SIZE;
+ trad_frame_set_reg_addr (this_cache, AARCH64_PC_REGNUM, offset);
- if (sve_regs != 0)
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ /* Restore the SVE / FPSIMD registers. */
+ if (tdep->has_sve () && signal_frame.sve_section != 0)
{
- CORE_ADDR offset;
+ ULONGEST vq = sve_vq_from_vl (signal_frame.vl);
+ CORE_ADDR sve_regs = signal_frame.sve_section;
+
+ /* Restore VG. */
+ trad_frame_set_reg_value (this_cache, AARCH64_SVE_VG_REGNUM,
+ sve_vg_from_vl (signal_frame.vl));
+ int num_regs = gdbarch_num_regs (gdbarch);
for (int i = 0; i < 32; i++)
{
offset = sve_regs + (i * vq * 16);
@@ -511,30 +571,75 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
trad_frame_set_reg_addr (this_cache, AARCH64_SVE_FFR_REGNUM, offset);
}
- if (fpsimd != 0)
+ /* Restore the FPSIMD registers. */
+ if (signal_frame.fpsimd_section != 0)
{
+ CORE_ADDR fpsimd = signal_frame.fpsimd_section;
+
trad_frame_set_reg_addr (this_cache, AARCH64_FPSR_REGNUM,
fpsimd + AARCH64_FPSIMD_FPSR_OFFSET);
trad_frame_set_reg_addr (this_cache, AARCH64_FPCR_REGNUM,
fpsimd + AARCH64_FPSIMD_FPCR_OFFSET);
/* If there was no SVE section then set up the V registers. */
- if (sve_regs == 0)
+ if (!tdep->has_sve () || signal_frame.sve_section == 0)
aarch64_linux_restore_vregs (gdbarch, this_cache, fpsimd);
}
- if (za_state != 0)
+ /* Restore the SME registers. */
+ if (tdep->has_sme ())
{
- /* Restore the ZA state. */
- trad_frame_set_reg_addr (this_cache, tdep->sme_za_regnum,
- za_state);
+ if (signal_frame.za_section != 0)
+ {
+ /* Restore the ZA state. */
+ trad_frame_set_reg_addr (this_cache, tdep->sme_za_regnum,
+ signal_frame.za_section);
+ }
+
+ /* Restore/Reconstruct SVCR. */
+ ULONGEST svcr = 0;
+ svcr |= signal_frame.za_payload ? SVCR_ZA_BIT : 0;
+ svcr |= signal_frame.streaming_mode ? SVCR_SM_BIT : 0;
+ trad_frame_set_reg_value (this_cache, tdep->sme_svcr_regnum, svcr);
+
+ /* Restore SVG. */
+ trad_frame_set_reg_value (this_cache, tdep->sme_svg_regnum,
+ sve_vg_from_vl (signal_frame.svl));
}
- /* If SME is supported, set SVCR as well. */
- if (tdep->has_sme ())
- trad_frame_set_reg_value (this_cache, tdep->sme_svcr_regnum, svcr);
+ trad_frame_set_id (this_cache, frame_id_build (signal_frame.sp, func));
+}
- trad_frame_set_id (this_cache, frame_id_build (sp, func));
+/* Implements the "prev_arch" method of struct tramp_frame. */
+
+static struct gdbarch *
+aarch64_linux_sigframe_prev_arch (frame_info_ptr this_frame,
+ void **frame_cache)
+{
+ struct trad_frame_cache *cache
+ = (struct trad_frame_cache *) *frame_cache;
+
+ gdb_assert (cache != nullptr);
+
+ struct aarch64_linux_sigframe signal_frame;
+ aarch64_linux_read_signal_frame_info (this_frame, signal_frame);
+
+ /* The SVE vector length and the SME vector length may change from frame to
+ frame. Make sure we report the correct architecture to the previous
+ frame.
+
+ We can reuse the next frame's architecture here, as it should be mostly
+ the same, except for potential different vg and svg values. */
+ const struct target_desc *tdesc
+ = gdbarch_target_desc (get_frame_arch (this_frame));
+ aarch64_features features = aarch64_features_from_target_desc (tdesc);
+ features.vq = sve_vq_from_vl (signal_frame.vl);
+ features.svq = (uint8_t) sve_vq_from_vl (signal_frame.svl);
+
+ struct gdbarch_info info;
+ info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
+ info.target_desc = aarch64_read_description (features);
+ return gdbarch_find_by_info (info);
}
static const struct tramp_frame aarch64_linux_rt_sigframe =
@@ -551,7 +656,9 @@ static const struct tramp_frame aarch64_linux_rt_sigframe =
{0xd4000001, ULONGEST_MAX},
{TRAMP_SENTINEL_INSN, ULONGEST_MAX}
},
- aarch64_linux_sigframe_init
+ aarch64_linux_sigframe_init,
+ nullptr, /* validate */
+ aarch64_linux_sigframe_prev_arch, /* prev_arch */
};
/* Register maps. */
diff --git a/gdb/tramp-frame.c b/gdb/tramp-frame.c
index c69ee6efc2c..94e42e9fec1 100644
--- a/gdb/tramp-frame.c
+++ b/gdb/tramp-frame.c
@@ -170,5 +170,6 @@ tramp_frame_prepend_unwinder (struct gdbarch *gdbarch,
unwinder->stop_reason = default_frame_unwind_stop_reason;
unwinder->this_id = tramp_frame_this_id;
unwinder->prev_register = tramp_frame_prev_register;
+ unwinder->prev_arch = tramp_frame->prev_arch;
frame_unwind_prepend_unwinder (gdbarch, unwinder);
}
diff --git a/gdb/tramp-frame.h b/gdb/tramp-frame.h
index fa0241acb2d..563c34ae595 100644
--- a/gdb/tramp-frame.h
+++ b/gdb/tramp-frame.h
@@ -42,6 +42,13 @@ struct trad_frame_cache;
instruction sequence. */
#define TRAMP_SENTINEL_INSN ULONGEST_MAX
+/* Assuming the frame chain: (outer) prev <-> this <-> next (inner);
+ use THIS frame, and implicitly the NEXT frame's register unwind
+ method, return PREV frame's architecture. */
+
+typedef struct gdbarch *(frame_prev_arch_ftype) (frame_info_ptr this_frame,
+ void **this_prologue_cache);
+
struct tramp_frame
{
/* The trampoline's type, some a signal trampolines, some are normal
@@ -75,6 +82,11 @@ struct tramp_frame
int (*validate) (const struct tramp_frame *self,
frame_info_ptr this_frame,
CORE_ADDR *pc);
+
+ /* Given the current frame in THIS_FRAME and a frame cache in FRAME_CACHE,
+ return the architecture of the previous frame. */
+ struct gdbarch *(*prev_arch) (frame_info_ptr this_frame,
+ void **frame_cache);
};
void tramp_frame_prepend_unwinder (struct gdbarch *gdbarch,
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 11/17] [gdb/aarch64] sme: Support TPIDR2 signal frame context
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (9 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 10/17] [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 12/17] [binutils/aarch64] sme: Core file support Luis Machado
` (6 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
The Linux Kernel defines a separate context for the TPIDR2 register in a
signal frame. Handle this additional context in gdb so this register
gets restored properly when unwinding through signal frames.
The TPIDR2 register is closely related to SME, and is available when SME
support is reported.
This is tested by testcases that are available in a later patch in the series.
Regressions-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-tdep.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index c973a790f62..7ce34ee6846 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -154,6 +154,7 @@
#define AARCH64_FPSIMD_MAGIC 0x46508001
#define AARCH64_SVE_MAGIC 0x53564501
#define AARCH64_ZA_MAGIC 0x54366345
+#define AARCH64_TPIDR2_MAGIC 0x54504902
/* Defines for the extra_context that follows an AARCH64_EXTRA_MAGIC. */
#define AARCH64_EXTRA_DATAP_OFFSET 8
@@ -184,6 +185,9 @@
#define AARCH64_SME_CONTEXT_SIZE(svq) \
(AARCH64_SME_CONTEXT_REGS_OFFSET + AARCH64_SME_CONTEXT_ZA_SIZE (svq))
+/* TPIDR2 register value offset in the TPIDR2 signal frame context. */
+#define AARCH64_TPIDR2_CONTEXT_TPIDR2_OFFSET 8
+
/* Holds information about the signal frame. */
struct aarch64_linux_sigframe
{
@@ -204,6 +208,8 @@ struct aarch64_linux_sigframe
CORE_ADDR sve_section = 0;
/* Starting address of the section containing the ZA register. */
CORE_ADDR za_section = 0;
+ /* Starting address of the section containing the TPIDR2 register. */
+ CORE_ADDR tpidr2_section = 0;
/* Starting address of the section containing extra information. */
CORE_ADDR extra_section = 0;
@@ -465,6 +471,13 @@ aarch64_linux_read_signal_frame_info (frame_info_ptr this_frame,
break;
}
+ case AARCH64_TPIDR2_MAGIC:
+ {
+ /* This is context containing the tpidr2 register. */
+ signal_frame.tpidr2_section = section;
+ section += size;
+ break;
+ }
case AARCH64_EXTRA_MAGIC:
{
/* Extra is always the last valid section in reserved and points to
@@ -607,6 +620,17 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
sve_vg_from_vl (signal_frame.svl));
}
+ /* Restore the tpidr2 register, if the target supports it and if there is
+ an entry for it. */
+ if (signal_frame.tpidr2_section != 0 && tdep->has_tls ()
+ && tdep->tls_register_count >= 2)
+ {
+ /* Restore tpidr2. */
+ trad_frame_set_reg_addr (this_cache, tdep->tls_regnum_base + 1,
+ signal_frame.tpidr2_section
+ + AARCH64_TPIDR2_CONTEXT_TPIDR2_OFFSET);
+ }
+
trad_frame_set_id (this_cache, frame_id_build (signal_frame.sp, func));
}
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 12/17] [binutils/aarch64] sme: Core file support
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (10 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 11/17] [gdb/aarch64] sme: Support TPIDR2 signal frame context Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 13/17] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Luis Machado
` (5 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
From: Ezra Sitorus <ezra.sitorus@arm.com>
Add required code to support core file dumps with NT_ARM_ZA and NT_ARM_SSVE
register sets in them.
These new register sets are dumped when SME is supported.
---
bfd/elf-bfd.h | 4 ++++
bfd/elf.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 62 insertions(+)
diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index 2a64a1e6a03..d0187231d30 100644
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -2924,6 +2924,10 @@ extern char *elfcore_write_aarch_pauth
(bfd *, char *, int *, const void *, int);
extern char *elfcore_write_aarch_mte
(bfd *, char *, int *, const void *, int);
+extern char *elfcore_write_aarch_ssve
+ (bfd *, char *, int *, const void *, int);
+extern char *elfcore_write_aarch_za
+ (bfd *, char *, int *, const void *, int);
extern char *elfcore_write_arc_v2
(bfd *, char *, int *, const void *, int);
extern char *elfcore_write_riscv_csr
diff --git a/bfd/elf.c b/bfd/elf.c
index 185028cbd97..8cb924d8752 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -10057,6 +10057,18 @@ elfcore_grok_aarch_mte (bfd *abfd, Elf_Internal_Note *note)
note);
}
+static bool
+elfcore_grok_aarch_ssve (bfd *abfd, Elf_Internal_Note *note)
+{
+ return elfcore_make_note_pseudosection (abfd, ".reg-aarch-ssve", note);
+}
+
+static bool
+elfcore_grok_aarch_za (bfd *abfd, Elf_Internal_Note *note)
+{
+ return elfcore_make_note_pseudosection (abfd, ".reg-aarch-za", note);
+}
+
static bool
elfcore_grok_arc_v2 (bfd *abfd, Elf_Internal_Note *note)
{
@@ -10772,6 +10784,20 @@ elfcore_grok_note (bfd *abfd, Elf_Internal_Note *note)
else
return true;
+ case NT_ARM_SSVE:
+ if (note->namesz == 6
+ && strcmp (note->namedata, "LINUX") == 0)
+ return elfcore_grok_aarch_ssve (abfd, note);
+ else
+ return true;
+
+ case NT_ARM_ZA:
+ if (note->namesz == 6
+ && strcmp (note->namedata, "LINUX") == 0)
+ return elfcore_grok_aarch_za (abfd, note);
+ else
+ return true;
+
case NT_GDB_TDESC:
if (note->namesz == 4
&& strcmp (note->namedata, "GDB") == 0)
@@ -12386,6 +12412,34 @@ elfcore_write_aarch_mte (bfd *abfd,
size);
}
+char *
+elfcore_write_aarch_ssve (bfd *abfd,
+ char *buf,
+ int *bufsiz,
+ const void *aarch_ssve,
+ int size)
+{
+ char *note_name = "LINUX";
+ return elfcore_write_note (abfd, buf, bufsiz,
+ note_name, NT_ARM_SSVE,
+ aarch_ssve,
+ size);
+}
+
+char *
+elfcore_write_aarch_za (bfd *abfd,
+ char *buf,
+ int *bufsiz,
+ const void *aarch_za,
+ int size)
+{
+ char *note_name = "LINUX";
+ return elfcore_write_note (abfd, buf, bufsiz,
+ note_name, NT_ARM_ZA,
+ aarch_za,
+ size);
+}
+
char *
elfcore_write_arc_v2 (bfd *abfd,
char *buf,
@@ -12567,6 +12621,10 @@ elfcore_write_register_note (bfd *abfd,
return elfcore_write_aarch_pauth (abfd, buf, bufsiz, data, size);
if (strcmp (section, ".reg-aarch-mte") == 0)
return elfcore_write_aarch_mte (abfd, buf, bufsiz, data, size);
+ if (strcmp (section, ".reg-aarch-ssve") == 0)
+ return elfcore_write_aarch_ssve (abfd, buf, bufsiz, data, size);
+ if (strcmp (section, ".reg-aarch-za") == 0)
+ return elfcore_write_aarch_za (abfd, buf, bufsiz, data, size);
if (strcmp (section, ".reg-arc-v2") == 0)
return elfcore_write_arc_v2 (abfd, buf, bufsiz, data, size);
if (strcmp (section, ".gdb-tdesc") == 0)
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 13/17] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (11 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 12/17] [binutils/aarch64] sme: Core file support Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 14/17] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order Luis Machado
` (4 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
When we have a core file generated by gdb (via the gcore command), gdb dumps
the target description to a note. During loading of that core file, gdb will
first try to load that saved target description.
This works fine for almost all architectures. But AArch64 has a few
dynamically-generated target descriptions/gdbarch depending on the vector
length that was in use at the time the core file was generated.
The target description gdb dumps to the core file note is the one generated
at the time of attachment/startup. If, for example, the SVE vector length
changed during execution, this would not reflect on the core file, as gdb
would still dump the initial target description.
Another issue is that the gdbarch potentially doesn't match the thread's
real gdbarch, and so things like the register cache may have different formats
and sizes.
To address this, fetch the thread's architecture before dumping its register
state. That way we will always use the correct target description/gdbarch.
---
gdb/linux-tdep.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/gdb/linux-tdep.c b/gdb/linux-tdep.c
index 1fc9cb6faee..6749a39cfc2 100644
--- a/gdb/linux-tdep.c
+++ b/gdb/linux-tdep.c
@@ -2091,12 +2091,28 @@ linux_make_corefile_notes (struct gdbarch *gdbarch, bfd *obfd, int *note_size)
stop_signal);
if (signalled_thr != nullptr)
- linux_corefile_thread (signalled_thr, &thread_args);
+ {
+ /* On some architectures, like AArch64, each thread can have a distinct
+ gdbarch (due to scalable extensions), and using the inferior gdbarch
+ is incorrect.
+
+ Fetch each thread's gdbarch and pass it down to the lower layers so
+ we can dump the right set of registers. */
+ thread_args.gdbarch = target_thread_architecture (signalled_thr->ptid);
+ linux_corefile_thread (signalled_thr, &thread_args);
+ }
for (thread_info *thr : current_inferior ()->non_exited_threads ())
{
if (thr == signalled_thr)
continue;
+ /* On some architectures, like AArch64, each thread can have a distinct
+ gdbarch (due to scalable extensions), and using the inferior gdbarch
+ is incorrect.
+
+ Fetch each thread's gdbarch and pass it down to the lower layers so
+ we can dump the right set of registers. */
+ thread_args.gdbarch = target_thread_architecture (thr->ptid);
linux_corefile_thread (thr, &thread_args);
}
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 14/17] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (12 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 13/17] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 15/17] [gdb/aarch64] sme: Core file support for Linux Luis Machado
` (3 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
Due to the nature of the AArch64 SVE/SME extensions in GDB, each thread
can potentially have distinct target descriptions/gdbarches.
When loading a gcore-generated core file, at the moment GDB gives priority
to the target description dumped to NT_GDB_TDESC. Though technically correct
for most target, it doesn't work correctly for AArch64 with SVE or SME
support.
The correct approach for AArch64/Linux is to rely on the
gdbarch_core_read_description hook, so it can figure out the proper target
description for a given thread based on the various available register notes.
I think this should work for other architectures as well. If not, we may
need to adjust things so all architectures get the information that they
need for discovering the target description of the core file.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/corelow.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/gdb/corelow.c b/gdb/corelow.c
index db489b4280e..e3ad9772869 100644
--- a/gdb/corelow.c
+++ b/gdb/corelow.c
@@ -1078,6 +1078,21 @@ core_target::thread_alive (ptid_t ptid)
const struct target_desc *
core_target::read_description ()
{
+ /* If the architecture provides a corefile target description hook, use
+ it now. Even if the core file contains a target description in a note
+ section, it is not useful for targets that can potentially have distinct
+ descriptions for each thread. One example is AArch64's SVE/SME
+ extensions that allow per-thread vector length changes, resulting in
+ registers with different sizes. */
+ if (m_core_gdbarch && gdbarch_core_read_description_p (m_core_gdbarch))
+ {
+ const struct target_desc *result;
+
+ result = gdbarch_core_read_description (m_core_gdbarch, this, core_bfd);
+ if (result != nullptr)
+ return result;
+ }
+
/* If the core file contains a target description note then we will use
that in preference to anything else. */
bfd_size_type tdesc_note_size = 0;
@@ -1101,15 +1116,6 @@ core_target::read_description ()
}
}
- if (m_core_gdbarch && gdbarch_core_read_description_p (m_core_gdbarch))
- {
- const struct target_desc *result;
-
- result = gdbarch_core_read_description (m_core_gdbarch, this, core_bfd);
- if (result != NULL)
- return result;
- }
-
return this->beneath ()->read_description ();
}
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 15/17] [gdb/aarch64] sme: Core file support for Linux
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (13 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 14/17] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 16/17] [gdb/testsuite] sme: Add SVE/SME testcases Luis Machado
` (2 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
This patch enables dumping SME state via gdb's gcore command and also
enables gdb to read SME state from a core file generated by the Linux
Kernel.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-tdep.c | 532 ++++++++++++++++++++++++++++--
gdb/arch/aarch64-scalable-linux.c | 34 ++
gdb/arch/aarch64-scalable-linux.h | 15 +
3 files changed, 548 insertions(+), 33 deletions(-)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index 7ce34ee6846..0bd75daa994 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -57,6 +57,10 @@
#include "elf/common.h"
#include "elf/aarch64.h"
+#include "arch/aarch64-insn.h"
+
+/* For std::sqrt */
+#include <cmath>
/* Signal frame handling.
@@ -743,50 +747,55 @@ const struct regset aarch64_linux_fpregset =
#define SVE_HEADER_FLAG_SVE 1
-/* Get VQ value from SVE section in the core dump. */
+/* Get the vector quotient (VQ) or streaming vector quotient (SVQ) value
+ from the section named SECTION_NAME.
+
+ Return non-zero if successful and 0 otherwise. */
static uint64_t
-aarch64_linux_core_read_vq (struct gdbarch *gdbarch, bfd *abfd)
+aarch64_linux_core_read_vq (struct gdbarch *gdbarch, bfd *abfd,
+ const char *section_name)
{
- gdb_byte header[SVE_HEADER_SIZE];
- enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- asection *sve_section = bfd_get_section_by_name (abfd, ".reg-aarch-sve");
+ gdb_assert (section_name != nullptr);
- if (sve_section == nullptr)
+ asection *section = bfd_get_section_by_name (abfd, section_name);
+
+ if (section == nullptr)
{
/* No SVE state. */
return 0;
}
- size_t size = bfd_section_size (sve_section);
+ size_t size = bfd_section_size (section);
/* Check extended state size. */
if (size < SVE_HEADER_SIZE)
{
- warning (_("'.reg-aarch-sve' section in core file too small."));
+ warning (_("'%s' core file section is too small. "
+ "Expected %s bytes, got %s bytes"), section_name,
+ pulongest (SVE_HEADER_SIZE), pulongest (size));
return 0;
}
- if (!bfd_get_section_contents (abfd, sve_section, header, 0, SVE_HEADER_SIZE))
+ gdb_byte header[SVE_HEADER_SIZE];
+
+ if (!bfd_get_section_contents (abfd, section, header, 0, SVE_HEADER_SIZE))
{
warning (_("Couldn't read sve header from "
- "'.reg-aarch-sve' section in core file."));
+ "'%s' core file section."), section_name);
return 0;
}
- uint64_t vl = extract_unsigned_integer (header + SVE_HEADER_VL_OFFSET,
- SVE_HEADER_VL_LENGTH, byte_order);
- uint64_t vq = sve_vq_from_vl (vl);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ uint64_t vq
+ = sve_vq_from_vl (extract_unsigned_integer (header + SVE_HEADER_VL_OFFSET,
+ SVE_HEADER_VL_LENGTH,
+ byte_order));
- if (vq > AARCH64_MAX_SVE_VQ)
- {
- warning (_("SVE Vector length in core file not supported by this version"
- " of GDB. (VQ=%s)"), pulongest (vq));
- return 0;
- }
- else if (vq == 0)
+ if (vq > AARCH64_MAX_SVE_VQ || vq == 0)
{
- warning (_("SVE Vector length in core file is invalid. (VQ=%s"),
+ warning (_("SVE/SSVE vector length in core file is invalid."
+ " (max vq=%d) (detected vq=%s)"), AARCH64_MAX_SVE_VQ,
pulongest (vq));
return 0;
}
@@ -794,14 +803,53 @@ aarch64_linux_core_read_vq (struct gdbarch *gdbarch, bfd *abfd)
return vq;
}
+/* Get the vector quotient (VQ) value from CORE_BFD's sections.
+
+ Return non-zero if successful and 0 otherwise. */
+
+static uint64_t
+aarch64_linux_core_read_vq_from_sections (struct gdbarch *gdbarch,
+ bfd *core_bfd)
+{
+ /* First check if we have a SSVE section. If so, check if it is active. */
+ asection *section = bfd_get_section_by_name (core_bfd, ".reg-aarch-ssve");
+
+ if (section != nullptr)
+ {
+ /* We've found a SSVE section, so now fetch its data. */
+ gdb_byte header[SVE_HEADER_SIZE];
+
+ if (bfd_get_section_contents (core_bfd, section, header, 0,
+ SVE_HEADER_SIZE))
+ {
+ /* Check if the SSVE section has SVE contents. */
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ uint16_t flags
+ = extract_unsigned_integer (header + SVE_HEADER_FLAGS_OFFSET,
+ SVE_HEADER_FLAGS_LENGTH, byte_order);
+
+ if (flags & SVE_HEADER_FLAG_SVE)
+ {
+ /* The SSVE state is active, so return the vector length from the
+ the SSVE section. */
+ return aarch64_linux_core_read_vq (gdbarch, core_bfd,
+ ".reg-aarch-ssve");
+ }
+ }
+ }
+
+ /* No valid SSVE section. Return the vq from the SVE section (if any). */
+ return aarch64_linux_core_read_vq (gdbarch, core_bfd, ".reg-aarch-sve");
+}
+
/* Supply register REGNUM from BUF to REGCACHE, using the register map
in REGSET. If REGNUM is -1, do this for all registers in REGSET.
- If BUF is NULL, set the registers to "unavailable" status. */
+ If BUF is nullptr, set the registers to "unavailable" status. */
static void
-aarch64_linux_supply_sve_regset (const struct regset *regset,
- struct regcache *regcache,
- int regnum, const void *buf, size_t size)
+supply_sve_regset (const struct regset *regset,
+ struct regcache *regcache,
+ int regnum, const void *buf, size_t size)
{
gdb_byte *header = (gdb_byte *) buf;
struct gdbarch *gdbarch = regcache->arch ();
@@ -853,14 +901,89 @@ aarch64_linux_supply_sve_regset (const struct regset *regset,
}
}
+/* Collect an inactive SVE register set state. This is equivalent to a
+ fpsimd layout.
+
+ Collect the data from REGCACHE to BUF, using the register
+ map in REGSET. */
+
+static void
+collect_inactive_sve_regset (const struct regcache *regcache,
+ void *buf, size_t size, int vg_regnum)
+{
+ gdb_byte *header = (gdb_byte *) buf;
+ struct gdbarch *gdbarch = regcache->arch ();
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+
+ gdb_assert (buf != nullptr);
+ gdb_assert (size > SVE_HEADER_SIZE);
+
+ /* Zero out everything first. */
+ memset ((gdb_byte *) buf, 0, SVE_CORE_DUMMY_SIZE);
+
+ /* BUF starts with a SVE header prior to the register dump. */
+
+ /* Dump the default size of an empty SVE payload. */
+ uint32_t real_size = SVE_CORE_DUMMY_SIZE;
+ store_unsigned_integer (header + SVE_HEADER_SIZE_OFFSET,
+ SVE_HEADER_SIZE_LENGTH, byte_order, real_size);
+
+ /* Dump a dummy max size. */
+ uint32_t max_size = SVE_CORE_DUMMY_MAX_SIZE;
+ store_unsigned_integer (header + SVE_HEADER_MAX_SIZE_OFFSET,
+ SVE_HEADER_MAX_SIZE_LENGTH, byte_order, max_size);
+
+ /* Dump the vector length. */
+ ULONGEST vg = 0;
+ regcache->raw_collect (vg_regnum, &vg);
+ uint16_t vl = sve_vl_from_vg (vg);
+ store_unsigned_integer (header + SVE_HEADER_VL_OFFSET, SVE_HEADER_VL_LENGTH,
+ byte_order, vl);
+
+ /* Dump the standard maximum vector length. */
+ uint16_t max_vl = SVE_CORE_DUMMY_MAX_VL;
+ store_unsigned_integer (header + SVE_HEADER_MAX_VL_OFFSET,
+ SVE_HEADER_MAX_VL_LENGTH, byte_order,
+ max_vl);
+
+ /* The rest of the fields is zero. */
+ uint16_t flags = SVE_CORE_DUMMY_FLAGS;
+ store_unsigned_integer (header + SVE_HEADER_FLAGS_OFFSET,
+ SVE_HEADER_FLAGS_LENGTH, byte_order,
+ flags);
+ uint16_t reserved = SVE_CORE_DUMMY_RESERVED;
+ store_unsigned_integer (header + SVE_HEADER_RESERVED_OFFSET,
+ SVE_HEADER_RESERVED_LENGTH, byte_order, reserved);
+
+ /* We are done with the header part of it. Now dump the register state
+ in the FPSIMD format. */
+
+ /* Dump the first 128 bits of each of the Z registers. */
+ header += AARCH64_SVE_CONTEXT_REGS_OFFSET;
+ for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
+ regcache->raw_collect_part (AARCH64_SVE_Z0_REGNUM + i, 0, V_REGISTER_SIZE,
+ header + V_REGISTER_SIZE * i);
+
+ /* Dump FPSR and FPCR. */
+ header += 32 * V_REGISTER_SIZE;
+ regcache->raw_collect (AARCH64_FPSR_REGNUM, header);
+ regcache->raw_collect (AARCH64_FPCR_REGNUM, header);
+
+ /* Dump two reserved empty fields of 4 bytes. */
+ header += 8;
+ memset (header, 0, 8);
+
+ /* We should have a FPSIMD-formatted register dump now. */
+}
+
/* Collect register REGNUM from REGCACHE to BUF, using the register
map in REGSET. If REGNUM is -1, do this for all registers in
REGSET. */
static void
-aarch64_linux_collect_sve_regset (const struct regset *regset,
- const struct regcache *regcache,
- int regnum, void *buf, size_t size)
+collect_sve_regset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *buf, size_t size)
{
gdb_byte *header = (gdb_byte *) buf;
struct gdbarch *gdbarch = regcache->arch ();
@@ -875,24 +998,308 @@ aarch64_linux_collect_sve_regset (const struct regset *regset,
store_unsigned_integer (header + SVE_HEADER_SIZE_OFFSET,
SVE_HEADER_SIZE_LENGTH, byte_order, size);
+ uint32_t max_size = SVE_CORE_DUMMY_MAX_SIZE;
store_unsigned_integer (header + SVE_HEADER_MAX_SIZE_OFFSET,
- SVE_HEADER_MAX_SIZE_LENGTH, byte_order, size);
+ SVE_HEADER_MAX_SIZE_LENGTH, byte_order, max_size);
store_unsigned_integer (header + SVE_HEADER_VL_OFFSET, SVE_HEADER_VL_LENGTH,
byte_order, sve_vl_from_vq (vq));
+ uint16_t max_vl = SVE_CORE_DUMMY_MAX_VL;
store_unsigned_integer (header + SVE_HEADER_MAX_VL_OFFSET,
SVE_HEADER_MAX_VL_LENGTH, byte_order,
- sve_vl_from_vq (vq));
+ max_vl);
+ uint16_t flags = SVE_HEADER_FLAG_SVE;
store_unsigned_integer (header + SVE_HEADER_FLAGS_OFFSET,
SVE_HEADER_FLAGS_LENGTH, byte_order,
- SVE_HEADER_FLAG_SVE);
+ flags);
+ uint16_t reserved = SVE_CORE_DUMMY_RESERVED;
store_unsigned_integer (header + SVE_HEADER_RESERVED_OFFSET,
- SVE_HEADER_RESERVED_LENGTH, byte_order, 0);
+ SVE_HEADER_RESERVED_LENGTH, byte_order, reserved);
/* The SVE register dump follows. */
regcache->collect_regset (regset, regnum, (gdb_byte *) buf + SVE_HEADER_SIZE,
size - SVE_HEADER_SIZE);
}
+/* Supply register REGNUM from BUF to REGCACHE, using the register map
+ in REGSET. If REGNUM is -1, do this for all registers in REGSET.
+ If BUF is NULL, set the registers to "unavailable" status. */
+
+static void
+aarch64_linux_supply_sve_regset (const struct regset *regset,
+ struct regcache *regcache,
+ int regnum, const void *buf, size_t size)
+{
+ struct gdbarch *gdbarch = regcache->arch ();
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ if (tdep->has_sme ())
+ {
+ ULONGEST svcr = 0;
+ regcache->raw_collect (tdep->sme_svcr_regnum, &svcr);
+
+ /* Is streaming mode enabled? */
+ if (svcr & SVCR_SM_BIT)
+ /* If so, don't load SVE data from the SVE section. The data to be
+ used is in the SSVE section. */
+ return;
+ }
+ /* If streaming mode is not enabled, load the SVE regcache data from the SVE
+ section. */
+ supply_sve_regset (regset, regcache, regnum, buf, size);
+}
+
+/* Collect register REGNUM from REGCACHE to BUF, using the register
+ map in REGSET. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+static void
+aarch64_linux_collect_sve_regset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *buf, size_t size)
+{
+ struct gdbarch *gdbarch = regcache->arch ();
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+ bool streaming_mode = false;
+
+ if (tdep->has_sme ())
+ {
+ ULONGEST svcr = 0;
+ regcache->raw_collect (tdep->sme_svcr_regnum, &svcr);
+
+ /* Is streaming mode enabled? */
+ if (svcr & SVCR_SM_BIT)
+ {
+ /* If so, don't dump SVE regcache data to the SVE section. The SVE
+ data should be dumped to the SSVE section. Dump an empty SVE
+ block instead. */
+ streaming_mode = true;
+ }
+ }
+
+ /* If streaming mode is not enabled or there is no SME support, dump the
+ SVE regcache data to the SVE section. */
+
+ /* Check if we have an active SVE state (non-zero Z/P/FFR registers).
+ If so, then we need to dump registers in the SVE format.
+
+ Otherwise we should dump the registers in the FPSIMD format. */
+ if (sve_state_is_empty (regcache) || streaming_mode)
+ collect_inactive_sve_regset (regcache, buf, size, AARCH64_SVE_VG_REGNUM);
+ else
+ collect_sve_regset (regset, regcache, regnum, buf, size);
+}
+
+/* Supply register REGNUM from BUF to REGCACHE, using the register map
+ in REGSET. If REGNUM is -1, do this for all registers in REGSET.
+ If BUF is NULL, set the registers to "unavailable" status. */
+
+static void
+aarch64_linux_supply_ssve_regset (const struct regset *regset,
+ struct regcache *regcache,
+ int regnum, const void *buf, size_t size)
+{
+ gdb_byte *header = (gdb_byte *) buf;
+ struct gdbarch *gdbarch = regcache->arch ();
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ uint16_t flags = extract_unsigned_integer (header + SVE_HEADER_FLAGS_OFFSET,
+ SVE_HEADER_FLAGS_LENGTH,
+ byte_order);
+
+ /* Since SVCR's bits are inferred from the data we have in the header of the
+ SSVE section, we need to initialize it to zero first, so that it doesn't
+ carry garbage data. */
+ ULONGEST svcr = 0;
+ regcache->raw_supply (tdep->sme_svcr_regnum, &svcr);
+
+ /* Is streaming mode enabled? */
+ if (flags & SVE_HEADER_FLAG_SVE)
+ {
+ /* Streaming mode is active, so flip the SM bit. */
+ svcr = SVCR_SM_BIT;
+ regcache->raw_supply (tdep->sme_svcr_regnum, &svcr);
+
+ /* Fetch the SVE data from the SSVE section. */
+ supply_sve_regset (regset, regcache, regnum, buf, size);
+ }
+}
+
+/* Collect register REGNUM from REGCACHE to BUF, using the register
+ map in REGSET. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+static void
+aarch64_linux_collect_ssve_regset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *buf, size_t size)
+{
+ struct gdbarch *gdbarch = regcache->arch ();
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+ ULONGEST svcr = 0;
+ regcache->raw_collect (tdep->sme_svcr_regnum, &svcr);
+
+ /* Is streaming mode enabled? */
+ if (svcr & SVCR_SM_BIT)
+ {
+ /* If so, dump SVE regcache data to the SSVE section. */
+ collect_sve_regset (regset, regcache, regnum, buf, size);
+ }
+ else
+ {
+ /* Otherwise dump an empty SVE block to the SSVE section with the
+ streaming vector length. */
+ collect_inactive_sve_regset (regcache, buf, size, tdep->sme_svg_regnum);
+ }
+}
+
+/* Supply register REGNUM from BUF to REGCACHE, using the register map
+ in REGSET. If REGNUM is -1, do this for all registers in REGSET.
+ If BUF is NULL, set the registers to "unavailable" status. */
+
+static void
+aarch64_linux_supply_za_regset (const struct regset *regset,
+ struct regcache *regcache,
+ int regnum, const void *buf, size_t size)
+{
+ gdb_byte *header = (gdb_byte *) buf;
+ struct gdbarch *gdbarch = regcache->arch ();
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+
+ /* Handle an empty buffer. */
+ if (buf == nullptr)
+ return regcache->supply_regset (regset, regnum, nullptr, size);
+
+ if (size < SVE_HEADER_SIZE)
+ warning (_("ZA state header size (%s) invalid. Should be at least %s."),
+ pulongest (size), pulongest (SVE_HEADER_SIZE));
+
+ /* The ZA register note in a core file can have a couple of states:
+
+ 1 - Just the header without the payload. This means that there is no
+ ZA data, and we should populate only SVCR and SVG registers on GDB's
+ side. The ZA data should be marked as unavailable.
+
+ 2 - The header with an additional data payload. This means there is
+ actual ZA data, and we should populate ZA, SVCR and SVG. */
+
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ /* Populate SVG. */
+ ULONGEST svg
+ = sve_vg_from_vl (extract_unsigned_integer (header + SVE_HEADER_VL_OFFSET,
+ SVE_HEADER_VL_LENGTH,
+ byte_order));
+ regcache->raw_supply (tdep->sme_svg_regnum, &svg);
+
+ size_t data_size
+ = extract_unsigned_integer (header + SVE_HEADER_SIZE_OFFSET,
+ SVE_HEADER_SIZE_LENGTH, byte_order)
+ - SVE_HEADER_SIZE;
+
+ /* Populate SVCR. */
+ bool has_za_payload = (data_size > 0);
+ ULONGEST svcr;
+ regcache->raw_collect (tdep->sme_svcr_regnum, &svcr);
+
+ /* If we have a ZA payload, enable bit 2 of SVCR, otherwise clear it. This
+ register gets updated by the SVE/SSVE-handling functions as well, as they
+ report the SM bit 1. */
+ if (has_za_payload)
+ svcr |= SVCR_ZA_BIT;
+ else
+ svcr &= ~SVCR_ZA_BIT;
+
+ /* Update SVCR in the register buffer. */
+ regcache->raw_supply (tdep->sme_svcr_regnum, &svcr);
+
+ /* Populate the register cache with ZA register contents, if we have any. */
+ buf = has_za_payload ? (gdb_byte *) buf + SVE_HEADER_SIZE : nullptr;
+
+ /* Update ZA in the register buffer. */
+ if (has_za_payload)
+ regcache->raw_supply (tdep->sme_za_regnum, buf);
+ else
+ {
+ size_t za_bytes = std::pow (sve_vl_from_vg (svg), 2);
+ gdb_byte za_zeroed[za_bytes];
+ memset (za_zeroed, 0, za_bytes);
+ regcache->raw_supply (tdep->sme_za_regnum, za_zeroed);
+ }
+}
+
+/* Collect register REGNUM from REGCACHE to BUF, using the register
+ map in REGSET. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+static void
+aarch64_linux_collect_za_regset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *buf, size_t size)
+{
+ gdb_assert (buf != nullptr);
+
+ if (size < SVE_HEADER_SIZE)
+ warning (_("ZA state header size (%s) invalid. Should be at least %s."),
+ pulongest (size), pulongest (SVE_HEADER_SIZE));
+
+ /* The ZA register note in a core file can have a couple of states:
+
+ 1 - Just the header without the payload. This means that there is no
+ ZA data, and we should dump just the header.
+
+ 2 - The header with an additional data payload. This means there is
+ actual ZA data, and we should dump both the header and the ZA data
+ payload. */
+
+ aarch64_gdbarch_tdep *tdep
+ = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
+
+ /* Determine if we have ZA state from the SVCR register ZA bit. */
+ ULONGEST svcr;
+ regcache->raw_collect (tdep->sme_svcr_regnum, &svcr);
+
+ /* Check the ZA payload. */
+ bool has_za_payload = (svcr & SVCR_ZA_BIT) != 0;
+ size = has_za_payload ? size : SVE_HEADER_SIZE;
+
+ /* Write the size and max_size fields. */
+ gdb_byte *header = (gdb_byte *) buf;
+ enum bfd_endian byte_order = gdbarch_byte_order (regcache->arch ());
+ store_unsigned_integer (header + SVE_HEADER_SIZE_OFFSET,
+ SVE_HEADER_SIZE_LENGTH, byte_order, size);
+
+ uint32_t max_size
+ = SVE_HEADER_SIZE + std::pow (sve_vl_from_vq (tdep->sme_svq), 2);
+ store_unsigned_integer (header + SVE_HEADER_MAX_SIZE_OFFSET,
+ SVE_HEADER_MAX_SIZE_LENGTH, byte_order, max_size);
+
+ /* Output the other fields of the ZA header (vl, max_vl, flags and
+ reserved). */
+ uint64_t svq = tdep->sme_svq;
+ store_unsigned_integer (header + SVE_HEADER_VL_OFFSET, SVE_HEADER_VL_LENGTH,
+ byte_order, sve_vl_from_vq (svq));
+
+ uint16_t max_vl = SVE_CORE_DUMMY_MAX_VL;
+ store_unsigned_integer (header + SVE_HEADER_MAX_VL_OFFSET,
+ SVE_HEADER_MAX_VL_LENGTH, byte_order,
+ max_vl);
+
+ uint16_t flags = SVE_CORE_DUMMY_FLAGS;
+ store_unsigned_integer (header + SVE_HEADER_FLAGS_OFFSET,
+ SVE_HEADER_FLAGS_LENGTH, byte_order, flags);
+
+ uint16_t reserved = SVE_CORE_DUMMY_RESERVED;
+ store_unsigned_integer (header + SVE_HEADER_RESERVED_OFFSET,
+ SVE_HEADER_RESERVED_LENGTH, byte_order, reserved);
+
+ buf = has_za_payload ? (gdb_byte *) buf + SVE_HEADER_SIZE : nullptr;
+
+ /* Dump the register cache contents for the ZA register to the buffer. */
+ regcache->collect_regset (regset, regnum, (gdb_byte *) buf,
+ size - SVE_HEADER_SIZE);
+}
+
/* Implement the "iterate_over_regset_sections" gdbarch method. */
static void
@@ -919,6 +1326,30 @@ aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
{ 0 }
};
+ const struct regset aarch64_linux_ssve_regset =
+ {
+ sve_regmap,
+ aarch64_linux_supply_ssve_regset, aarch64_linux_collect_ssve_regset,
+ REGSET_VARIABLE_SIZE
+ };
+
+ /* If SME is supported in the core file, process the SSVE section first,
+ and the SVE section last. This is because we need information from
+ the SSVE set to determine if streaming mode is active. If streaming
+ mode is active, we need to extract the data from the SSVE section.
+
+ Otherwise, if streaming mode is not active, we fetch the data from the
+ SVE section. */
+ if (tdep->has_sme ())
+ {
+ cb (".reg-aarch-ssve",
+ SVE_HEADER_SIZE
+ + regcache_map_entry_size (aarch64_linux_fpregmap),
+ SVE_HEADER_SIZE + regcache_map_entry_size (sve_regmap),
+ &aarch64_linux_ssve_regset, "SSVE registers", cb_data);
+ }
+
+ /* Handle the SVE register set. */
const struct regset aarch64_linux_sve_regset =
{
sve_regmap,
@@ -935,6 +1366,29 @@ aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
cb (".reg2", AARCH64_LINUX_SIZEOF_FPREGSET, AARCH64_LINUX_SIZEOF_FPREGSET,
&aarch64_linux_fpregset, NULL, cb_data);
+ if (tdep->has_sme ())
+ {
+ /* Setup the register set information for a ZA register set core
+ dump. */
+
+ /* Create this on the fly in order to handle the ZA register size. */
+ const struct regcache_map_entry za_regmap[] =
+ {
+ { 1, tdep->sme_za_regnum, (int) std::pow (sve_vl_from_vq (tdep->sme_svq), 2) }
+ };
+
+ const struct regset aarch64_linux_za_regset =
+ {
+ za_regmap,
+ aarch64_linux_supply_za_regset, aarch64_linux_collect_za_regset,
+ REGSET_VARIABLE_SIZE
+ };
+
+ cb (".reg-aarch-za",
+ SVE_HEADER_SIZE,
+ SVE_HEADER_SIZE + std::pow (sve_vl_from_vq (tdep->sme_svq), 2),
+ &aarch64_linux_za_regset, "ZA register", cb_data);
+ }
if (tdep->has_pauth ())
{
@@ -1013,7 +1467,16 @@ aarch64_linux_core_read_description (struct gdbarch *gdbarch,
CORE_ADDR hwcap2 = linux_get_hwcap2 (auxv, target, gdbarch);
aarch64_features features;
- features.vq = aarch64_linux_core_read_vq (gdbarch, abfd);
+
+ /* We need to extract the SVE data from the .reg-aarch-sve section or the
+ .reg-aarch-ssve section depending on which one was active when the core
+ file was generated.
+
+ If the SSVE section contains SVE data, then it is considered active.
+ Otherwise the SVE section is considered active. This guarantees we will
+ have the correct target description with the correct SVE vector
+ length. */
+ features.vq = aarch64_linux_core_read_vq_from_sections (gdbarch, abfd);
features.pauth = hwcap & AARCH64_HWCAP_PACA;
features.mte = hwcap2 & HWCAP2_MTE;
@@ -1027,6 +1490,9 @@ aarch64_linux_core_read_description (struct gdbarch *gdbarch,
features.tls = size / AARCH64_TLS_REGISTER_SIZE;
}
+ features.svq
+ = aarch64_linux_core_read_vq (gdbarch, abfd, ".reg-aarch-za");
+
return aarch64_read_description (features);
}
diff --git a/gdb/arch/aarch64-scalable-linux.c b/gdb/arch/aarch64-scalable-linux.c
index 3803acfd9a8..2e4aa92e36f 100644
--- a/gdb/arch/aarch64-scalable-linux.c
+++ b/gdb/arch/aarch64-scalable-linux.c
@@ -19,3 +19,37 @@
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "arch/aarch64-scalable-linux.h"
+#include "arch/aarch64.h"
+#include "gdbsupport/byte-vector.h"
+#include "gdbsupport/common-regcache.h"
+
+/* See arch/aarch64-scalable-linux.h */
+
+bool
+sve_state_is_empty (const struct reg_buffer_common *reg_buf)
+{
+ /* Instead of allocating a buffer with the size of the current vector
+ length, just use a buffer that is big enough for all cases. */
+ gdb_byte zero_buffer[256];
+
+ /* Zero it out. */
+ memset (zero_buffer, 0, 256);
+
+ /* Are any of the Z registers set (non-zero) after the first 128 bits? */
+ for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
+ {
+ if (!reg_buf->raw_compare (AARCH64_SVE_Z0_REGNUM + i, zero_buffer,
+ V_REGISTER_SIZE))
+ return false;
+ }
+
+ /* Are any of the P registers set (non-zero)? */
+ for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
+ {
+ if (!reg_buf->raw_compare (AARCH64_SVE_P0_REGNUM + i, zero_buffer, 0))
+ return false;
+ }
+
+ /* Is the FFR register set (non-zero)? */
+ return reg_buf->raw_compare (AARCH64_SVE_FFR_REGNUM, zero_buffer, 0);
+}
diff --git a/gdb/arch/aarch64-scalable-linux.h b/gdb/arch/aarch64-scalable-linux.h
index df1741004ed..cb9d85a9d5d 100644
--- a/gdb/arch/aarch64-scalable-linux.h
+++ b/gdb/arch/aarch64-scalable-linux.h
@@ -22,6 +22,7 @@
#define ARCH_AARCH64_SCALABLE_LINUX_H
#include "gdbsupport/common-defs.h"
+#include "gdbsupport/common-regcache.h"
/* Feature check for Scalable Matrix Extension. */
#ifndef HWCAP2_SME
@@ -35,4 +36,18 @@
/* Mask including all valid SVCR bits. */
#define SVCR_BIT_MASK (SVCR_SM_BIT | SVCR_ZA_BIT)
+/* SVE/SSVE-related constants used for an empty SVE/SSVE register set
+ dumped to a core file. When SME is supported, either the SVE state or
+ the SSVE state will be empty when it is dumped to a core file. */
+#define SVE_CORE_DUMMY_SIZE 0x220
+#define SVE_CORE_DUMMY_MAX_SIZE 0x2240
+#define SVE_CORE_DUMMY_VL 0x10
+#define SVE_CORE_DUMMY_MAX_VL 0x100
+#define SVE_CORE_DUMMY_FLAGS 0x0
+#define SVE_CORE_DUMMY_RESERVED 0x0
+
+/* Return TRUE if the SVE state in the register cache REGCACHE
+ is empty (zero). Return FALSE otherwise. */
+extern bool sve_state_is_empty (const struct reg_buffer_common *reg_buf);
+
#endif /* ARCH_AARCH64_SCALABLE_LINUX_H */
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 16/17] [gdb/testsuite] sme: Add SVE/SME testcases
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (14 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 15/17] [gdb/aarch64] sme: Core file support for Linux Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 4:26 ` [PATCH 17/17] [gdb/docs] sme: Document SME registers and features Luis Machado
2023-04-11 15:50 ` [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux John Baldwin
17 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
Add 5 SVE/SME tests to exercise all the new features like reading/writing
registers, pseudo-registers, signal frames and core files.
- Sanity check for SME: Gives a brief smoke test to make sure the most basic
of features are working correctly.
- ZA unavailability tests: Validates the behavior/content of the ZA register
is correct when no payload is available. It also exercises changing the
vector lengths.
- ZA Availability tests: These tests exercise reading/writing to all the
possible ZA pseudo-registers, and validates the state is correct.
- Core file tests: Validates that core file reading and writing works
correctly and that all state dumped/loaded is sane. This is exercised for
both Linux Kernel core files and gcore core files.
- Signal frame tests: Validates the correct restoration of SME/SVE/FPSIMD
values across signal frames.
Since some of these tests are very lengthy and take a little while to run
(under QEMU at the moment), I decided to parallelize them into smaller
chunks so we can throw some more CPU power at them so they run faster.
I'd still like to add a few more tests to give the testsuite more coverage
in the areas of SME/SVE. Hopefully in the near future that will happen.
Just a reminder that most of these tests will FAIL when running against
gdbserver because all of the tests change the vector length mid-execution
in some way. Since gdbserver can't communicate the change of state over
RSP to GDB, we will always get wrong state from gdbserver.
Co-Authored-By: Ezra Sitorus <ezra.sitorus@arm.com>
---
gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp | 18 +
gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp | 18 +
gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp | 18 +
gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp | 18 +
gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp | 18 +
gdb/testsuite/gdb.arch/aarch64-sme-core.c | 361 +++++++++++++++++
.../gdb.arch/aarch64-sme-core.exp.tcl | 167 ++++++++
.../gdb.arch/aarch64-sme-regs-available-0.exp | 18 +
.../gdb.arch/aarch64-sme-regs-available-1.exp | 18 +
.../gdb.arch/aarch64-sme-regs-available-2.exp | 18 +
.../gdb.arch/aarch64-sme-regs-available-3.exp | 18 +
.../gdb.arch/aarch64-sme-regs-available-4.exp | 18 +
.../gdb.arch/aarch64-sme-regs-available.c | 184 +++++++++
.../aarch64-sme-regs-available.exp.tcl | 194 +++++++++
.../gdb.arch/aarch64-sme-regs-sigframe-0.exp | 18 +
.../gdb.arch/aarch64-sme-regs-sigframe-1.exp | 18 +
.../gdb.arch/aarch64-sme-regs-sigframe-2.exp | 18 +
.../gdb.arch/aarch64-sme-regs-sigframe-3.exp | 18 +
.../gdb.arch/aarch64-sme-regs-sigframe-4.exp | 18 +
.../gdb.arch/aarch64-sme-regs-sigframe.c | 368 +++++++++++++++++
.../aarch64-sme-regs-sigframe.exp.tcl | 156 ++++++++
.../aarch64-sme-regs-unavailable-0.exp | 18 +
.../aarch64-sme-regs-unavailable-1.exp | 18 +
.../aarch64-sme-regs-unavailable-2.exp | 18 +
.../aarch64-sme-regs-unavailable-3.exp | 18 +
.../aarch64-sme-regs-unavailable-4.exp | 18 +
.../gdb.arch/aarch64-sme-regs-unavailable.c | 154 ++++++++
.../aarch64-sme-regs-unavailable.exp.tcl | 162 ++++++++
gdb/testsuite/gdb.arch/aarch64-sme-sanity.c | 249 ++++++++++++
gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp | 72 ++++
gdb/testsuite/lib/aarch64.exp | 372 ++++++++++++++++++
gdb/testsuite/lib/gdb.exp | 63 +++
32 files changed, 2862 insertions(+)
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core.c
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-0.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-1.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-2.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-3.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-4.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available.c
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-0.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-1.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-2.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-3.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-4.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-0.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-1.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-2.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-3.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-4.exp
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.c
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-sanity.c
create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp
create mode 100644 gdb/testsuite/lib/aarch64.exp
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp b/gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp
new file mode 100644
index 00000000000..c4755346bc8
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 0
+set id_end 24
+source $srcdir/$subdir/aarch64-sme-core.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp b/gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp
new file mode 100644
index 00000000000..6461c47d6b5
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 25
+set id_end 49
+source $srcdir/$subdir/aarch64-sme-core.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp b/gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp
new file mode 100644
index 00000000000..e5bf5bf2b84
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 50
+set id_end 74
+source $srcdir/$subdir/aarch64-sme-core.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp b/gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp
new file mode 100644
index 00000000000..1846c83a63c
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 75
+set id_end 99
+source $srcdir/$subdir/aarch64-sme-core.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp b/gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp
new file mode 100644
index 00000000000..45e69fa8ad5
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 100
+set id_end 124
+source $srcdir/$subdir/aarch64-sme-core.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core.c b/gdb/testsuite/gdb.arch/aarch64-sme-core.c
new file mode 100644
index 00000000000..7d4284b80c8
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-core.c
@@ -0,0 +1,361 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2023 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Exercise AArch64's Scalable Vector/Matrix Extension core file generation
+ for GDB. This includes reading Linux Kernel-generated core files and
+ writing GDB core files via the gcore command and making sure the contents
+ are sane. */
+
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <sys/prctl.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#ifndef HWCAP_SVE
+#define HWCAP_SVE (1 << 22)
+#endif
+
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
+#ifndef PR_SVE_SET_VL
+#define PR_SVE_SET_VL 50
+#define PR_SVE_GET_VL 51
+#define PR_SVE_VL_LEN_MASK 0xffff
+#endif
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#define PR_SME_GET_VL 64
+#define PR_SME_VL_LEN_MASK 0xffff
+#endif
+
+static void
+enable_za ()
+{
+ /* smstart za */
+ __asm __volatile (".word 0xD503457F");
+}
+
+static void
+disable_za ()
+{
+ /* smstop za */
+ __asm __volatile (".word 0xD503447F");
+}
+
+static void
+enable_sm ()
+{
+ /* smstart sm */
+ __asm __volatile (".word 0xD503437F");
+}
+
+static void
+disable_sm ()
+{
+ /* smstop sm */
+ __asm __volatile (".word 0xD503427F");
+}
+
+static void
+initialize_fpsimd_state ()
+{
+ char buffer[16];
+
+ for (int i = 0; i < 16; i++)
+ buffer[i] = 0x55;
+
+ __asm __volatile ("mov x0, %0\n\t" \
+ : : "r" (buffer));
+
+ __asm __volatile ("ldr q0, [x0]");
+ __asm __volatile ("ldr q1, [x0]");
+ __asm __volatile ("ldr q2, [x0]");
+ __asm __volatile ("ldr q3, [x0]");
+ __asm __volatile ("ldr q4, [x0]");
+ __asm __volatile ("ldr q5, [x0]");
+ __asm __volatile ("ldr q6, [x0]");
+ __asm __volatile ("ldr q7, [x0]");
+ __asm __volatile ("ldr q8, [x0]");
+ __asm __volatile ("ldr q9, [x0]");
+ __asm __volatile ("ldr q10, [x0]");
+ __asm __volatile ("ldr q11, [x0]");
+ __asm __volatile ("ldr q12, [x0]");
+ __asm __volatile ("ldr q13, [x0]");
+ __asm __volatile ("ldr q14, [x0]");
+ __asm __volatile ("ldr q15, [x0]");
+ __asm __volatile ("ldr q16, [x0]");
+ __asm __volatile ("ldr q17, [x0]");
+ __asm __volatile ("ldr q18, [x0]");
+ __asm __volatile ("ldr q19, [x0]");
+ __asm __volatile ("ldr q20, [x0]");
+ __asm __volatile ("ldr q21, [x0]");
+ __asm __volatile ("ldr q22, [x0]");
+ __asm __volatile ("ldr q23, [x0]");
+ __asm __volatile ("ldr q24, [x0]");
+ __asm __volatile ("ldr q25, [x0]");
+ __asm __volatile ("ldr q26, [x0]");
+ __asm __volatile ("ldr q27, [x0]");
+ __asm __volatile ("ldr q28, [x0]");
+ __asm __volatile ("ldr q29, [x0]");
+ __asm __volatile ("ldr q30, [x0]");
+ __asm __volatile ("ldr q31, [x0]");
+}
+
+static void
+initialize_za_state ()
+{
+ /* zero za */
+ __asm __volatile (".word 0xC00800FF");
+
+ char buffer[256];
+
+ for (int i = 0; i < 256; i++)
+ buffer[i] = 0xaa;
+
+ __asm __volatile ("mov x0, %0\n\t" \
+ : : "r" (buffer));
+
+ /* Initialize loop boundaries. */
+ __asm __volatile ("mov w12, 0");
+ __asm __volatile ("mov w17, 256");
+
+ /* loop: ldr za[w12, 0], [x0] */
+ __asm __volatile ("loop: .word 0xe1000000");
+ __asm __volatile ("add w12, w12, 1");
+ __asm __volatile ("cmp w12, w17");
+ __asm __volatile ("bne loop");
+}
+
+static void
+initialize_sve_state ()
+{
+ __asm __volatile ("dup z0.b, -1");
+ __asm __volatile ("dup z1.b, -1");
+ __asm __volatile ("dup z2.b, -1");
+ __asm __volatile ("dup z3.b, -1");
+ __asm __volatile ("dup z4.b, -1");
+ __asm __volatile ("dup z5.b, -1");
+ __asm __volatile ("dup z6.b, -1");
+ __asm __volatile ("dup z7.b, -1");
+ __asm __volatile ("dup z8.b, -1");
+ __asm __volatile ("dup z9.b, -1");
+ __asm __volatile ("dup z10.b, -1");
+ __asm __volatile ("dup z11.b, -1");
+ __asm __volatile ("dup z12.b, -1");
+ __asm __volatile ("dup z13.b, -1");
+ __asm __volatile ("dup z14.b, -1");
+ __asm __volatile ("dup z15.b, -1");
+ __asm __volatile ("dup z16.b, -1");
+ __asm __volatile ("dup z17.b, -1");
+ __asm __volatile ("dup z18.b, -1");
+ __asm __volatile ("dup z19.b, -1");
+ __asm __volatile ("dup z20.b, -1");
+ __asm __volatile ("dup z21.b, -1");
+ __asm __volatile ("dup z22.b, -1");
+ __asm __volatile ("dup z23.b, -1");
+ __asm __volatile ("dup z24.b, -1");
+ __asm __volatile ("dup z25.b, -1");
+ __asm __volatile ("dup z26.b, -1");
+ __asm __volatile ("dup z27.b, -1");
+ __asm __volatile ("dup z28.b, -1");
+ __asm __volatile ("dup z29.b, -1");
+ __asm __volatile ("dup z30.b, -1");
+ __asm __volatile ("dup z31.b, -1");
+ __asm __volatile ("ptrue p0.b");
+ __asm __volatile ("ptrue p1.b");
+ __asm __volatile ("ptrue p2.b");
+ __asm __volatile ("ptrue p3.b");
+ __asm __volatile ("ptrue p4.b");
+ __asm __volatile ("ptrue p5.b");
+ __asm __volatile ("ptrue p6.b");
+ __asm __volatile ("ptrue p7.b");
+ __asm __volatile ("ptrue p8.b");
+ __asm __volatile ("ptrue p9.b");
+ __asm __volatile ("ptrue p10.b");
+ __asm __volatile ("ptrue p11.b");
+ __asm __volatile ("ptrue p12.b");
+ __asm __volatile ("ptrue p13.b");
+ __asm __volatile ("ptrue p14.b");
+ __asm __volatile ("ptrue p15.b");
+ __asm __volatile ("setffr");
+}
+
+static int get_vl_size ()
+{
+ int res = prctl (PR_SVE_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int get_svl_size ()
+{
+ int res = prctl (PR_SME_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int set_vl_size (int new_vl)
+{
+ int res = prctl (PR_SVE_SET_VL, new_vl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_vl_size ();
+ if (res != new_vl)
+ {
+ printf ("Unexpected VL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+static int set_svl_size (int new_svl)
+{
+ int res = prctl (PR_SME_SET_VL, new_svl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_svl_size ();
+ if (res != new_svl)
+ {
+ printf ("Unexpected SVL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+/* Enable register states based on STATE.
+
+ 0 - FPSIMD
+ 1 - SVE
+ 2 - SSVE
+ 3 - ZA
+ 4 - ZA and SSVE. */
+
+void enable_states (int state)
+{
+ disable_za ();
+ disable_sm ();
+ initialize_fpsimd_state ();
+
+ if (state == 1)
+ {
+ initialize_sve_state ();
+ }
+ else if (state == 2)
+ {
+ enable_sm ();
+ initialize_sve_state ();
+ }
+ else if (state == 3)
+ {
+ enable_za ();
+ initialize_za_state ();
+ }
+ else if (state == 4)
+ {
+ enable_za ();
+ enable_sm ();
+ initialize_sve_state ();
+ initialize_za_state ();
+ }
+
+ return;
+}
+
+static int
+test_id_to_state (int id)
+{
+ return id / 25;
+}
+
+static int
+test_id_to_vl (int id)
+{
+ return 16 << ((id / 5) % 5);
+}
+
+static int
+test_id_to_svl (int id)
+{
+ return 16 << (id % 5);
+}
+
+static void
+dummy ()
+{
+}
+
+int
+main (int argc, char **argv)
+{
+ if (argc > 2)
+ printf ("Incorrect number of arguments passed to test.\n");
+
+ if (getauxval (AT_HWCAP) & HWCAP_SVE && getauxval (AT_HWCAP2) & HWCAP2_SME)
+ {
+ long test_id = 0;
+
+ /* If we have a test id passed as argument, read it now. */
+ if (argc == 2)
+ test_id = strtol (argv[1], NULL, 0);
+
+ dummy (); /* stop to initialize test_id */
+
+ int state = test_id_to_state (test_id);
+ int vl = test_id_to_vl (test_id);
+ int svl = test_id_to_svl (test_id);
+
+ if (set_vl_size (vl) == -1)
+ return -1;
+ if (set_svl_size (svl) == -1)
+ return -1;
+
+ enable_states (state);
+
+ char *p = 0x0;
+ *p = 0xff; /* crash point */
+ }
+ else
+ {
+ printf ("SKIP: no HWCAP_SVE or HWCAP2_SME on this system\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl
new file mode 100644
index 00000000000..1fc325d4df7
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl
@@ -0,0 +1,167 @@
+# Copyright (C) 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Exercise core file reading/writing in the presence of SME support.
+# This test exercises GDB's dumping/loading capability for Linux
+# Kernel core files and for gcore core files.
+
+load_lib aarch64.exp
+
+#
+# Validate that CORE_FILENAME can be read correctly and that the register
+# state is sane.
+#
+proc check_sme_core_file { core_filename state vl svl } {
+ # Load the core file.
+ if [gdb_test "core $core_filename" \
+ [multi_line \
+ "Core was generated by.*\." \
+ "Program terminated with signal SIGSEGV, Segmentation fault\." \
+ "#0 ${::hex} in main \\(.*\\) at .*" \
+ ".*p = 0xff;.* crash point .*"] \
+ "load core file"] {
+ untested "failed to generate core file"
+ return -1
+ }
+
+ check_state $state $vl $svl
+
+ # Check the value of TPIDR2 in the core file.
+ gdb_test "print/x \$tpidr2" " = 0x1f2f3f4f5f6f7f8f" "tpidr2 contents from core file"
+}
+
+#
+# Generate two core files for EXECUTABLE, BINFILE with a test id of ID.
+# STATE is the register state, VL is the SVE vector length and SVL is the
+# SME vector length.
+# One of the core files is generated by the kernel and the other by the
+# gcore command.
+#
+proc generate_sme_core_files { executable binfile id state vl svl} {
+ # Run the program until the point where we need to adjust the
+ # test id.
+ set init_breakpoint "stop to initialize test_id"
+ gdb_breakpoint [gdb_get_line_number $init_breakpoint]
+ gdb_continue_to_breakpoint $init_breakpoint
+ gdb_test_no_output "set test_id = $id"
+
+ # Run the program until just before the crash.
+ set crash_breakpoint "crash point"
+ gdb_breakpoint [gdb_get_line_number $crash_breakpoint]
+ gdb_continue_to_breakpoint $crash_breakpoint
+ gdb_test_no_output "set print repeats 1" "adjust repeat count pre-crash"
+
+ # Adjust the register to custom values that we will check later when
+ # loading the core files.
+ check_state $state $vl $svl
+
+ # Modify tpidr2 so we can validate its value is properly dumped to the
+ # core files.
+ gdb_test_no_output "set \$tpidr2 = 0x1f2f3f4f5f6f7f8f"
+
+ # Continue until a crash.
+ gdb_test "continue" \
+ [multi_line \
+ "Program received signal SIGSEGV, Segmentation fault\." \
+ "${::hex} in main \\(.*\\) at .*" \
+ ".*p = 0xff;.* crash point .*"] \
+ "run to crash"
+
+ # Generate the gcore core file.
+ set gcore_filename [standard_output_file "${executable}-${id}-${state}-${vl}-${svl}.gcore"]
+ set gcore_generated [gdb_gcore_cmd "$gcore_filename" "generate gcore file"]
+
+ # Continue until the end.
+ gdb_test "continue" "Program terminated with signal SIGSEGV.*" \
+ "program terminated with SIGSEGV"
+
+ # Generate a native core file.
+ set core_filename [core_find ${binfile} {} $id]
+ set core_generated [expr {$core_filename != ""}]
+ set native_core_name "${binfile}-${id}-${state}-${vl}-${svl}.core"
+ remote_exec build "mv $core_filename ${native_core_name}"
+ set core_filename ${native_core_name}
+
+ # At this point we have a couple core files, the gcore one generated by GDB
+ # and the native one generated by the Linux Kernel. Make sure GDB can read
+ # both correctly.
+ if {$gcore_generated} {
+ clean_restart ${binfile}
+ gdb_test_no_output "set print repeats 1" \
+ "adjust repeat count post-crash gcore"
+
+ with_test_prefix "gcore corefile" {
+ check_sme_core_file $gcore_filename $state $vl $svl
+ }
+ } else {
+ fail "gcore corefile not generated"
+ }
+
+ if {$core_generated} {
+ clean_restart ${binfile}
+
+ gdb_test_no_output "set print repeats 1" \
+ "adjust repeat count post-crash native core"
+
+ with_test_prefix "native corefile" {
+ check_sme_core_file $core_filename $state $vl $svl
+ }
+ } else {
+ untested "native corefile not generated"
+ }
+}
+
+#
+# Exercise core file reading (kernel-generated core files) and writing
+# (gcore command) for test id's ID_START through ID_END.
+#
+proc test_sme_core_file { id_start id_end } {
+ set compile_flags {"debug" "macros" "additional_flags=-march=armv8.5-a+sve"}
+ standard_testfile ${::srcdir}/${::subdir}/aarch64-sme-core.c
+ set executable "${::testfile}"
+ if {[prepare_for_testing "failed to prepare" ${executable} ${::srcfile} ${compile_flags}]} {
+ return -1
+ }
+ set binfile [standard_output_file ${executable}]
+
+ for {set id $id_start} {$id <= $id_end} {incr id} {
+ set state [test_id_to_state $id]
+ set vl [test_id_to_vl $id]
+ set svl [test_id_to_svl $id]
+
+ with_test_prefix "state=${state} vl=${vl} svl=${svl}" {
+ if ![runto_main] {
+ untested "could not run to main"
+ return -1
+ }
+
+ generate_sme_core_files ${executable} ${binfile} $id $state $vl $svl
+ }
+ }
+}
+
+require is_aarch64_target
+
+if {![allow_aarch64_sve_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+if {![allow_aarch64_sme_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+test_sme_core_file $id_start $id_end
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-0.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-0.exp
new file mode 100644
index 00000000000..b264170c56a
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-0.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 0
+set id_end 4
+source $srcdir/$subdir/aarch64-sme-regs-available.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-1.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-1.exp
new file mode 100644
index 00000000000..ac48aa905bc
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-1.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 5
+set id_end 9
+source $srcdir/$subdir/aarch64-sme-regs-available.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-2.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-2.exp
new file mode 100644
index 00000000000..0e8f3e311ee
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-2.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 10
+set id_end 14
+source $srcdir/$subdir/aarch64-sme-regs-available.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-3.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-3.exp
new file mode 100644
index 00000000000..fabb24c5aad
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-3.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 14
+set id_end 19
+source $srcdir/$subdir/aarch64-sme-regs-available.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-4.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-4.exp
new file mode 100644
index 00000000000..5abeabb74c4
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available-4.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 20
+set id_end 24
+source $srcdir/$subdir/aarch64-sme-regs-available.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.c b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.c
new file mode 100644
index 00000000000..bf27356908f
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.c
@@ -0,0 +1,184 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2023 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Exercise various cases of reading/writing ZA contents for AArch64's
+ Scalable Matrix Extension. */
+
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <sys/prctl.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#ifndef HWCAP_SVE
+#define HWCAP_SVE (1 << 22)
+#endif
+
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
+#ifndef PR_SVE_SET_VL
+#define PR_SVE_SET_VL 50
+#define PR_SVE_GET_VL 51
+#define PR_SVE_VL_LEN_MASK 0xffff
+#endif
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#define PR_SME_GET_VL 64
+#define PR_SME_VL_LEN_MASK 0xffff
+#endif
+
+static void
+enable_za ()
+{
+ /* smstart za */
+ __asm __volatile (".word 0xD503457F");
+}
+
+static void
+disable_za ()
+{
+ /* smstop za */
+ __asm __volatile (".word 0xD503447F");
+}
+
+static int get_vl_size ()
+{
+ int res = prctl (PR_SVE_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int get_svl_size ()
+{
+ int res = prctl (PR_SME_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int set_vl_size (int new_vl)
+{
+ int res = prctl (PR_SVE_SET_VL, new_vl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_vl_size ();
+ if (res != new_vl)
+ {
+ printf ("Unexpected VL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+static int set_svl_size (int new_svl)
+{
+ int res = prctl (PR_SME_SET_VL, new_svl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_svl_size ();
+ if (res != new_svl)
+ {
+ printf ("Unexpected SVL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+static int
+test_id_to_vl (int id)
+{
+ return 16 << ((id / 5) % 5);
+}
+
+static int
+test_id_to_svl (int id)
+{
+ return 16 << (id % 5);
+}
+
+static void
+dummy ()
+{
+}
+
+int
+main (int argc, char **argv)
+{
+ if (getauxval (AT_HWCAP) & HWCAP_SVE && getauxval (AT_HWCAP2) & HWCAP2_SME)
+ {
+ int id_start = ID_START;
+ int id_end = ID_END;
+
+ for (int id = id_start; id <= id_end; id++)
+ {
+ int vl = test_id_to_vl (id);
+ int svl = test_id_to_svl (id);
+
+ if (set_vl_size (vl) == -1)
+ return -1;
+ if (set_svl_size (svl) == -1)
+ return -1;
+
+ enable_za ();
+ dummy (); /* stop 1 */
+ }
+
+ for (int id = id_start; id <= id_end; id++)
+ {
+ int vl = test_id_to_vl (id);
+ int svl = test_id_to_svl (id);
+
+ /* Make sure the vl/svl is something other than what gdb is about
+ to set them to. */
+ if (set_vl_size (vl == 16? 32 : vl) == -1)
+ return -1;
+ if (set_svl_size (svl == 16? 32 : svl) == -1)
+ return -1;
+
+ disable_za ();
+ dummy (); /* stop 2 */
+ }
+ }
+ else
+ {
+ printf ("SKIP: no HWCAP_SVE or HWCAP2_SME on this system\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl
new file mode 100644
index 00000000000..19131819273
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl
@@ -0,0 +1,194 @@
+# Copyright (C) 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Exercise reading/writing ZA registers when there is ZA state.
+
+load_lib aarch64.exp
+
+#
+# Cycle through all ZA registers and pseudo-registers and validate that their
+# contents are available for vector length SVL.
+#
+# Make sure reading/writing to ZA registers work as expected.
+#
+proc check_regs { mode vl svl } {
+ # Check VG to make sure it is correct
+ set expected_vg [expr $vl / 8]
+ gdb_test "print \$vg" "= ${expected_vg}"
+
+ # Check SVG to make sure it is correct
+ set expected_svg [expr $svl / 8]
+ gdb_test "print \$svg" "= ${expected_svg}"
+
+ # If svl is adjusted by prctl, we will have ZA enabled. If gdb is
+ # adjusting svl, ZA will not be enabled by default. It will only be
+ # enabled when ZA is written to.
+ set za_state "= \\\[ ZA \\\]"
+ if {$mode == "gdb"} {
+ set za_state "= \\\[ \\\]"
+ }
+
+ # Check SVCR.
+ if [gdb_test "print \$svcr" $za_state "svcr before assignments" ] {
+ fail "incorrect za state"
+ return -1
+ }
+
+ # Check the size of ZA.
+ set expected_za_size [expr $svl * $svl]
+ gdb_test "print sizeof \$za" " = $expected_za_size"
+
+ # Check the size of Z0.
+ gdb_test "print sizeof \$z0" " = $vl"
+
+ # Exercise reading/writing from/to ZA.
+ initialize_2d_array "\$za" 255 $svl $svl
+ set pattern [string_to_regexp [2d_array_value_pattern 255 $svl $svl]]
+ gdb_test "print \$za" " = $pattern" "read back from za"
+
+ # Exercise reading/writing from/to the tile pseudo-registers.
+ set last_tile 1
+ set expected_size [expr $svl * $svl]
+ set tile_svl $svl
+ set za_state "= \\\[ ZA \\\]"
+ foreach_with_prefix granularity {"b" "h" "s" "d" "q"} {
+ for {set tile 0} {$tile < $last_tile} {incr tile} {
+ set register_name "\$za${tile}${granularity}"
+
+ # Test the size.
+ gdb_test "print sizeof ${register_name}" " = ${expected_size}"
+
+ # Test reading/writing
+ initialize_2d_array $register_name 255 $tile_svl $tile_svl
+
+ # Make sure we have ZA state.
+ if [gdb_test "print \$svcr" $za_state "svcr after assignment to ${register_name}" ] {
+ fail "incorrect za state"
+ return -1
+ }
+
+ set pattern [string_to_regexp [2d_array_value_pattern 255 $tile_svl $tile_svl]]
+ gdb_test "print $register_name" " = $pattern" "read back from $register_name"
+ }
+ set last_tile [expr $last_tile * 2]
+ set expected_size [expr $expected_size / 2]
+ set tile_svl [expr $tile_svl / 2]
+ }
+
+ # Exercise reading/writing from/to the tile slice pseudo-registers.
+ set last_tile 1
+ set last_slice $svl
+ set expected_size $svl
+ set num_elements $svl
+ foreach_with_prefix granularity {"b" "h" "s" "d" "q"} {
+ for {set tile 0} {$tile < $last_tile} {incr tile} {
+ for {set slice 0} {$slice < $last_slice} {incr slice} {
+ foreach_with_prefix direction {"h" "v"} {
+ set register_name "\$za${tile}${direction}${granularity}${slice}"
+
+ # Test the size.
+ gdb_test "print sizeof ${register_name}" " = ${expected_size}"
+
+ # Test reading/writing
+ initialize_1d_array $register_name 255 $num_elements
+
+ # Make sure we have ZA state.
+ if [gdb_test "print \$svcr" $za_state "svcr after assignment of ${register_name}" ] {
+ fail "incorrect za state"
+ return -1
+ }
+
+ set pattern [string_to_regexp [1d_array_value_pattern 255 $num_elements]]
+ gdb_test "print $register_name" " = $pattern" "read back from $register_name"
+ }
+ }
+ }
+ set last_tile [expr $last_tile * 2]
+ set last_slice [expr ($last_slice / 2)]
+ set num_elements [expr $num_elements / 2]
+ }
+}
+
+#
+# Cycle through all ZA registers and pseudo-registers and validate their
+# contents.
+#
+proc test_sme_registers_available { id_start id_end } {
+
+ set compile_flags {"debug" "macros"}
+ lappend compile_flags "additional_flags=-DID_START=${id_start}"
+ lappend compile_flags "additional_flags=-DID_END=${id_end}"
+
+ standard_testfile ${::srcdir}/${::subdir}/aarch64-sme-regs-available.c
+ set executable "${::testfile}-${id_start}-${id_end}"
+ if {[prepare_for_testing "failed to prepare" ${executable} ${::srcfile} ${compile_flags}]} {
+ return -1
+ }
+ set binfile [standard_output_file ${executable}]
+
+ if ![runto_main] {
+ untested "could not run to main"
+ return -1
+ }
+
+ gdb_test_no_output "set print repeats 1"
+
+ set prctl_breakpoint "stop 1"
+ gdb_breakpoint [gdb_get_line_number $prctl_breakpoint]
+
+ for {set id $id_start} {$id <= $id_end} {incr id} {
+ set vl [test_id_to_vl $id]
+ set svl [test_id_to_svl $id]
+ set mode "prctl"
+ with_test_prefix "$mode, vl=${vl} svl=${svl}" {
+ # Run the program until it has adjusted svl.
+ gdb_continue_to_breakpoint $prctl_breakpoint
+ check_regs $mode $vl $svl
+ }
+ }
+
+ set non_prctl_breakpoint "stop 2"
+ gdb_breakpoint [gdb_get_line_number $non_prctl_breakpoint]
+ gdb_continue_to_breakpoint $non_prctl_breakpoint
+
+ for {set id $id_start} {$id <= $id_end} {incr id} {
+ set vl [test_id_to_vl $id]
+ set svl [test_id_to_svl $id]
+ set mode "gdb"
+ with_test_prefix "$mode, vl=${vl} svl=${svl}" {
+ # Adjust svl via gdb.
+ set vg_value [expr $vl / 8]
+ set svg_value [expr $svl / 8]
+ gdb_test_no_output "set \$vg = ${vg_value}"
+ gdb_test_no_output "set \$svg = ${svg_value}"
+
+ check_regs $mode $vl $svl
+ }
+ }
+}
+
+require is_aarch64_target
+
+if {![allow_aarch64_sve_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+if {![allow_aarch64_sme_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+test_sme_registers_available $id_start $id_end
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-0.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-0.exp
new file mode 100644
index 00000000000..00b29deed98
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-0.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 0
+set id_end 24
+source $srcdir/$subdir/aarch64-sme-regs-sigframe.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-1.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-1.exp
new file mode 100644
index 00000000000..991efce4f25
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-1.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 25
+set id_end 49
+source $srcdir/$subdir/aarch64-sme-regs-sigframe.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-2.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-2.exp
new file mode 100644
index 00000000000..5bd3cb80861
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-2.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 50
+set id_end 74
+source $srcdir/$subdir/aarch64-sme-regs-sigframe.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-3.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-3.exp
new file mode 100644
index 00000000000..6e9cf9e929b
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-3.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 75
+set id_end 99
+source $srcdir/$subdir/aarch64-sme-regs-sigframe.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-4.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-4.exp
new file mode 100644
index 00000000000..0a9a11c30a2
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-4.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 100
+set id_end 124
+source $srcdir/$subdir/aarch64-sme-regs-sigframe.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c
new file mode 100644
index 00000000000..4d178ec01f6
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c
@@ -0,0 +1,368 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2023 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Exercise AArch64's Scalable Vector/Matrix Extension signal frame handling
+ for GDB. */
+
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <sys/prctl.h>
+#include <stdlib.h>
+#include <string.h>
+#include <signal.h>
+#include <unistd.h>
+
+#ifndef HWCAP_SVE
+#define HWCAP_SVE (1 << 22)
+#endif
+
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
+#ifndef PR_SVE_SET_VL
+#define PR_SVE_SET_VL 50
+#define PR_SVE_GET_VL 51
+#define PR_SVE_VL_LEN_MASK 0xffff
+#endif
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#define PR_SME_GET_VL 64
+#define PR_SME_VL_LEN_MASK 0xffff
+#endif
+
+static int count = 0;
+
+static void
+handler (int sig)
+{
+ count++; /* handler */
+}
+
+static void
+enable_za ()
+{
+ /* smstart za */
+ __asm __volatile (".word 0xD503457F");
+}
+
+static void
+disable_za ()
+{
+ /* smstop za */
+ __asm __volatile (".word 0xD503447F");
+}
+
+static void
+enable_sm ()
+{
+ /* smstart sm */
+ __asm __volatile (".word 0xD503437F");
+}
+
+static void
+disable_sm ()
+{
+ /* smstop sm */
+ __asm __volatile (".word 0xD503427F");
+}
+
+static void
+initialize_fpsimd_state ()
+{
+ char buffer[16];
+
+ for (int i = 0; i < 16; i++)
+ buffer[i] = 0x55;
+
+ __asm __volatile ("mov x0, %0\n\t" \
+ : : "r" (buffer));
+
+ __asm __volatile ("ldr q0, [x0]");
+ __asm __volatile ("ldr q1, [x0]");
+ __asm __volatile ("ldr q2, [x0]");
+ __asm __volatile ("ldr q3, [x0]");
+ __asm __volatile ("ldr q4, [x0]");
+ __asm __volatile ("ldr q5, [x0]");
+ __asm __volatile ("ldr q6, [x0]");
+ __asm __volatile ("ldr q7, [x0]");
+ __asm __volatile ("ldr q8, [x0]");
+ __asm __volatile ("ldr q9, [x0]");
+ __asm __volatile ("ldr q10, [x0]");
+ __asm __volatile ("ldr q11, [x0]");
+ __asm __volatile ("ldr q12, [x0]");
+ __asm __volatile ("ldr q13, [x0]");
+ __asm __volatile ("ldr q14, [x0]");
+ __asm __volatile ("ldr q15, [x0]");
+ __asm __volatile ("ldr q16, [x0]");
+ __asm __volatile ("ldr q17, [x0]");
+ __asm __volatile ("ldr q18, [x0]");
+ __asm __volatile ("ldr q19, [x0]");
+ __asm __volatile ("ldr q20, [x0]");
+ __asm __volatile ("ldr q21, [x0]");
+ __asm __volatile ("ldr q22, [x0]");
+ __asm __volatile ("ldr q23, [x0]");
+ __asm __volatile ("ldr q24, [x0]");
+ __asm __volatile ("ldr q25, [x0]");
+ __asm __volatile ("ldr q26, [x0]");
+ __asm __volatile ("ldr q27, [x0]");
+ __asm __volatile ("ldr q28, [x0]");
+ __asm __volatile ("ldr q29, [x0]");
+ __asm __volatile ("ldr q30, [x0]");
+ __asm __volatile ("ldr q31, [x0]");
+}
+
+static void
+initialize_za_state ()
+{
+ /* zero za */
+ __asm __volatile (".word 0xC00800FF");
+
+ char buffer[256];
+
+ for (int i = 0; i < 256; i++)
+ buffer[i] = 0xaa;
+
+ __asm __volatile ("mov x0, %0\n\t" \
+ : : "r" (buffer));
+
+ /* Initialize loop boundaries. */
+ __asm __volatile ("mov w12, 0");
+ __asm __volatile ("mov w17, 256");
+
+ /* loop: ldr za[w12, 0], [x0] */
+ __asm __volatile ("loop: .word 0xe1000000");
+ __asm __volatile ("add w12, w12, 1");
+ __asm __volatile ("cmp w12, w17");
+ __asm __volatile ("bne loop");
+}
+
+static void
+initialize_sve_state ()
+{
+ __asm __volatile ("dup z0.b, -1");
+ __asm __volatile ("dup z1.b, -1");
+ __asm __volatile ("dup z2.b, -1");
+ __asm __volatile ("dup z3.b, -1");
+ __asm __volatile ("dup z4.b, -1");
+ __asm __volatile ("dup z5.b, -1");
+ __asm __volatile ("dup z6.b, -1");
+ __asm __volatile ("dup z7.b, -1");
+ __asm __volatile ("dup z8.b, -1");
+ __asm __volatile ("dup z9.b, -1");
+ __asm __volatile ("dup z10.b, -1");
+ __asm __volatile ("dup z11.b, -1");
+ __asm __volatile ("dup z12.b, -1");
+ __asm __volatile ("dup z13.b, -1");
+ __asm __volatile ("dup z14.b, -1");
+ __asm __volatile ("dup z15.b, -1");
+ __asm __volatile ("dup z16.b, -1");
+ __asm __volatile ("dup z17.b, -1");
+ __asm __volatile ("dup z18.b, -1");
+ __asm __volatile ("dup z19.b, -1");
+ __asm __volatile ("dup z20.b, -1");
+ __asm __volatile ("dup z21.b, -1");
+ __asm __volatile ("dup z22.b, -1");
+ __asm __volatile ("dup z23.b, -1");
+ __asm __volatile ("dup z24.b, -1");
+ __asm __volatile ("dup z25.b, -1");
+ __asm __volatile ("dup z26.b, -1");
+ __asm __volatile ("dup z27.b, -1");
+ __asm __volatile ("dup z28.b, -1");
+ __asm __volatile ("dup z29.b, -1");
+ __asm __volatile ("dup z30.b, -1");
+ __asm __volatile ("dup z31.b, -1");
+ __asm __volatile ("ptrue p0.b");
+ __asm __volatile ("ptrue p1.b");
+ __asm __volatile ("ptrue p2.b");
+ __asm __volatile ("ptrue p3.b");
+ __asm __volatile ("ptrue p4.b");
+ __asm __volatile ("ptrue p5.b");
+ __asm __volatile ("ptrue p6.b");
+ __asm __volatile ("ptrue p7.b");
+ __asm __volatile ("ptrue p8.b");
+ __asm __volatile ("ptrue p9.b");
+ __asm __volatile ("ptrue p10.b");
+ __asm __volatile ("ptrue p11.b");
+ __asm __volatile ("ptrue p12.b");
+ __asm __volatile ("ptrue p13.b");
+ __asm __volatile ("ptrue p14.b");
+ __asm __volatile ("ptrue p15.b");
+ __asm __volatile ("setffr");
+}
+
+static int get_vl_size ()
+{
+ int res = prctl (PR_SVE_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int get_svl_size ()
+{
+ int res = prctl (PR_SME_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int set_vl_size (int new_vl)
+{
+ int res = prctl (PR_SVE_SET_VL, new_vl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_vl_size ();
+ if (res != new_vl)
+ {
+ printf ("Unexpected VL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+static int set_svl_size (int new_svl)
+{
+ int res = prctl (PR_SME_SET_VL, new_svl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_svl_size ();
+ if (res != new_svl)
+ {
+ printf ("Unexpected SVL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+/* Enable register states based on STATE.
+
+ 0 - FPSIMD
+ 1 - SVE
+ 2 - SSVE
+ 3 - ZA
+ 4 - ZA and SSVE. */
+
+void enable_states (int state)
+{
+ disable_za ();
+ disable_sm ();
+ initialize_fpsimd_state ();
+
+ if (state == 1)
+ {
+ initialize_sve_state ();
+ }
+ else if (state == 2)
+ {
+ enable_sm ();
+ initialize_sve_state ();
+ }
+ else if (state == 3)
+ {
+ enable_za ();
+ initialize_za_state ();
+ }
+ else if (state == 4)
+ {
+ enable_za ();
+ enable_sm ();
+ initialize_sve_state ();
+ initialize_za_state ();
+ }
+
+ return;
+}
+
+static int
+test_id_to_state (int id)
+{
+ return (id / 25);
+}
+
+static int
+test_id_to_vl (int id)
+{
+ return 16 << ((id / 5) % 5);
+}
+
+static int
+test_id_to_svl (int id)
+{
+ return 16 << (id % 5);
+}
+
+static void
+dummy ()
+{
+}
+
+int
+main (int argc, char **argv)
+{
+ if (getauxval (AT_HWCAP) & HWCAP_SVE && getauxval (AT_HWCAP2) & HWCAP2_SME)
+ {
+ int id_start = ID_START;
+ int id_end = ID_END;
+#ifdef SIGILL
+ signal (SIGILL, handler);
+#endif
+
+ int signal_count = 0;
+ for (int id = id_start; id <= id_end; id++)
+ {
+ int state = test_id_to_state (id);
+ int vl = test_id_to_vl (id);
+ int svl = test_id_to_svl (id);
+
+ if (set_vl_size (vl) == -1)
+ return -1;
+ if (set_svl_size (svl) == -1)
+ return -1;
+
+ signal_count++;
+ enable_states (state);
+ dummy (); /* stop before SIGILL */
+ __asm __volatile (".word 0xDEADBEEF"); /* illegal instruction */
+ while (signal_count != count);
+ }
+ }
+ else
+ {
+ printf ("SKIP: no HWCAP_SVE or HWCAP2_SME on this system\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl
new file mode 100644
index 00000000000..4279cdc6d9b
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl
@@ -0,0 +1,156 @@
+# Copyright (C) 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Exercise restoring SME/TPIDR2 state from a signal frame.
+
+load_lib aarch64.exp
+
+#
+# Validate the state of registers in the signal frame for various states.
+#
+proc test_sme_registers_sigframe { id_start id_end } {
+
+ set compile_flags {"debug" "macros"}
+ lappend compile_flags "additional_flags=-march=armv8.5-a+sve"
+ lappend compile_flags "additional_flags=-DID_START=${id_start}"
+ lappend compile_flags "additional_flags=-DID_END=${id_end}"
+
+ standard_testfile ${::srcdir}/${::subdir}/aarch64-sme-regs-sigframe.c
+ set executable "${::testfile}-${id_start}-${id_end}"
+ if {[prepare_for_testing "failed to prepare" ${executable} ${::srcfile} ${compile_flags}]} {
+ return -1
+ }
+ set binfile [standard_output_file ${executable}]
+
+ if ![runto_main] {
+ untested "could not run to main"
+ return -1
+ }
+
+ set sigill_breakpoint "stop before SIGILL"
+ set handler_breakpoint "handler"
+ gdb_breakpoint [gdb_get_line_number $sigill_breakpoint]
+ gdb_breakpoint [gdb_get_line_number $handler_breakpoint]
+
+ for {set id $id_start} {$id <= $id_end} {incr id} {
+ set state [test_id_to_state $id]
+ set vl [test_id_to_vl $id]
+ set svl [test_id_to_svl $id]
+
+ with_test_prefix "state=${state} vl=${vl} svl=${svl}" {
+
+ # Run the program until it has adjusted the svl.
+ if [gdb_continue_to_breakpoint $sigill_breakpoint] {
+ return -1
+ }
+
+ # Check SVG to make sure it is correct
+ set expected_svg [expr $svl / 8]
+ gdb_test "print \$svg" "= ${expected_svg}"
+
+ # Check the size of ZA.
+ set expected_za_size [expr $svl * $svl]
+ gdb_test "print sizeof \$za" " = $expected_za_size"
+
+ # Check the value of SVCR.
+ gdb_test "print \$svcr" [get_svcr_value $state] "svcr before signal"
+
+ # Handle SME ZA initialization and state.
+ set byte 0
+ if { $state == "za" || $state == "za_ssve" } {
+ set byte 170
+ }
+
+ # Set the expected ZA pattern.
+ set za_pattern [string_to_regexp [2d_array_value_pattern $byte $svl $svl]]
+
+ # Handle SVE/SSVE initialization and state.
+ set sve_vl $svl
+ if { $state == "ssve" || $state == "za_ssve" } {
+ # SVE state comes from SSVE.
+ set sve_vl $svl
+ } else {
+ # SVE state comes from regular SVE.
+ set sve_vl $vl
+ }
+
+ # Initialize the SVE state.
+ set sve_pattern [string_to_regexp [sve_value_pattern $state $sve_vl 85 255]]
+ for {set row 0} {$row < 32} {incr row} {
+ set register_name "\$z${row}\.b\.u"
+ gdb_test "print sizeof $register_name" " = $sve_vl" "size of $register_name"
+ gdb_test "print $register_name" $sve_pattern "read back from $register_name"
+ }
+
+ # Print ZA to check its value.
+ gdb_test "print \$za" $za_pattern "read back from za"
+
+ # Test TPIDR2 restore from signal frame as well.
+ gdb_test_no_output "set \$tpidr2=0x0102030405060708"
+
+ # Run to the illegal instruction.
+ if [gdb_test "continue" "Continuing\.\r\n\r\nProgram received signal SIGILL, Illegal instruction\..*in main.*"] {
+ return
+ }
+
+ # Skip the illegal instruction. The signal handler will be called after we continue.
+ gdb_test_no_output "set \$pc=\$pc+4"
+ # Continue to the signal handler.
+ if [gdb_continue_to_breakpoint $handler_breakpoint] {
+ return -1
+ }
+
+ # Modify TPIDR2 so it is different from its value past the signal
+ # frame.
+ gdb_test_no_output "set \$tpidr2 = 0x0"
+
+ # Select the frame that contains "main".
+ gdb_test "frame 2" "#2.* main \\\(.*\\\) at.*"
+
+ for {set row 0} {$row < 32} {incr row} {
+ set register_name "\$z${row}\.b\.u"
+ gdb_test "print sizeof $register_name" " = $sve_vl" "size of $register_name in the signal frame"
+ gdb_test "print $register_name" $sve_pattern "$register_name contents from signal frame"
+ }
+
+ # Check the size of ZA in the signal frame.
+ set expected_za_size [expr $svl * $svl]
+ gdb_test "print sizeof \$za" " = $expected_za_size" "size of za in signal frame"
+
+ # Check the value of SVCR in the signal frame.
+ gdb_test "print \$svcr" [get_svcr_value $state] "svcr from signal frame"
+
+ # Check the value of ZA in the signal frame.
+ gdb_test "print \$za" $za_pattern "za contents from signal frame"
+
+ # Check the value of TPIDR2 in the signal frame.
+ gdb_test "print/x \$tpidr2" " = 0x102030405060708" "tpidr2 contents from signal frame"
+ }
+ }
+}
+
+require is_aarch64_target
+
+if {![allow_aarch64_sve_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+if {![allow_aarch64_sme_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+test_sme_registers_sigframe $id_start $id_end
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-0.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-0.exp
new file mode 100644
index 00000000000..c758c4862be
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-0.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 0
+set id_end 3
+source $srcdir/$subdir/aarch64-sme-regs-unavailable.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-1.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-1.exp
new file mode 100644
index 00000000000..10e27174067
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-1.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 11
+set id_end 15
+source $srcdir/$subdir/aarch64-sme-regs-unavailable.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-2.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-2.exp
new file mode 100644
index 00000000000..c1e5e279231
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-2.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 16
+set id_end 19
+source $srcdir/$subdir/aarch64-sme-regs-unavailable.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-3.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-3.exp
new file mode 100644
index 00000000000..cbe84dbff9a
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-3.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 20
+set id_end 22
+source $srcdir/$subdir/aarch64-sme-regs-unavailable.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-4.exp b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-4.exp
new file mode 100644
index 00000000000..f6f884cb910
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-4.exp
@@ -0,0 +1,18 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+set id_start 23
+set id_end 24
+source $srcdir/$subdir/aarch64-sme-regs-unavailable.exp.tcl
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.c b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.c
new file mode 100644
index 00000000000..2dd72ffd5d4
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.c
@@ -0,0 +1,154 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2023 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Exercise various cases of ZA contents not being available for AArch64's
+ Scalable Matrix Extension. */
+
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <sys/prctl.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+#ifndef HWCAP_SVE
+#define HWCAP_SVE (1 << 22)
+#endif
+
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
+#ifndef PR_SVE_SET_VL
+#define PR_SVE_SET_VL 50
+#define PR_SVE_GET_VL 51
+#define PR_SVE_VL_LEN_MASK 0xffff
+#endif
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#define PR_SME_GET_VL 64
+#define PR_SME_VL_LEN_MASK 0xffff
+#endif
+
+static int get_vl_size ()
+{
+ int res = prctl (PR_SVE_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int get_svl_size ()
+{
+ int res = prctl (PR_SME_GET_VL, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_GET_VL (%d)", res);
+ return -1;
+ }
+ return (res & PR_SVE_VL_LEN_MASK);
+}
+
+static int set_vl_size (int new_vl)
+{
+ int res = prctl (PR_SVE_SET_VL, new_vl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SVE_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_vl_size ();
+ if (res != new_vl)
+ {
+ printf ("Unexpected VL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+static int set_svl_size (int new_svl)
+{
+ int res = prctl (PR_SME_SET_VL, new_svl, 0, 0, 0, 0);
+ if (res < 0)
+ {
+ printf ("FAILED to PR_SME_SET_VL (%d)", res);
+ return -1;
+ }
+
+ res = get_svl_size ();
+ if (res != new_svl)
+ {
+ printf ("Unexpected SVL value (%d)", res);
+ return -1;
+ }
+
+ return res;
+}
+
+static int
+test_id_to_vl (int id)
+{
+ return 16 << ((id / 5) % 5);
+}
+
+static int
+test_id_to_svl (int id)
+{
+ return 16 << (id % 5);
+}
+
+static void
+dummy ()
+{
+}
+
+int
+main (int argc, char **argv)
+{
+ if (getauxval (AT_HWCAP) & HWCAP_SVE && getauxval (AT_HWCAP2) & HWCAP2_SME)
+ {
+ int id_start = ID_START;
+ int id_end = ID_END;
+
+ for (int id = id_start; id <= id_end; id++)
+ {
+ int vl = test_id_to_vl (id);
+ int svl = test_id_to_svl (id);
+
+ if (set_vl_size (vl) == -1)
+ return -1;
+ if (set_svl_size (svl) == -1)
+ return -1;
+
+ dummy (); /* stop 1 */
+ }
+
+ dummy (); /* stop 2 */
+ }
+ else
+ {
+ printf ("SKIP: no HWCAP_SVE or HWCAP2_SME on this system\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl
new file mode 100644
index 00000000000..d515fe07b90
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl
@@ -0,0 +1,162 @@
+# Copyright (C) 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Exercise the following:
+# - Printing ZA registers when there is no ZA state.
+# - Setting values of ZA registers when there is no ZA state.
+# - Validating ZA state is activated when we write to ZA registers.
+
+load_lib aarch64.exp
+
+#
+# Validate that the ZA registers have the expected state.
+#
+proc_with_prefix check_regs { vl svl } {
+ # Check VG to make sure it is correct
+ set expected_vg [expr $vl / 8]
+ gdb_test "print \$vg" "= ${expected_vg}"
+
+ # Check SVG to make sure it is correct
+ set expected_svg [expr $svl / 8]
+ gdb_test "print \$svg" "= ${expected_svg}"
+
+ # Make sure there is no SM or ZA state.
+ if [gdb_test "print \$svcr" "= \\\[ \\\]"] {
+ fail "incorrect ZA state"
+ return -1
+ }
+
+ # Check the size of ZA.
+ set expected_za_size [expr $svl * $svl]
+ gdb_test "print sizeof \$za" " = $expected_za_size"
+
+ # Check the size of Z0.
+ gdb_test "print sizeof \$z0" " = $vl"
+
+ # Set the expected ZA pattern.
+ set za_pattern [string_to_regexp [2d_array_value_pattern 0 $svl $svl]]
+
+ # Check ZA.
+ gdb_test "print \$za" $za_pattern
+
+ # Exercise reading/writing the tile slice pseudo-registers.
+ set last_tile 1
+ set last_slice $svl
+ set elements $svl
+ set expected_size $svl
+ foreach_with_prefix granularity {"b" "h" "s" "d" "q"} {
+ set pattern [string_to_regexp [1d_array_value_pattern 0 $elements]]
+ for {set tile 0} {$tile < $last_tile} {incr tile} {
+ for {set slice 0} {$slice < $last_slice} {incr slice} {
+ foreach_with_prefix direction {"h" "v"} {
+ set register_name "\$za${tile}${direction}${granularity}${slice}"
+ # Test the size.
+ gdb_test "print sizeof ${register_name}" " = ${expected_size}"
+ gdb_test "print ${register_name}" $pattern
+ }
+ }
+ }
+ set last_tile [expr $last_tile * 2]
+ set last_slice [expr ($last_slice / 2)]
+ set elements [expr ($elements / 2)]
+ }
+
+ # Exercise reading/writing the tile pseudo-registers.
+ set last_tile 1
+ set elements $svl
+ set expected_size [expr $svl * $svl]
+ foreach_with_prefix granularity {"b" "h" "s" "d" "q"} {
+ set pattern [string_to_regexp [2d_array_value_pattern 0 $elements $elements]]
+ for {set tile 0} {$tile < $last_tile} {incr tile} {
+ set register_name "\$za${tile}${granularity}"
+ # Test the size.
+ gdb_test "print sizeof ${register_name}" " = ${expected_size}"
+ gdb_test "print ${register_name}" $pattern
+ }
+ set last_tile [expr $last_tile * 2]
+ set expected_size [expr $expected_size / 2]
+ set elements [expr ($elements / 2)]
+ }
+}
+
+#
+# Cycle through all ZA registers and pseudo-registers and validate that their
+# contents are unavailable (zeroed out) for vector length SVL.
+#
+proc test_sme_registers_unavailable { id_start id_end } {
+
+ set compile_flags {"debug" "macros"}
+ lappend compile_flags "additional_flags=-DID_START=${id_start}"
+ lappend compile_flags "additional_flags=-DID_END=${id_end}"
+
+ standard_testfile ${::srcdir}/${::subdir}/aarch64-sme-regs-unavailable.c
+ set executable "${::testfile}-${id_start}-${id_end}"
+ if {[prepare_for_testing "failed to prepare" ${executable} ${::srcfile} ${compile_flags}]} {
+ return -1
+ }
+ set binfile [standard_output_file ${executable}]
+
+ if ![runto_main] {
+ untested "could not run to main"
+ return -1
+ }
+
+ gdb_test_no_output "set print repeats 1"
+
+ set prctl_breakpoint "stop 1"
+ gdb_breakpoint [gdb_get_line_number $prctl_breakpoint]
+
+ for {set id $id_start} {$id <= $id_end} {incr id} {
+ set vl [test_id_to_vl $id]
+ set svl [test_id_to_svl $id]
+ with_test_prefix "prctl, vl=${vl} svl=${svl}" {
+ # Run the program until it has adjusted svl.
+ gdb_continue_to_breakpoint $prctl_breakpoint
+ check_regs $vl $svl
+ }
+ }
+
+ set non_prctl_breakpoint "stop 2"
+ gdb_breakpoint [gdb_get_line_number $non_prctl_breakpoint]
+ gdb_continue_to_breakpoint $non_prctl_breakpoint
+
+ for {set id $id_start} {$id <= $id_end} {incr id} {
+ set vl [test_id_to_vl $id]
+ set svl [test_id_to_svl $id]
+ with_test_prefix "non prctl, vl=${vl} svl=${svl}" {
+ # Adjust vg and svg.
+ set vg_value [expr $vl / 8]
+ set svg_value [expr $svl / 8]
+ gdb_test_no_output "set \$vg = ${vg_value}"
+ gdb_test_no_output "set \$svg = ${svg_value}"
+
+ check_regs $vl $svl
+ }
+ }
+}
+
+require is_aarch64_target
+
+if {![allow_aarch64_sve_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+if {![allow_aarch64_sme_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+test_sme_registers_unavailable $id_start $id_end
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c
new file mode 100644
index 00000000000..694de0626d2
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c
@@ -0,0 +1,249 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2023 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Sanity test to exercise AArch64's Scalable Vector/Matrix Extension basic
+ functionality. It cycles through different combinations of state and
+ initializes different register sets. */
+
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#ifndef HWCAP_SVE
+#define HWCAP_SVE (1 << 22)
+#endif
+
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
+static void
+enable_za ()
+{
+ /* smstart za */
+ __asm __volatile (".word 0xD503457F");
+}
+
+static void
+disable_za ()
+{
+ /* smstop za */
+ __asm __volatile (".word 0xD503447F");
+}
+
+static void
+enable_sm ()
+{
+ /* smstart sm */
+ __asm __volatile (".word 0xD503437F");
+}
+
+static void
+disable_sm ()
+{
+ /* smstop sm */
+ __asm __volatile (".word 0xD503427F");
+}
+
+static void
+initialize_fpsimd_state ()
+{
+ char buffer[16];
+
+ for (int i = 0; i < 16; i++)
+ buffer[i] = 0x55;
+
+ __asm __volatile ("mov x0, %0\n\t" \
+ : : "r" (buffer));
+
+ __asm __volatile ("ldr q0, [x0]");
+ __asm __volatile ("ldr q1, [x0]");
+ __asm __volatile ("ldr q2, [x0]");
+ __asm __volatile ("ldr q3, [x0]");
+ __asm __volatile ("ldr q4, [x0]");
+ __asm __volatile ("ldr q5, [x0]");
+ __asm __volatile ("ldr q6, [x0]");
+ __asm __volatile ("ldr q7, [x0]");
+ __asm __volatile ("ldr q8, [x0]");
+ __asm __volatile ("ldr q9, [x0]");
+ __asm __volatile ("ldr q10, [x0]");
+ __asm __volatile ("ldr q11, [x0]");
+ __asm __volatile ("ldr q12, [x0]");
+ __asm __volatile ("ldr q13, [x0]");
+ __asm __volatile ("ldr q14, [x0]");
+ __asm __volatile ("ldr q15, [x0]");
+ __asm __volatile ("ldr q16, [x0]");
+ __asm __volatile ("ldr q17, [x0]");
+ __asm __volatile ("ldr q18, [x0]");
+ __asm __volatile ("ldr q19, [x0]");
+ __asm __volatile ("ldr q20, [x0]");
+ __asm __volatile ("ldr q21, [x0]");
+ __asm __volatile ("ldr q22, [x0]");
+ __asm __volatile ("ldr q23, [x0]");
+ __asm __volatile ("ldr q24, [x0]");
+ __asm __volatile ("ldr q25, [x0]");
+ __asm __volatile ("ldr q26, [x0]");
+ __asm __volatile ("ldr q27, [x0]");
+ __asm __volatile ("ldr q28, [x0]");
+ __asm __volatile ("ldr q29, [x0]");
+ __asm __volatile ("ldr q30, [x0]");
+ __asm __volatile ("ldr q31, [x0]");
+}
+
+static void
+initialize_za_state ()
+{
+ /* zero za */
+ __asm __volatile (".word 0xC00800FF");
+
+ char buffer[256];
+
+ for (int i = 0; i < 256; i++)
+ buffer[i] = 0xaa;
+
+ __asm __volatile ("mov x0, %0\n\t" \
+ : : "r" (buffer));
+
+ /* Initialize loop boundaries. */
+ __asm __volatile ("mov w12, 0");
+ __asm __volatile ("mov w17, 256");
+
+ /* loop: ldr za[w12, 0], [x0] */
+ __asm __volatile ("loop: .word 0xe1000000");
+ __asm __volatile ("add w12, w12, 1");
+ __asm __volatile ("cmp w12, w17");
+ __asm __volatile ("bne loop");
+}
+
+static void
+initialize_sve_state ()
+{
+ __asm __volatile ("dup z0.b, -1");
+ __asm __volatile ("dup z1.b, -1");
+ __asm __volatile ("dup z2.b, -1");
+ __asm __volatile ("dup z3.b, -1");
+ __asm __volatile ("dup z4.b, -1");
+ __asm __volatile ("dup z5.b, -1");
+ __asm __volatile ("dup z6.b, -1");
+ __asm __volatile ("dup z7.b, -1");
+ __asm __volatile ("dup z8.b, -1");
+ __asm __volatile ("dup z9.b, -1");
+ __asm __volatile ("dup z10.b, -1");
+ __asm __volatile ("dup z11.b, -1");
+ __asm __volatile ("dup z12.b, -1");
+ __asm __volatile ("dup z13.b, -1");
+ __asm __volatile ("dup z14.b, -1");
+ __asm __volatile ("dup z15.b, -1");
+ __asm __volatile ("dup z16.b, -1");
+ __asm __volatile ("dup z17.b, -1");
+ __asm __volatile ("dup z18.b, -1");
+ __asm __volatile ("dup z19.b, -1");
+ __asm __volatile ("dup z20.b, -1");
+ __asm __volatile ("dup z21.b, -1");
+ __asm __volatile ("dup z22.b, -1");
+ __asm __volatile ("dup z23.b, -1");
+ __asm __volatile ("dup z24.b, -1");
+ __asm __volatile ("dup z25.b, -1");
+ __asm __volatile ("dup z26.b, -1");
+ __asm __volatile ("dup z27.b, -1");
+ __asm __volatile ("dup z28.b, -1");
+ __asm __volatile ("dup z29.b, -1");
+ __asm __volatile ("dup z30.b, -1");
+ __asm __volatile ("dup z31.b, -1");
+ __asm __volatile ("ptrue p0.b");
+ __asm __volatile ("ptrue p1.b");
+ __asm __volatile ("ptrue p2.b");
+ __asm __volatile ("ptrue p3.b");
+ __asm __volatile ("ptrue p4.b");
+ __asm __volatile ("ptrue p5.b");
+ __asm __volatile ("ptrue p6.b");
+ __asm __volatile ("ptrue p7.b");
+ __asm __volatile ("ptrue p8.b");
+ __asm __volatile ("ptrue p9.b");
+ __asm __volatile ("ptrue p10.b");
+ __asm __volatile ("ptrue p11.b");
+ __asm __volatile ("ptrue p12.b");
+ __asm __volatile ("ptrue p13.b");
+ __asm __volatile ("ptrue p14.b");
+ __asm __volatile ("ptrue p15.b");
+ __asm __volatile ("setffr");
+}
+
+/* Enable register states based on STATE.
+
+ 0 - FPSIMD
+ 1 - SVE
+ 2 - SSVE
+ 3 - ZA
+ 4 - ZA and SSVE. */
+
+void enable_states (int state)
+{
+ disable_za ();
+ disable_sm ();
+ initialize_fpsimd_state ();
+
+ if (state == 1)
+ {
+ initialize_sve_state ();
+ }
+ else if (state == 2)
+ {
+ enable_sm ();
+ initialize_sve_state ();
+ }
+ else if (state == 3)
+ {
+ enable_za ();
+ initialize_za_state ();
+ }
+ else if (state == 4)
+ {
+ enable_za ();
+ enable_sm ();
+ initialize_sve_state ();
+ initialize_za_state ();
+ }
+
+ return;
+}
+
+void dummy ()
+{
+}
+
+int
+main (int argc, char **argv)
+{
+ if (getauxval (AT_HWCAP) & HWCAP_SVE && getauxval (AT_HWCAP2) & HWCAP2_SME)
+ {
+ for (int state = 0; state < 5; state++)
+ {
+ enable_states (state);
+ dummy (); /* stop here */
+ }
+ }
+ else
+ {
+ printf ("SKIP: no HWCAP_SVE or HWCAP2_SME on this system\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp
new file mode 100644
index 00000000000..c96df7543e0
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp
@@ -0,0 +1,72 @@
+# Copyright (C) 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Sanity check for AArch64 Scalable Vector/Matrix Extensions functionality.
+
+load_lib aarch64.exp
+
+#
+# Run a series of basic checks for SVE/SME states.
+#
+proc sanity_check { vl svl } {
+ # Run the program until the point where we start initializing the different
+ # register states.
+ set state_breakpoint "stop here"
+ gdb_breakpoint [gdb_get_line_number $state_breakpoint]
+
+ for {set id 0} {$id < 5} {incr id} {
+ set state [state_id_to_state_string $id]
+
+ with_test_prefix "state=${state} vl=${vl} svl=${svl}" {
+ gdb_continue_to_breakpoint $state_breakpoint
+ check_state $state $vl $svl
+ }
+ }
+}
+
+require is_aarch64_target
+
+if {![allow_aarch64_sve_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+if {![allow_aarch64_sme_tests]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+set compile_flags {"debug" "macros" "additional_flags=-march=armv8.5-a+sve"}
+standard_testfile
+if {[prepare_for_testing "failed to prepare" ${testfile} ${srcfile} ${compile_flags}]} {
+ return -1
+}
+
+if {![runto_main]} {
+ return -1
+}
+
+# Adjust the repeat count for the test.
+gdb_test_no_output "set print repeats 1" "adjust repeat count"
+
+# Fetch both the vector length and the streaming vector length the target
+# system is using. We do not force any vector lengths and do not change
+# it mid-execution.
+set vl [expr [get_valueof "" "\$vg" "0" "fetch value of vl"] * 8]
+set svl [expr [get_valueof "" "\$svg" "0" "fetch value of svl"] * 8]
+
+# Now we are at the point where we can start checking state and moving the
+# testcase forward.
+sanity_check $vl $svl
diff --git a/gdb/testsuite/lib/aarch64.exp b/gdb/testsuite/lib/aarch64.exp
new file mode 100644
index 00000000000..076964e2028
--- /dev/null
+++ b/gdb/testsuite/lib/aarch64.exp
@@ -0,0 +1,372 @@
+# Copyright 2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+# Support routines for aarch64-specific tests
+
+#
+# Return a regular expression that matches what gdb would print for a
+# 1-dimension vector containing ELEMENTS elements of value BYTE.
+#
+# The pattern is of the form "{BYTE <repeats ELEMENTS times>".
+#
+proc 1d_array_value_pattern { byte elements } {
+ set brace_open "{"
+ set brace_close "}"
+
+ append data $brace_open $byte
+ if {$elements > 1} {
+ append data " <repeats $elements times>"
+ }
+ append data $brace_close
+
+ verbose -log "1d_array_value_pattern Pattern string is..."
+ verbose -log $data
+ return $data
+}
+
+#
+# Return a regular expression that matches what gdb would print for a
+# 2-dimension vector containing ROWS rows and COLUMNS columns of elements
+# of value BYTE.
+#
+# The pattern is of the form
+# "{{BYTE <repeats COLUMNS times>} <repeats ROWS times>}".
+#
+proc 2d_array_value_pattern { byte rows columns } {
+ set brace_open "{"
+ set brace_close "}"
+
+ append data $brace_open [1d_array_value_pattern $byte $columns]
+ if {$rows > 1} {
+ append data " <repeats $rows times>"
+ }
+ append data $brace_close
+
+ verbose -log "2d_array_value_pattern Pattern string is..."
+ verbose -log $data
+ return $data
+}
+
+#
+# Return a regular expression that matches what gdb would print for a
+# SVE Z register of length VL in state STATE. The Z register should be filled
+# with BYTE_SVE and the FPSIMD registers should be filled with BYTE_FPSIMD.
+#
+# The pattern is of the form
+#
+# {BYTE_FPSIMD <repeats 16 times>}
+#
+# or
+#
+# {BYTE_FPSIMD <repeats 16 times>, 0 <repeats ... times>}
+#
+# or
+#
+# {BYTE_SVE <repeats VL times>}
+#
+proc sve_value_pattern { state vl byte_fpsimd byte_sve } {
+ set brace_open "{"
+ set brace_close "}"
+
+ append data $brace_open
+ if { $state == "fpsimd" || $state == "za" } {
+ if { $vl > 16 } {
+ set sve_repeat_count [expr $vl - 16]
+ append data "$byte_fpsimd <repeats 16 times>, 0 <repeats $sve_repeat_count times>"
+ } else {
+ append data "$byte_fpsimd <repeats 16 times>"
+ }
+ } else {
+ append data "$byte_sve <repeats $vl times>"
+ }
+ append data $brace_close
+
+ verbose -log "sve_value_pattern pattern string is..."
+ verbose -log $data
+ return $data
+}
+
+#
+# Initialize register NAME, a 1-dimension vector, with ELEMENTS elements
+# by setting all elements to BYTE. ELEMENTS is limited at 256 for memory
+# usage purposes.
+#
+# The initialization is of the form "{BYTE, BYTE, BYTE ...}".
+#
+proc initialize_1d_array { name byte elements } {
+ set brace_open "{"
+ set brace_close "}"
+
+ append data $brace_open
+
+ # Build the assignment in a single shot.
+ for {set element 0} {$element < $elements} {incr element} {
+ # Construct the initializer by appending elements to it.
+ append data $byte
+
+ # If this isn't the last element, add a comma.
+ if {[expr $element + 1] < $elements} {
+ append data ", "
+ }
+ }
+ append data $brace_close
+
+ verbose -log "initialization string is..."
+ verbose -log $data
+ gdb_test_no_output "set $name = $data" "write to $name"
+}
+
+#
+# Return an initializer string for a 2-dimension vector with ROWS rows and
+# COLUMNS columns, initializing all elements to BYTE for register NAME.
+#
+# COLUMNS is limited to 256 elements for memory usage purposes.
+#
+# The initialization is of the form "{{BYTE, BYTE}, ..., {BYTE, BYTE}}}".
+#
+proc initialize_2d_array { name byte rows columns } {
+ set brace_open "{"
+ set brace_close "}"
+
+ if {[expr $rows * $columns] <= 256} {
+ # Build the assignment in a single shot, as we have a maximum of 256
+ # elements.
+ for {set row 0} {$row < $rows} {incr row} {
+ append data $brace_open
+ for {set column 0} {$column < $columns} {incr column} {
+ # Construct the initializer by appending elements to it.
+ append data $byte
+
+ # If this isn't the last column, add a comma.
+ if {[expr $column + 1] < $columns} {
+ append data ", "
+ }
+ }
+
+ append data $brace_close
+
+ # If this isn't the last row, add a comma.
+ if {[expr $row + 1] < $rows} {
+ append data ","
+ }
+ }
+
+ set data $brace_open$data
+ set data $data$brace_close
+
+ verbose -log "initialization string is..."
+ verbose -log $data
+ gdb_test_no_output "set $name = $data" "write to $name"
+ } else {
+ # There are too many elements to initialize (more than 256), so we
+ # will do the initialization row by row.
+ for {set row 0} {$row < $rows} {incr row} {
+ initialize_1d_array "$name\[$row\]" $byte $columns
+ }
+ }
+}
+
+#
+# Return the SVCR value based STATE.
+#
+proc get_svcr_value { state } {
+ if { $state == "ssve" } {
+ return "= \\\[ SM \\\]"
+ } elseif { $state == "za" } {
+ return "= \\\[ ZA \\\]"
+ } elseif { $state == "za_ssve" } {
+ return "= \\\[ SM ZA \\\]"
+ }
+
+ return "= \\\[ \\\]"
+}
+
+#
+# Return the state string based on STATE
+#
+proc state_id_to_state_string { state } {
+ if {$state == 0} {
+ return "fpsimd"
+ } elseif {$state == 1} {
+ return "sve"
+ } elseif {$state == 2} {
+ return "ssve"
+ } elseif {$state == 3} {
+ return "za"
+ } elseif {$state == 4} {
+ return "za_ssve"
+ }
+}
+
+#
+# Given a test ID, return the string representing the register state.
+# The state is one of fpsimd, sve, ssve, za and za_ssve.
+#
+proc test_id_to_state { id } {
+ set state [expr $id / 25]
+
+ return [state_id_to_state_string $state]
+}
+
+#
+# Given a test ID, return the associated vector length.
+#
+proc test_id_to_vl { id } {
+ return [expr 16 << (($id / 5) % 5)]
+}
+
+#
+# Given a test ID, return the associated streaming vector length.
+#
+proc test_id_to_svl { id } {
+ return [expr 16 << ($id % 5)]
+}
+
+#
+# Validate the values of the FPSIMD registers.
+#
+proc check_fpsimd_regs { byte state vl svl} {
+ set fpsimd_pattern [string_to_regexp [1d_array_value_pattern $byte 16]]
+
+ for {set number 0} {$number < 32} {incr number} {
+ set register_name "\$v${number}\.b\.u"
+ gdb_test "print sizeof $register_name" " = 16"
+ gdb_test "print $register_name" $fpsimd_pattern
+ }
+}
+
+#
+# Validate the values of the SVE registers.
+#
+proc check_sve_regs { byte state vl svl } {
+
+ # If streaming mode is enabled, the vector length is the streaming
+ # vector length.
+ set z_pattern ""
+ set z_size 0
+ if {$state == "ssve" || $state == "za_ssve"} {
+ set z_pattern [string_to_regexp [1d_array_value_pattern $byte $svl]]
+ set z_size $svl
+ } else {
+ set z_size $vl
+
+ if {$state == "fpsimd" || $state == "za"} {
+ # If there is no SVE/SSVE state, the contents of the Z/P/FFR registers
+ # are zero.
+ if {$vl == 16} {
+ set z_pattern [string_to_regexp [1d_array_value_pattern $byte $vl]]
+ } else {
+ set z_repeats [expr $vl - 16]
+ set z_pattern [string_to_regexp "{$byte <repeats 16 times>, 0 <repeats $z_repeats times>}"]
+ }
+ } else {
+ set z_pattern [string_to_regexp [1d_array_value_pattern $byte $vl]]
+ }
+ }
+ set p_size [expr $z_size / 8]
+
+ # If there is no SVE/SSVE state, the contents of the Z/P/FFR registers
+ # are zero.
+ set p_byte $byte
+ if {$state == "fpsimd" || $state == "za"} {
+ set p_byte 0
+ }
+ set p_pattern [string_to_regexp [1d_array_value_pattern $p_byte $p_size]]
+
+ for {set number 0} {$number < 32} {incr number} {
+ set register_name "\$z${number}\.b\.u"
+ gdb_test "print sizeof $register_name" " = $z_size"
+ gdb_test "print $register_name" $z_pattern
+ }
+
+ for {set number 0} {$number < 16} {incr number} {
+ set register_name "\$p${number}"
+ gdb_test "print sizeof $register_name" " = $p_size"
+ gdb_test "print $register_name" $p_pattern
+ }
+
+ gdb_test "print \$ffr" $p_pattern
+}
+
+#
+# Validate the values of the SME registers.
+#
+proc check_sme_regs { byte state svl } {
+ # ZA contents are only available when the ZA state is enabled. Otherwise
+ # the ZA contents are unavailable (zeroed out).
+ set za_pattern ""
+ set expected_za_size [expr $svl * $svl]
+
+ if {$state != "za" && $state != "za_ssve"} {
+ set byte 0
+ }
+
+ set za_pattern [string_to_regexp [2d_array_value_pattern $byte $svl $svl]]
+
+ gdb_test "print sizeof \$za" " = $expected_za_size"
+ gdb_test "print \$za" $za_pattern
+}
+
+#
+# With register STATE, vector length VL and streaming vector length SVL,
+# run some register state checks to make sure the values are the expected
+# ones
+#
+proc check_state { state vl svl } {
+ # The FPSIMD registers are initialized with a value of 0x55 (125)
+ # for each byte.
+ #
+ # The SVE registers are initialized with a value of 0xff (255) for each
+ # byte, including the predicate registers and FFR.
+ #
+ # The SME (ZA) register is initialized with a value of 0xaa (252) for
+ # each byte.
+
+ # Check VG to make sure it is correct
+ set expected_vg [expr $vl / 8]
+ # If streaming mode is enabled, then vg is actually svg.
+ if {$state == "ssve" || $state == "za_ssve"} {
+ set expected_vg [expr $svl / 8]
+ }
+ gdb_test "print \$vg" " = ${expected_vg}"
+
+ # Check SVG to make sure it is correct
+ set expected_svg [expr $svl / 8]
+ gdb_test "print \$svg" " = ${expected_svg}"
+
+ # Check the value of SVCR.
+ gdb_test "print \$svcr" [get_svcr_value $state]
+
+ # When we have any SVE or SSVE state, the FPSIMD registers will have
+ # the same values as the SVE/SSVE Z registers.
+ set fpsimd_byte 85
+ if {$state == "sve" || $state == "ssve" || $state == "za_ssve"} {
+ set fpsimd_byte 255
+ }
+
+ set sve_byte 255
+ if {$state == "fpsimd" || $state == "za"} {
+ set sve_byte 85
+ }
+
+ # Check FPSIMD registers
+ check_fpsimd_regs $fpsimd_byte $state $vl $svl
+ # Check SVE registers
+ check_sve_regs $sve_byte $state $vl $svl
+ # Check SME registers
+ check_sme_regs 170 $state $svl
+}
+
+
diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp
index 7538071d1cf..529b96091f2 100644
--- a/gdb/testsuite/lib/gdb.exp
+++ b/gdb/testsuite/lib/gdb.exp
@@ -4025,6 +4025,69 @@ gdb_caching_proc allow_aarch64_sve_tests {} {
return $allow_sve_tests
}
+# Run a test on the target to see if it supports Aarch64 SME extensions.
+# Return 0 if so, 1 if it does not. Note this causes a restart of GDB.
+
+gdb_caching_proc allow_aarch64_sme_tests {} {
+ global srcdir subdir gdb_prompt inferior_exited_re
+
+ set me "allow_aarch64_sme_tests"
+
+ if { ![is_aarch64_target]} {
+ return 0
+ }
+
+ set compile_flags "{additional_flags=-march=armv8-a+sme}"
+
+ # Compile a test program containing SVE instructions.
+ set src {
+ int main() {
+ asm volatile ("smstart za");
+ return 0;
+ }
+ }
+ if {![gdb_simple_compile $me $src executable $compile_flags]} {
+ # Try again, but with a raw hex instruction so we don't rely on
+ # assembler support for SME.
+
+ set compile_flags "{additional_flags=-march=armv8-a}"
+
+ # Compile a test program containing SVE instructions.
+ set src {
+ int main() {
+ asm volatile (".word 0xD503457F");
+ return 0;
+ }
+ }
+
+ if {![gdb_simple_compile $me $src executable $compile_flags]} {
+ return 0
+ }
+ }
+
+ # Compilation succeeded so now run it via gdb.
+ clean_restart $obj
+ gdb_run_cmd
+ gdb_expect {
+ -re ".*Illegal instruction.*${gdb_prompt} $" {
+ verbose -log "\n$me sme support not detected"
+ set allow_sme_tests 0
+ }
+ -re ".*$inferior_exited_re normally.*${gdb_prompt} $" {
+ verbose -log "\n$me: sme support detected"
+ set allow_sme_tests 1
+ }
+ default {
+ warning "\n$me: default case taken"
+ set allow_sme_tests 0
+ }
+ }
+ gdb_exit
+ remote_file build delete $obj
+
+ verbose "$me: returning $allow_sme_tests" 2
+ return $allow_sme_tests
+}
# A helper that compiles a test case to see if __int128 is supported.
proc gdb_int128_helper {lang} {
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (15 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 16/17] [gdb/testsuite] sme: Add SVE/SME testcases Luis Machado
@ 2023-04-11 4:26 ` Luis Machado
2023-04-11 7:09 ` Eli Zaretskii
` (2 more replies)
2023-04-11 15:50 ` [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux John Baldwin
17 siblings, 3 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 4:26 UTC (permalink / raw)
To: gdb-patches
Provide documentation for the SME feature and other information that
should be useful for users that need to debug a SME-capable target.
---
gdb/NEWS | 11 ++++++++
gdb/doc/gdb.texinfo | 68 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index 10a1a70fa52..48a82172f0e 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -3,6 +3,17 @@
*** Changes since GDB 13
+* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
+ a new matrix register named ZA, a new thread register TPIDR2 and a new vector
+ length register SVG (streaming vector granule). GDB also supports tracking
+ ZA state across signal frames.
+
+ Some features are still under development or are dependent on ABI specs that
+ are still in alpha stage. For example, manual function calls with ZA state
+ don't have any special handling, and tracking of SVG changes based on
+ DWARF information is still not implemented, but there are plans to do so in
+ the future.
+
* GDB now has some support for integer types larger than 64 bits.
* Removed targets and native configurations
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 2d5358a792b..f84e05fbed2 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -26038,6 +26038,61 @@ but the lengths of the @code{z} and @code{p} registers will not change. This
is a known limitation of @value{GDBN} and does not affect the execution of the
target process.
+@subsubsection AArch64 SME.
+@cindex AArch64 SME.
+
+When @value{GDBN} is debugging the AArch64 architecture, if the Scalable Matrix
+Extension (SME) is present, then @value{GDBN} will provide the @code{za}
+register. @value{GDBN} will also provide the @code{svg} pseudo register and
+the @code{svcr} pseudo register.
+
+The @code{za} register is a 2-dimensional vector of bytes with a size of svl
+x svl, where svl is the streaming vector length.
+
+The @code{svg} vector is the streaming vector granule for the current thread
+and represents the number of 64-bit chunks in one dimension of the @code{za}
+register.
+
+The @code{svcr} register (streaming vector control register) is a status
+register that holds two state bits: @code{SM} in bit 0 and @code{ZA} in bit 1.
+
+If the @code{SM} bit is 1, it means the current thread is in streaming
+mode, and the SVE registers will have their sizes based on the @code{svg}
+register. If the @code{SM} bit is 0, the current thread is not in streaming
+mode, and the SVE registers have sizes based on the @code{vg} register.
+
+If the @code{ZA} bit is 1, it means the @code{ZA} state, and therefore the
+@code{za} register, is being used and has meaningful contents. If the
+@code{ZA} bit is 0, the ZA state is unavailable and the contents of the
+@code{za} register are undefined.
+
+If the @code{ZA} state is 0, the @code{za} register and its pseudo registers
+will read as <unavailable>.
+
+If the streaming vector length changes, then the @code{svg} register will be
+updated, as well as the @code{za} register.
+
+The possible values for @code{svg} are 2, 4, 8, 16, 32. These numbers
+correspond to streaming vector length values of 16 bytes, 32 bytes, 64 bytes,
+128 bytes and 256 bytes.
+
+The minimum size of the @code{za} register is there 16 x 16 bytes, and the
+maximum size is 256 x 256 bytes. The size of the @code{za} register is the
+size of all the SVE @code{z} registers combined.
+
+The @code{za} register can also be referenced using tiles and tile slices.
+
+There is a fixed number of @code{za} tile pseudo registers (32). They are:
+za0b, za0h, za1h, zas0, zas1, zas2, zas3, zad0, zad1, zad2, zad3, zad4, zad5.
+
+The tile slice pseudo registers are numerous. For a minimum streaming vector
+length of 16 bytes, there are 5 x 32 pseudo registers. For the maximum
+streaming vector length of 256 bytes, there are 5 x 512 pseudo registers.
+
+The tile slice pseudo registers have the following naming pattern:
+
+za<tile number><orientation><slice number>.
+
@subsubsection AArch64 Pointer Authentication.
@cindex AArch64 Pointer Authentication.
@anchor{AArch64 PAC}
@@ -48030,6 +48085,19 @@ This restriction may be lifted in the future.
Extra registers are allowed in this feature, but they will not affect
@value{GDBN}.
+The @samp{org.gnu.gdb.aarch64.sme} feature is optional. If present,
+it should contain registers @samp{za}, @samp{svg} and @samp{svcr}.
+
+@samp{za} is a vector of bytes of size svl x svl. @samp{svg} is a 64-bit
+pseudo register containing the number of 64-bit chunks in svl. @samp{svcr}
+is a 64-bit state register containing bits 0 (SM) and 1 (ZA).
+
+The rest of the unused bits of @samp{svcr} are undefined and reserved. They
+should not be used and may be defined by future extensions of the architecture.
+
+Extra registers are allowed in this feature, but they will not affect
+@value{GDBN}.
+
@node ARC Features
@subsection ARC Features
@cindex target descriptions, ARC Features
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-11 4:26 ` [PATCH 17/17] [gdb/docs] sme: Document SME registers and features Luis Machado
@ 2023-04-11 7:09 ` Eli Zaretskii
2023-04-11 7:22 ` Luis Machado
2023-04-12 12:04 ` [PATCH,v2 " Luis Machado
2023-04-17 17:19 ` [PATCH,v3 " Luis Machado
2 siblings, 1 reply; 38+ messages in thread
From: Eli Zaretskii @ 2023-04-11 7:09 UTC (permalink / raw)
To: Luis Machado; +Cc: gdb-patches
> Date: Tue, 11 Apr 2023 05:26:58 +0100
> From: Luis Machado via Gdb-patches <gdb-patches@sourceware.org>
>
> Provide documentation for the SME feature and other information that
> should be useful for users that need to debug a SME-capable target.
> ---
> gdb/NEWS | 11 ++++++++
> gdb/doc/gdb.texinfo | 68 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
Thanks.
> diff --git a/gdb/NEWS b/gdb/NEWS
> index 10a1a70fa52..48a82172f0e 100644
> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -3,6 +3,17 @@
>
> *** Changes since GDB 13
>
> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
> + length register SVG (streaming vector granule). GDB also supports tracking
> + ZA state across signal frames.
> +
> + Some features are still under development or are dependent on ABI specs that
> + are still in alpha stage. For example, manual function calls with ZA state
> + don't have any special handling, and tracking of SVG changes based on
> + DWARF information is still not implemented, but there are plans to do so in
> + the future.
> +
> * GDB now has some support for integer types larger than 64 bits.
This part is OK.
> +@subsubsection AArch64 SME.
> +@cindex AArch64 SME.
Please also add a @cindex entry with the full name: scalable matrix
extension.
> +The @code{za} register is a 2-dimensional vector of bytes with a size of svl
> +x svl, where svl is the streaming vector length.
I suggest to rephrase:
The @code{za} register is a 2-dimensional rectangular
@code{@var{n}x@var{n}} matrix of bytes, where @var{n} is the
streaming vector length.
Should the text also explain what is this "streaming vector", its
length and "granule"? The text seems to use these terms all over
assuming the reader knows what they mean.
> +The @code{svg} vector is the streaming vector granule for the current thread
^^^^^^
"register", not "vector", right?
> +and represents the number of 64-bit chunks in one dimension of the @code{za}
> +register.
What do you mean by "represents the number"? how can one "represent" a
number?
Also, it sounds like the @var{n} I suggested to use above is related
to this register, in which case the description of ZA should make that
relation explicit. (I can suggest how once I understand the subject
well enough, see the questions above.)
> +The @code{svcr} register (streaming vector control register) is a status
> +register that holds two state bits: @code{SM} in bit 0 and @code{ZA} in bit 1.
I suggest to use @sc{sm} and @sc{za} here, instead of @code{SM} and
@code{ZA}. Try that in PDF and see which you like better. (Note that
@sc has its effect only on lower-case characters of its argument.)
> +If the @code{SM} bit is 1, it means the current thread is in streaming
> +mode, and the SVE registers will have their sizes based on the @code{svg}
> +register.
What does it mean for "the SVE registers will have their sizes based
on the @code{svg} register"? The text should explain this more
explicitly, IMO.
> If the @code{SM} bit is 0, the current thread is not in streaming
> +mode, and the SVE registers have sizes based on the @code{vg} register.
This refers to stuff explained elsewhere (the 'vg' register), so a
cross-reference is in order.
> +If the @code{ZA} state is 0, the @code{za} register and its pseudo registers
> +will read as <unavailable>.
What are the pseudo registers of the ZA register? I don't think they
were described earlier in the text.
> +The minimum size of the @code{za} register is there 16 x 16 bytes, and the
> +maximum size is 256 x 256 bytes. The size of the @code{za} register is the
> +size of all the SVE @code{z} registers combined.
By "The size of the @code{za} register" do you mean the number of
bytes in the matrix? That is, if ZA is 16 x 16, then its size is
16*16=256 bytes, or is it 16 bytes?
> +The @code{za} register can also be referenced using tiles and tile slices.
Referenced how? Should the text say anything specific about this
slice referencing, before talking (below) about the number of slices?
> +There is a fixed number of @code{za} tile pseudo registers (32). They are:
> +za0b, za0h, za1h, zas0, zas1, zas2, zas3, zad0, zad1, zad2, zad3, zad4, zad5.
This should probably preceded by something like
A @dfn{tile} of the @code{za} register is a pseudo-register which
can be used to... <add here what these tiles are used for>".
> +The tile slice pseudo registers are numerous. For a minimum streaming vector
> +length of 16 bytes, there are 5 x 32 pseudo registers. For the maximum
> +streaming vector length of 256 bytes, there are 5 x 512 pseudo registers.
> +
> +The tile slice pseudo registers have the following naming pattern:
> +
> +za<tile number><orientation><slice number>.
Likewise here: there should be a short explanation of what are tile
slices and how to use them.
All in all, I find this description rather terse and almost
impenetrable. I guess only those who are already familiar with this
architecture will fully understand it. Maybe this is the assumption
for the readers of this stuff, but then perhaps include a reference to
some external description of the architecture, and just say that GDB
supports this and that registers and pseudo-registers, without going
into any details regarding the meaning and purpose of each one of
them.
> +@samp{za} is a vector of bytes of size svl x svl. @samp{svg} is a 64-bit
> +pseudo register containing the number of 64-bit chunks in svl. @samp{svcr}
> +is a 64-bit state register containing bits 0 (SM) and 1 (ZA).
This again mentions "svl" without saying anything about it.
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-11 7:09 ` Eli Zaretskii
@ 2023-04-11 7:22 ` Luis Machado
0 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-11 7:22 UTC (permalink / raw)
To: Eli Zaretskii; +Cc: gdb-patches
Hi Eli,
Thanks for the quick feedback.
On 4/11/23 08:08, Eli Zaretskii wrote:
>> Date: Tue, 11 Apr 2023 05:26:58 +0100
>> From: Luis Machado via Gdb-patches <gdb-patches@sourceware.org>
>>
>> Provide documentation for the SME feature and other information that
>> should be useful for users that need to debug a SME-capable target.
>> ---
>> gdb/NEWS | 11 ++++++++
>> gdb/doc/gdb.texinfo | 68 +++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>
> Thanks.
>
>> diff --git a/gdb/NEWS b/gdb/NEWS
>> index 10a1a70fa52..48a82172f0e 100644
>> --- a/gdb/NEWS
>> +++ b/gdb/NEWS
>> @@ -3,6 +3,17 @@
>>
>> *** Changes since GDB 13
>>
>> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
>> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
>> + length register SVG (streaming vector granule). GDB also supports tracking
>> + ZA state across signal frames.
>> +
>> + Some features are still under development or are dependent on ABI specs that
>> + are still in alpha stage. For example, manual function calls with ZA state
>> + don't have any special handling, and tracking of SVG changes based on
>> + DWARF information is still not implemented, but there are plans to do so in
>> + the future.
>> +
>> * GDB now has some support for integer types larger than 64 bits.
>
> This part is OK.
>
>> +@subsubsection AArch64 SME.
>> +@cindex AArch64 SME.
>
> Please also add a @cindex entry with the full name: scalable matrix
> extension.
>
>> +The @code{za} register is a 2-dimensional vector of bytes with a size of svl
>> +x svl, where svl is the streaming vector length.
>
> I suggest to rephrase:
>
> The @code{za} register is a 2-dimensional rectangular
> @code{@var{n}x@var{n}} matrix of bytes, where @var{n} is the
> streaming vector length.
>
> Should the text also explain what is this "streaming vector", its
> length and "granule"? The text seems to use these terms all over
> assuming the reader knows what they mean.
>
>> +The @code{svg} vector is the streaming vector granule for the current thread
> ^^^^^^
> "register", not "vector", right?
>
>> +and represents the number of 64-bit chunks in one dimension of the @code{za}
>> +register.
>
> What do you mean by "represents the number"? how can one "represent" a
> number?
>
> Also, it sounds like the @var{n} I suggested to use above is related
> to this register, in which case the description of ZA should make that
> relation explicit. (I can suggest how once I understand the subject
> well enough, see the questions above.)
>
>> +The @code{svcr} register (streaming vector control register) is a status
>> +register that holds two state bits: @code{SM} in bit 0 and @code{ZA} in bit 1.
>
> I suggest to use @sc{sm} and @sc{za} here, instead of @code{SM} and
> @code{ZA}. Try that in PDF and see which you like better. (Note that
> @sc has its effect only on lower-case characters of its argument.)
>
>> +If the @code{SM} bit is 1, it means the current thread is in streaming
>> +mode, and the SVE registers will have their sizes based on the @code{svg}
>> +register.
>
> What does it mean for "the SVE registers will have their sizes based
> on the @code{svg} register"? The text should explain this more
> explicitly, IMO.
>
>> If the @code{SM} bit is 0, the current thread is not in streaming
>> +mode, and the SVE registers have sizes based on the @code{vg} register.
>
> This refers to stuff explained elsewhere (the 'vg' register), so a
> cross-reference is in order.
>
>> +If the @code{ZA} state is 0, the @code{za} register and its pseudo registers
>> +will read as <unavailable>.
>
> What are the pseudo registers of the ZA register? I don't think they
> were described earlier in the text.
>
>> +The minimum size of the @code{za} register is there 16 x 16 bytes, and the
>> +maximum size is 256 x 256 bytes. The size of the @code{za} register is the
>> +size of all the SVE @code{z} registers combined.
>
> By "The size of the @code{za} register" do you mean the number of
> bytes in the matrix? That is, if ZA is 16 x 16, then its size is
> 16*16=256 bytes, or is it 16 bytes?
>
>> +The @code{za} register can also be referenced using tiles and tile slices.
>
> Referenced how? Should the text say anything specific about this
> slice referencing, before talking (below) about the number of slices?
>
>> +There is a fixed number of @code{za} tile pseudo registers (32). They are:
>> +za0b, za0h, za1h, zas0, zas1, zas2, zas3, zad0, zad1, zad2, zad3, zad4, zad5.
>
> This should probably preceded by something like
>
> A @dfn{tile} of the @code{za} register is a pseudo-register which
> can be used to... <add here what these tiles are used for>".
>
>> +The tile slice pseudo registers are numerous. For a minimum streaming vector
>> +length of 16 bytes, there are 5 x 32 pseudo registers. For the maximum
>> +streaming vector length of 256 bytes, there are 5 x 512 pseudo registers.
>> +
>> +The tile slice pseudo registers have the following naming pattern:
>> +
>> +za<tile number><orientation><slice number>.
>
> Likewise here: there should be a short explanation of what are tile
> slices and how to use them.
>
> All in all, I find this description rather terse and almost
> impenetrable. I guess only those who are already familiar with this
> architecture will fully understand it. Maybe this is the assumption
> for the readers of this stuff, but then perhaps include a reference to
> some external description of the architecture, and just say that GDB
> supports this and that registers and pseudo-registers, without going
> into any details regarding the meaning and purpose of each one of
> them.
As is usually the case, developers tend to assume some of the subject matter is already understood by
whoever is developing software using a particular architectural feature. :-)
I agree the current documentation is a bit on the light side. Let me try to fill the gaps in v2.
Hopefully that will make the description of how SME is being used in gdb a bit more clear.
>
>> +@samp{za} is a vector of bytes of size svl x svl. @samp{svg} is a 64-bit
>> +pseudo register containing the number of 64-bit chunks in svl. @samp{svcr}
>> +is a 64-bit state register containing bits 0 (SM) and 1 (ZA).
>
> This again mentions "svl" without saying anything about it.
>
> Reviewed-By: Eli Zaretskii <eliz@gnu.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH,v2 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-11 4:26 ` [PATCH 17/17] [gdb/docs] sme: Document SME registers and features Luis Machado
2023-04-11 7:09 ` Eli Zaretskii
@ 2023-04-12 12:04 ` Luis Machado
2023-04-13 7:57 ` Eli Zaretskii
2023-04-17 17:19 ` [PATCH,v3 " Luis Machado
2 siblings, 1 reply; 38+ messages in thread
From: Luis Machado @ 2023-04-12 12:04 UTC (permalink / raw)
To: gdb-patches, eliz
Updates since v1:
- Made SME text more thorough.
- Adjusted text based on upstream reviews.
- Fixed documentation errors (missing itemization for SME registers).
Provide documentation for the SME feature and other information that
should be useful for users that need to debug a SME-capable target.
---
gdb/NEWS | 11 +++
gdb/doc/gdb.texinfo | 223 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 234 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index 10a1a70fa52..48a82172f0e 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -3,6 +3,17 @@
*** Changes since GDB 13
+* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
+ a new matrix register named ZA, a new thread register TPIDR2 and a new vector
+ length register SVG (streaming vector granule). GDB also supports tracking
+ ZA state across signal frames.
+
+ Some features are still under development or are dependent on ABI specs that
+ are still in alpha stage. For example, manual function calls with ZA state
+ don't have any special handling, and tracking of SVG changes based on
+ DWARF information is still not implemented, but there are plans to do so in
+ the future.
+
* GDB now has some support for integer types larger than 64 bits.
* Removed targets and native configurations
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 45a0580bc29..ef6dfd02623 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -26045,6 +26045,202 @@ but the lengths of the @code{z} and @code{p} registers will not change. This
is a known limitation of @value{GDBN} and does not affect the execution of the
target process.
+For SVE, the following definitions are used throughout @value{GDBN}'s source
+code and in this document:
+
+@itemize
+
+@item
+@anchor{VL}
+@cindex VL
+@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
+register.
+
+@item
+@anchor{VQ}
+@cindex VQ
+@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@item
+@anchor{VG}
+@cindex VG
+@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@end itemize
+
+@subsubsection AArch64 SME.
+@anchor{AArch64 SME}
+@cindex SME
+@cindex AArch64 SME
+@cindex Scalable Matrix Extension
+
+The Scalable Matrix Extension (@url{https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture, @acronym{SME}})
+is an AArch64 architecture extension that expands on the concept of the
+Scalable Vector Extension (@url{https://developer.arm.com/documentation/101726/4-0/Learn-about-the-Scalable-Vector-Extension--SVE-/What-is-the-Scalable-Vector-Extension-, @acronym{SVE}})
+by providing a 2-dimensional square matrix of variable size called @code{ZA},
+just like SVE provides a group of vector registers of variable size, the
+32 @code{Z} registers.
+
+Similarly to SVE, where the size of each @code{Z} register is directly related
+to the vector length (@code{VL} for short), the @acronym{SME} @code{ZA} matrix
+register's size is directly related to the streaming vector length
+(@code{SVL} for short). @xref{VL} @xref{SVL}
+
+For more information about @acronym{SME}, please refer to official
+@url{https://developer.arm.com/documentation/ddi0487/latest, architecture
+documentation}.
+
+The following definitions are used throughout @value{GDBN}'s source code and
+in this document:
+
+@itemize
+
+@item
+@anchor{SVL}
+@cindex SVL
+@code{SVL}: The streaming vector length, in bytes. It defines the size of each
+dimension of the 2-dimensional square @code{ZA} matrix. The total size of
+@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
+
+@item
+@anchor{SVQ}
+@cindex SVQ
+@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@item
+@anchor{SVG}
+@cindex SVG
+@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@end itemize
+
+When @value{GDBN} is debugging the AArch64 architecture, if the Scalable Matrix
+Extension (@acronym{SME}) is present, then @value{GDBN} will make the @code{za}
+register available. @value{GDBN} will also make the @code{svg} and @code{svcr}
+pseudo-registers available.
+
+The @code{za} register is a 2-dimensional square @code{@var{n}x@var{n}}
+matrix of bytes, where @var{n} is the streaming vector length (@code{SVL}. To
+simplify the representation and access to the @code{za} register in
+@value{GDBN}, it is defined as a vector of @code{@var{n}x@var{n}} bytes.
+@xref{SVL}
+
+If the user wants to index the @code{za} register as a matrix, it is possible
+to reference @code{za} as @code{za[i][j]}, where @var{i} is the row number
+and @var{j} is the column number.
+
+The @code{svg} register is the streaming vector granule (@code{SVG}) for the
+current thread. @xref{SVG}
+
+@anchor{aarch64 sme svcr}
+The @code{svcr} register (streaming vector control register) is a status
+register that holds two state bits: @sc{sm} in bit 0 and @sc{za} in bit 1.
+
+If the @sc{sm} bit is 1, it means the current thread is in streaming
+mode, and the SVE registers will have their sizes based on the @code{svg}
+register. If the @sc{sm} bit is 0, the current thread is not in streaming
+mode, and the SVE registers have sizes based on the @code{vg} register.
+@xref{VG}. @xref{SVG}.
+
+If the @sc{za} bit is 1, it means the @code{ZA} state, and therefore the
+@code{za} register, is being used and has meaningful contents. If the
+@sc{za} bit is 0, the @code{ZA} state is unavailable and the contents of the
+@code{za} register are undefined.
+
+For convenience and simplicity, if the @sc{za} bit is 0, the @code{za}
+register and all of its pseudo-registers will read as zero.
+
+If the streaming vector length changes, then the @code{svg} pseudo-register
+will be updated, as well as the @code{za} register size and the bits in the
+@code{svcr} pseudo-register.
+
+Setting the @code{svg} register to the same value will have no
+effect. Whenever the @code{svg} register is modified with a new value, the
+following will be observed:
+
+@itemize
+
+@item The @sc{za} and @sc{sm} bits will be cleared in the @code{svcr}
+register.
+
+@item The @code{za} register will have a new size and its state will be
+cleared, forcing its contents and the contents of all of its pseudo-registers
+back to zero.
+
+@item If the @sc{sm} bit was 1, the SVE registers will be reset to having
+their sizes dictated by the @code{vg} register as opposed to the @code{svg}
+register. If the @sc{sm} bit was 0 prior to modifying @code{svg}, there
+will be no observable effect on the SVE registers.
+
+@end itemize
+
+The possible values for @code{svg} are 2, 4, 8, 16, 32 (1, 2, 4, 8, 16
+for svq). These numbers correspond to streaming vector length values of 16
+bytes, 32 bytes, 64 bytes, 128 bytes and 256 bytes.
+
+The minimum size of the @code{za} register is 16 x 16 (256) bytes, and the
+maximum size is 256 x 256 (65536) bytes. In streaming mode, with bit @sc{sm}
+set, the size of the @code{za} register is the size of all the SVE @code{z}
+registers combined.
+
+The @code{za} register can also be accessed using tiles and tile slices.
+
+Tile pseudo-registers are square, 2-dimensional sub-arrays of elements within
+the @code{za} register.
+
+There is a fixed number of @code{za} tile pseudo registers (32). They are
+@code{za0b}, @code{za0h} through @code{za1h}, @code{zas0} through @code{zas3},
+@code{zad0} through @code{zad7} and @code{zaq0} through @code{zaq15}.
+
+Tile slice pseudo-registers are vectors of horizontally or vertically
+contiguous elements within the @code{za} register.
+
+The tile slice pseudo-registers are numerous. For a minimum streaming vector
+length of 16 bytes, there are 5 x 32 pseudo registers. For the maximum
+streaming vector length of 256 bytes, there are 5 x 512 pseudo registers.
+
+The tile slice pseudo registers have the following naming pattern:
+za<@var{tile number}><@var{orientation}><@var{slice number}>.
+
+There are up to 16 tiles (0 ~ 15), the orientation can be either vertical (v)
+or horizontal (h) and there are up to 256 slices (0 ~ 255) depending on the
+value of @code{svg}.
+
+When listing all the available registers, users will see the
+currently-available @code{za} pseudo-registers. Pseudo-registers that don't
+exist for a given @code{svg} value will not be displayed.
+
+For more information on @acronym{SME} and its terminology, please refer to the
+@url{https://developer.arm.com/documentation/ddi0616/aa/,
+Arm Architecture Reference Manual Supplement}, The Scalable Matrix Extension
+(@acronym{SME}), for Armv9-A.
+
+Some features are still under development and rely on ACLE and ABI
+definitions, so there are known limitations to the current @acronym{SME}
+support in @value{GDBN}.
+
+One such example is calling functions by hand from @value{GDBN}. Hand calls
+are not @acronym{SME}-aware and thus don't take into account the @code{svcr}
+bits nor the @code{za} contents.
+
+The lazy saving scheme involving the @code{tpidr2} register is not yet
+supported by @value{GDBN}, though the @code{tpidr2} register is known
+and supported by @value{GDBN}.
+
+Lastly, an important limitation for @code{gdbserver} is its inability to
+communicate changes in the streaming vector length to @value{GDBN}. This
+means @code{gdbserver}, even though it is capable of adjusting its internal
+caches to reflect a change to @code{svg}, will operate with a potentially
+different @code{svg} value compared to @value{GDBN}. This can lead to
+@value{GDBN} showing incorrect values for the @code{za} register and
+incorrect values for SVE registers (when the @sc{m} bit is on).
+
+This is the same limitation we have for the SVE registers.
+
@subsubsection AArch64 Pointer Authentication.
@cindex AArch64 Pointer Authentication.
@anchor{AArch64 PAC}
@@ -48037,6 +48233,33 @@ This restriction may be lifted in the future.
Extra registers are allowed in this feature, but they will not affect
@value{GDBN}.
+@subsubsection AArch64 SME registers feature
+
+The @samp{org.gnu.gdb.aarch64.sme} feature is optional. If present,
+it should contain registers @samp{za}, @samp{svg} and @samp{svcr}.
+@xref{AArch64 SME}
+
+@itemize @minus
+
+@item
+@samp{za} is a vector of bytes of size svl x svl.
+
+@item
+@samp{svg} is a 64-bit pseudo register containing the number of 64-bit chunks
+in svl. @xref{SVG}
+
+@item
+@samp{svcr} is a 64-bit state register containing bits 0 (@sc{sm}) and
+1 (@sc{za}). @xref{aarch64 sme svcr}
+
+The rest of the unused bits of @samp{svcr} is undefined and reserved. They
+should not be used and may be defined by future extensions of the architecture.
+
+@end itemize
+
+Extra registers are allowed in this feature, but they will not affect
+@value{GDBN}.
+
@node ARC Features
@subsection ARC Features
@cindex target descriptions, ARC Features
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v2 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-12 12:04 ` [PATCH,v2 " Luis Machado
@ 2023-04-13 7:57 ` Eli Zaretskii
2023-04-13 12:17 ` Luis Machado
0 siblings, 1 reply; 38+ messages in thread
From: Eli Zaretskii @ 2023-04-13 7:57 UTC (permalink / raw)
To: Luis Machado; +Cc: gdb-patches
> From: Luis Machado <luis.machado@arm.com>
> Date: Wed, 12 Apr 2023 13:04:44 +0100
>
> Updates since v1:
>
> - Made SME text more thorough.
> - Adjusted text based on upstream reviews.
> - Fixed documentation errors (missing itemization for SME registers).
>
> Provide documentation for the SME feature and other information that
> should be useful for users that need to debug a SME-capable target.
> ---
> gdb/NEWS | 11 +++
> gdb/doc/gdb.texinfo | 223 ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 234 insertions(+)
Thanks.
> diff --git a/gdb/NEWS b/gdb/NEWS
> index 10a1a70fa52..48a82172f0e 100644
> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -3,6 +3,17 @@
>
> *** Changes since GDB 13
>
> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
> + length register SVG (streaming vector granule). GDB also supports tracking
> + ZA state across signal frames.
> +
> + Some features are still under development or are dependent on ABI specs that
> + are still in alpha stage. For example, manual function calls with ZA state
> + don't have any special handling, and tracking of SVG changes based on
> + DWARF information is still not implemented, but there are plans to do so in
> + the future.
This part is OK.
> +For SVE, the following definitions are used throughout @value{GDBN}'s source
> +code and in this document:
> +
> +@itemize
> +
> +@item
> +@anchor{VL}
> +@cindex VL
> +@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
> +register.
> +
> +@item
> +@anchor{VQ}
> +@cindex VQ
> +@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
> +
> +@item
> +@anchor{VG}
> +@cindex VG
> +@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
I suggest to call these parameters @var{nvl}, @var{nvq}, and
@var{nvg}, respectively. That is: (1) lower-case names, (2) name them
differently from the corresponding register, and (3) use @var markup.
This could mean the names are no longer identical to what you use in
the GDB sources, but the text is easier to read and less confusing,
because, for example, the difference between SVG the parameter and SVG
the register name is tricky, and confused even you (or at least it
confused me, see below).
> +by providing a 2-dimensional square matrix of variable size called @code{ZA},
> +just like SVE provides a group of vector registers of variable size, the
> +32 @code{Z} registers.
ZA is a register, no? Then I suggest
by providing a 2-dimensional register @code{ZA}, which is a square
matrix of variable size, just like [...]
> +The following definitions are used throughout @value{GDBN}'s source code and
> +in this document:
> +
> +@itemize
> +
> +@item
> +@anchor{SVL}
> +@cindex SVL
> +@code{SVL}: The streaming vector length, in bytes. It defines the size of each
> +dimension of the 2-dimensional square @code{ZA} matrix. The total size of
> +@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
> +
> +@item
> +@anchor{SVQ}
> +@cindex SVQ
> +@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
> +
> +@item
> +@anchor{SVG}
> +@cindex SVG
> +@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
Likewise here: I suggest to use @var{nsvl} etc. for these parameters.
> +The @code{za} register is a 2-dimensional square @code{@var{n}x@var{n}}
> +matrix of bytes, where @var{n} is the streaming vector length (@code{SVL}.
Here you could use the parameter explicitly:
The @code{za} register is a 2-dimensional square
@code{@var{nsvl}x@var{nsvl}} matrix of bytes.
> +@xref{SVL}
This reference is unnecessary, as the description is only a short ways
above, and in the same node.
> +If the user wants to index the @code{za} register as a matrix, it is possible
> +to reference @code{za} as @code{za[i][j]}, where @var{i} is the row number
^^^^^^^^^^^^^^^
This should be @code{za[@var{i}][@var{j}]}.
> +The @code{svg} register is the streaming vector granule (@code{SVG}) for the
> +current thread. @xref{SVG}
Likewise: the @xref is not necessary.
> +If the @sc{sm} bit is 1, it means the current thread is in streaming
> +mode, and the SVE registers will have their sizes based on the @code{svg}
> +register. If the @sc{sm} bit is 0, the current thread is not in streaming
> +mode, and the SVE registers have sizes based on the @code{vg} register.
> +@xref{VG}. @xref{SVG}.
Here, only the cross-reference to VG is necessary.
> +Setting the @code{svg} register to the same value will have no
> +effect.
What do you mean by "same" here? Do you mean to say that setting SVG
is only meaningful if the value is different from its current value?
> +The possible values for @code{svg} are 2, 4, 8, 16, 32 (1, 2, 4, 8, 16
> +for svq).
Are these values for the SVG register or for the SVG parameter? Same
question about the reference to "svq".
> These numbers correspond to streaming vector length values of 16
> +bytes, 32 bytes, 64 bytes, 128 bytes and 256 bytes.
Same question here: are these the values of the SVL parameter?
> +There is a fixed number of @code{za} tile pseudo registers (32). They are
> +@code{za0b}, @code{za0h} through @code{za1h}, @code{zas0} through @code{zas3},
> +@code{zad0} through @code{zad7} and @code{zaq0} through @code{zaq15}.
Something is amiss here, I think, since I only get 31 when I add the
above numbers (1+2+4+8+16). What did I miss?
> +Tile slice pseudo-registers are vectors of horizontally or vertically
> +contiguous elements within the @code{za} register.
> +
> +The tile slice pseudo-registers are numerous. For a minimum streaming vector
> +length of 16 bytes, there are 5 x 32 pseudo registers. For the maximum
> +streaming vector length of 256 bytes, there are 5 x 512 pseudo registers.
An explanation of why 5 and why 32 or 512 will help here, I think.
> +The tile slice pseudo registers have the following naming pattern:
> +za<@var{tile number}><@var{orientation}><@var{slice number}>.
> +
> +There are up to 16 tiles (0 ~ 15), the orientation can be either vertical (v)
> +or horizontal (h) and there are up to 256 slices (0 ~ 255) depending on the
> +value of @code{svg}.
^^^^^^^^^^^^^^^^^^^
Is this the SVG parameter or the value of the SVG register?
> +When listing all the available registers, users will see the
> +currently-available @code{za} pseudo-registers. Pseudo-registers that don't
> +exist for a given @code{svg} value will not be displayed.
^^^^^^^^^^^^^^^^
Same question here.
> +For more information on @acronym{SME} and its terminology, please refer to the
> +@url{https://developer.arm.com/documentation/ddi0616/aa/,
> +Arm Architecture Reference Manual Supplement}, The Scalable Matrix Extension
> +(@acronym{SME}), for Armv9-A.
> +
> +Some features are still under development and rely on ACLE and ABI
> +definitions, so there are known limitations to the current @acronym{SME}
> +support in @value{GDBN}.
What is "ACLE"? It is not used anywhere else in the manual, AFAICT.
> +One such example is calling functions by hand from @value{GDBN}. Hand calls
> +are not @acronym{SME}-aware and thus don't take into account the @code{svcr}
> +bits nor the @code{za} contents.
I believe we refer to such calls as "calling functions in the program
being debugged", not "calling by hand". Also, a cross-reference to
the "Calling" node would be beneficial here.
> +The lazy saving scheme involving the @code{tpidr2} register is not yet
> +supported by @value{GDBN}, though the @code{tpidr2} register is known
> +and supported by @value{GDBN}.
What is the "lazy saving scheme"? If it's described somewhere in the
manual, please use here the same terminology as there, and please
include a cross-reference to that place.
> +Lastly, an important limitation for @code{gdbserver} is its inability to
> +communicate changes in the streaming vector length to @value{GDBN}. This
> +means @code{gdbserver}, even though it is capable of adjusting its internal
> +caches to reflect a change to @code{svg}, will operate with a potentially
> +different @code{svg} value compared to @value{GDBN}. This can lead to
> +@value{GDBN} showing incorrect values for the @code{za} register and
> +incorrect values for SVE registers (when the @sc{m} bit is on).
Is it really reasonable to release this feature given this glaring
limitation?
> +@item
> +@samp{za} is a vector of bytes of size svl x svl.
See the comments above: I'd use
[...] rectangular matrix bytes of the size @code{@var{nsvl}x@var{nsvl}}
> +@item
> +@samp{svg} is a 64-bit pseudo register containing the number of 64-bit chunks
> +in svl. @xref{SVG}
^^
Two spaces there.
> +@item
> +@samp{svcr} is a 64-bit state register containing bits 0 (@sc{sm}) and
> +1 (@sc{za}). @xref{aarch64 sme svcr}
^^
And there.
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v2 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-13 7:57 ` Eli Zaretskii
@ 2023-04-13 12:17 ` Luis Machado
[not found] ` <83leiv4xsc.fsf@gnu.org>
0 siblings, 1 reply; 38+ messages in thread
From: Luis Machado @ 2023-04-13 12:17 UTC (permalink / raw)
To: Eli Zaretskii; +Cc: gdb-patches
Hi Eli,
Thanks for the feedback on the documentation. I have some comments about your suggestion, but I think
we're converging.
On 4/13/23 08:57, Eli Zaretskii wrote:
>> From: Luis Machado <luis.machado@arm.com>
>> Date: Wed, 12 Apr 2023 13:04:44 +0100
>>
>> Updates since v1:
>>
>> - Made SME text more thorough.
>> - Adjusted text based on upstream reviews.
>> - Fixed documentation errors (missing itemization for SME registers).
>>
>> Provide documentation for the SME feature and other information that
>> should be useful for users that need to debug a SME-capable target.
>> ---
>> gdb/NEWS | 11 +++
>> gdb/doc/gdb.texinfo | 223 ++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 234 insertions(+)
>
> Thanks.
>
>> diff --git a/gdb/NEWS b/gdb/NEWS
>> index 10a1a70fa52..48a82172f0e 100644
>> --- a/gdb/NEWS
>> +++ b/gdb/NEWS
>> @@ -3,6 +3,17 @@
>>
>> *** Changes since GDB 13
>>
>> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
>> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
>> + length register SVG (streaming vector granule). GDB also supports tracking
>> + ZA state across signal frames.
>> +
>> + Some features are still under development or are dependent on ABI specs that
>> + are still in alpha stage. For example, manual function calls with ZA state
>> + don't have any special handling, and tracking of SVG changes based on
>> + DWARF information is still not implemented, but there are plans to do so in
>> + the future.
>
> This part is OK.
>
>> +For SVE, the following definitions are used throughout @value{GDBN}'s source
>> +code and in this document:
>> +
>> +@itemize
>> +
>> +@item
>> +@anchor{VL}
>> +@cindex VL
>> +@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
>> +register.
>> +
>> +@item
>> +@anchor{VQ}
>> +@cindex VQ
>> +@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>> +
>> +@item
>> +@anchor{VG}
>> +@cindex VG
>> +@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>
> I suggest to call these parameters @var{nvl}, @var{nvq}, and
> @var{nvg}, respectively. That is: (1) lower-case names, (2) name them
> differently from the corresponding register, and (3) use @var markup.
> This could mean the names are no longer identical to what you use in
> the GDB sources, but the text is easier to read and less confusing,
> because, for example, the difference between SVG the parameter and SVG
> the register name is tricky, and confused even you (or at least it
> confused me, see below).
>
I'm not sure that would be a good idea. These definitions (VL, VG and VQ, as well as the SME counterparts SVL, SVG and SVQ)
are supposed to provide different views into the same data, the SVE vector length or the SME vector length.
They are only supposed to help describe the concept of SVE/SME.
When we're talking about how gdb implements SVE and SME, then we're talking about registers vg and svg, which
map directly to the VG and SVG definitions.
I may be leaking some implementation details to the user's manual. Would it help if we only mention
these definitions when explaining the concept, but then restrict ourselves to only using the
vg and svg registers when explaining how gdb deals with SVE and SME?
But it is convenient, when detailing the sizes of registers, to use SVL, which doesn't have a
direct mapping to a gdb register.
>> +by providing a 2-dimensional square matrix of variable size called @code{ZA},
>> +just like SVE provides a group of vector registers of variable size, the
>> +32 @code{Z} registers.
>
> ZA is a register, no? Then I suggest
>
> by providing a 2-dimensional register @code{ZA}, which is a square
> matrix of variable size, just like [...]
>
Fixed.
>> +The following definitions are used throughout @value{GDBN}'s source code and
>> +in this document:
>> +
>> +@itemize
>> +
>> +@item
>> +@anchor{SVL}
>> +@cindex SVL
>> +@code{SVL}: The streaming vector length, in bytes. It defines the size of each
>> +dimension of the 2-dimensional square @code{ZA} matrix. The total size of
>> +@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
>> +
>> +@item
>> +@anchor{SVQ}
>> +@cindex SVQ
>> +@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>> +
>> +@item
>> +@anchor{SVG}
>> +@cindex SVG
>> +@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>
> Likewise here: I suggest to use @var{nsvl} etc. for these parameters.
>
Pending on my first point above.
>> +The @code{za} register is a 2-dimensional square @code{@var{n}x@var{n}}
>> +matrix of bytes, where @var{n} is the streaming vector length (@code{SVL}.
>
> Here you could use the parameter explicitly:
>
> The @code{za} register is a 2-dimensional square
> @code{@var{nsvl}x@var{nsvl}} matrix of bytes.
>
I'm having a hard time seeing the benefits of renaming SVL/SVQ/SVG to nsvl, nsvq and nsvg.
The definition for SVL/SVQ/SVG is made clear above, at least I see it that way.
My intent is to introduce SME enough so users are aware this feature is supported by gdb and are aware of
how gdb exposes it.
>> +@xref{SVL}
>
> This reference is unnecessary, as the description is only a short ways
> above, and in the same node.
>
Removed now.
>> +If the user wants to index the @code{za} register as a matrix, it is possible
>> +to reference @code{za} as @code{za[i][j]}, where @var{i} is the row number
> ^^^^^^^^^^^^^^^
> This should be @code{za[@var{i}][@var{j}]}.
>
Fixed now.
>> +The @code{svg} register is the streaming vector granule (@code{SVG}) for the
>> +current thread. @xref{SVG}
>
> Likewise: the @xref is not necessary.
>
Removed.
>> +If the @sc{sm} bit is 1, it means the current thread is in streaming
>> +mode, and the SVE registers will have their sizes based on the @code{svg}
>> +register. If the @sc{sm} bit is 0, the current thread is not in streaming
>> +mode, and the SVE registers have sizes based on the @code{vg} register.
>> +@xref{VG}. @xref{SVG}.
>
> Here, only the cross-reference to VG is necessary.
>
Fixed now.
>> +Setting the @code{svg} register to the same value will have no
>> +effect.
>
> What do you mean by "same" here? Do you mean to say that setting SVG
> is only meaningful if the value is different from its current value?
>
It means if svg is 2 and you attempt to set it to 2 nothing will change in the
register state. Then again, gdb already enforces this, I think.
I want to convey the information that the SME statw won't be reset if we accidentaly
set svg to the same value (possibly an implementation detail that shouldn't be in the
manual?).
>> +The possible values for @code{svg} are 2, 4, 8, 16, 32 (1, 2, 4, 8, 16
>> +for svq).
>
> Are these values for the SVG register or for the SVG parameter? Same
> question about the reference to "svq".
>
The svg values are for both the register and the parameter. They are the same thing.
As stated before, svg (the register) is simply how gdb exposes SVG (the definition).
svq is only a concept. No registers expose it directly (though gdb uses this in the code).
svl is the exact same situation as svq. It is a concept and there is no register exposing its
value directly, but we use it internally in gdb's code.
This is an extension to what SVE already established with vg, vq and vl.
I can see where there is some confusion with the uppercase/lowercase uses of svq/svl. I've
rectified that. Given svq/svl don't have register counterparts, I think it is fair to always use
SVQ/SVL.
>> These numbers correspond to streaming vector length values of 16
>> +bytes, 32 bytes, 64 bytes, 128 bytes and 256 bytes.
>
> Same question here: are these the values of the SVL parameter?
>
Yes. I describe the case for svg values (register/parameter), SVQ values and SVL values.
I've rephrased this slightly to...
The possible values for the @code{svg} register are 2, 4, 8, 16, 32 (1, 2, 4,
8, 16 for @code{SVQ}). These numbers correspond to streaming vector length
(@code{SVL}) values of 16 bytes, 32 bytes, 64 bytes, 128 bytes and 256 bytes respectively.
>> +There is a fixed number of @code{za} tile pseudo registers (32). They are
>> +@code{za0b}, @code{za0h} through @code{za1h}, @code{zas0} through @code{zas3},
>> +@code{zad0} through @code{zad7} and @code{zaq0} through @code{zaq15}.
>
> Something is amiss here, I think, since I only get 31 when I add the
> above numbers (1+2+4+8+16). What did I miss?
>
Yeah, that's a typo. It should really be 31. Thanks for catching that.
I might have read this too many times.
>> +Tile slice pseudo-registers are vectors of horizontally or vertically
>> +contiguous elements within the @code{za} register.
>> +
>> +The tile slice pseudo-registers are numerous. For a minimum streaming vector
>> +length of 16 bytes, there are 5 x 32 pseudo registers. For the maximum
>> +streaming vector length of 256 bytes, there are 5 x 512 pseudo registers.
>
> An explanation of why 5 and why 32 or 512 will help here, I think.
>
I noticed I missed a part of the tile slice register naming. I've reordered this block
and rewritten some of it. How does it look?
The tile slice pseudo registers have the following naming pattern:
@code{za<@var{tile number}><@var{direction}>@var{qualifier}
<@var{slice number}>}.
There are up to 16 tiles (0 ~ 15), the direction can be either @code{v}
(vertical) or @code{h} (horizontal), the qualifiers can be @code{b} (byte),
@code{h} (halfword), @code{s} (word), @code{d} (doubleword) and @code{q}
(quadword) and there are up to 256 slices (0 ~ 255) depending on the value
of @code{svg}. The number of slices is the same as the value of @code{SVL}.
The number of available tile slice pseudo-registers can be large. For a
minimum @code{SVL} of 16 bytes, there are 5 (number of qualifiers) x
2 (number of directions) x 16 (@code{SVL}) pseudo registers. For the
maximum @code{SVL} of 256 bytes, there are 5 x 2 x 256 pseudo registers.
>> +The tile slice pseudo registers have the following naming pattern:
>> +za<@var{tile number}><@var{orientation}><@var{slice number}>.
>> +
>> +There are up to 16 tiles (0 ~ 15), the orientation can be either vertical (v)
>> +or horizontal (h) and there are up to 256 slices (0 ~ 255) depending on the
>> +value of @code{svg}.
> ^^^^^^^^^^^^^^^^^^^
> Is this the SVG parameter or the value of the SVG register?
>
Same situation as before. Given SVG is represented by a register svg, I'm talking about the register.
>> +When listing all the available registers, users will see the
>> +currently-available @code{za} pseudo-registers. Pseudo-registers that don't
>> +exist for a given @code{svg} value will not be displayed.
> ^^^^^^^^^^^^^^^^
> Same question here.
>
Same as above.
>> +For more information on @acronym{SME} and its terminology, please refer to the
>> +@url{https://developer.arm.com/documentation/ddi0616/aa/,
>> +Arm Architecture Reference Manual Supplement}, The Scalable Matrix Extension
>> +(@acronym{SME}), for Armv9-A.
>> +
>> +Some features are still under development and rely on ACLE and ABI
>> +definitions, so there are known limitations to the current @acronym{SME}
>> +support in @value{GDBN}.
>
> What is "ACLE"? It is not used anywhere else in the manual, AFAICT.
>
Arm C Language Extensions. I've added a link to it and to the ABI document, like so:
Some features are still under development and rely on
@url{https://github.com/ARM-software/acle/releases/latest, ACLE} and
@url{https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst, ABI}
definitions, so there are known limitations to the current @acronym{SME}
support in @value{GDBN}.
>> +One such example is calling functions by hand from @value{GDBN}. Hand calls
>> +are not @acronym{SME}-aware and thus don't take into account the @code{svcr}
>> +bits nor the @code{za} contents.
>
> I believe we refer to such calls as "calling functions in the program
> being debugged", not "calling by hand". Also, a cross-reference to
> the "Calling" node would be beneficial here.
>
Probably implementor speak here. I've fixed it now. It should say the following:
One such example is calling functions in the program being debugged by
@value{GDBN}. Such calls are not @acronym{SME}-aware and thus don't take into
account the @code{svcr} pseudo-register bits nor the @code{za} register
contents.
>> +The lazy saving scheme involving the @code{tpidr2} register is not yet
>> +supported by @value{GDBN}, though the @code{tpidr2} register is known
>> +and supported by @value{GDBN}.
>
> What is the "lazy saving scheme"? If it's described somewhere in the
> manual, please use here the same terminology as there, and please
> include a cross-reference to that place.
>
It is described in the ABI. I've added a link to the ABI document and the section
describing it:
The @url{https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#the-za-lazy-saving-scheme,
lazy saving scheme} involving the @code{tpidr2} register is not yet supported
by @value{GDBN}, though the @code{tpidr2} register is known and supported
by @value{GDBN}.
>> +Lastly, an important limitation for @code{gdbserver} is its inability to
>> +communicate changes in the streaming vector length to @value{GDBN}. This
>> +means @code{gdbserver}, even though it is capable of adjusting its internal
>> +caches to reflect a change to @code{svg}, will operate with a potentially
>> +different @code{svg} value compared to @value{GDBN}. This can lead to
>> +@value{GDBN} showing incorrect values for the @code{za} register and
>> +incorrect values for SVE registers (when the @sc{m} bit is on).
>
> Is it really reasonable to release this feature given this glaring
> limitation?
>
I think it isn't great, but OK. This has been a limitation for SVE since its inception. I proposed
changes to fix this issue a while ago, and, more recently, Thiago has picked up this work and is
working on a potential fix. Once fixed for the SVE case, it will be trivial to make it work for
SME as well. I think this is also a limitation for Intel AMX.
The rationale for it being OK is that changes to the SVE vector length and SME vector length that
happen mid-execution of a program are very unlikely. The most common scenario is a program using
a single vector length throughout its execution.
>> +@item
>> +@samp{za} is a vector of bytes of size svl x svl.
>
> See the comments above: I'd use
>
> [...] rectangular matrix bytes of the size @code{@var{nsvl}x@var{nsvl}}
>
I've adjusted this, provisionally, to the following:
@item
@samp{svg} is a 64-bit pseudo-register containing the number of 64-bit chunks
in @code{SVL}. Its value is equal to @code{SVG}. @xref{SVG}. @xref{SVL}.
>> +@item
>> +@samp{svg} is a 64-bit pseudo register containing the number of 64-bit chunks
>> +in svl. @xref{SVG}
> ^^
> Two spaces there.
>
Fixed.
>> +@item
>> +@samp{svcr} is a 64-bit state register containing bits 0 (@sc{sm}) and
>> +1 (@sc{za}). @xref{aarch64 sme svcr}
> ^^
> And there.
>
Fixed.
> Reviewed-By: Eli Zaretskii <eliz@gnu.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH,v3 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-11 4:26 ` [PATCH 17/17] [gdb/docs] sme: Document SME registers and features Luis Machado
2023-04-11 7:09 ` Eli Zaretskii
2023-04-12 12:04 ` [PATCH,v2 " Luis Machado
@ 2023-04-17 17:19 ` Luis Machado
2023-04-22 9:21 ` Eli Zaretskii
2 siblings, 1 reply; 38+ messages in thread
From: Luis Machado @ 2023-04-17 17:19 UTC (permalink / raw)
To: gdb-patches, eliz
Updates since v2:
- More adjustments based on reviews.
- Fixed incorrect number of tile pseudo-registers.
- Fixed naming of tile slice pseudo-registers.
- More detail about SME and how gdb implements it.
- Attempted to clarify the text a bit more.
Updates since v1:
- Made SME text more thorough.
- Adjusted text based on upstream reviews.
- Fixed documentation errors (missing itemization for SME registers).
Provide documentation for the SME feature and other information that
should be useful for users that need to debug a SME-capable target.
---
gdb/NEWS | 11 ++
gdb/doc/gdb.texinfo | 249 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 260 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index 54b5da21245..e3ce7d7e881 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -3,6 +3,17 @@
*** Changes since GDB 13
+* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
+ a new matrix register named ZA, a new thread register TPIDR2 and a new vector
+ length register SVG (streaming vector granule). GDB also supports tracking
+ ZA state across signal frames.
+
+ Some features are still under development or are dependent on ABI specs that
+ are still in alpha stage. For example, manual function calls with ZA state
+ don't have any special handling, and tracking of SVG changes based on
+ DWARF information is still not implemented, but there are plans to do so in
+ the future.
+
* The AArch64 'org.gnu.gdb.aarch64.pauth' Pointer Authentication feature string
has been deprecated in favor of the 'org.gnu.gdb.aarch64.pauth_v2' feature
string.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 940315b2713..3149e5a6765 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -26045,6 +26045,224 @@ but the lengths of the @code{z} and @code{p} registers will not change. This
is a known limitation of @value{GDBN} and does not affect the execution of the
target process.
+For SVE, the following definitions are used throughout @value{GDBN}'s source
+code and in this document:
+
+@itemize
+
+@item
+@anchor{VL}
+@cindex VL
+@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
+register.
+
+@item
+@anchor{VQ}
+@cindex VQ
+@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@item
+@anchor{VG}
+@cindex VG
+@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@end itemize
+
+@subsubsection AArch64 SME.
+@anchor{AArch64 SME}
+@cindex SME
+@cindex AArch64 SME
+@cindex Scalable Matrix Extension
+
+The Scalable Matrix Extension (@url{https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture, @acronym{SME}})
+is an AArch64 architecture extension that expands on the concept of the
+Scalable Vector Extension (@url{https://developer.arm.com/documentation/101726/4-0/Learn-about-the-Scalable-Vector-Extension--SVE-/What-is-the-Scalable-Vector-Extension-, @acronym{SVE}})
+by providing a 2-dimensional register @code{ZA}, which is a square
+matrix of variable size, just like SVE provides a group of vector registers of
+variable size.
+
+Similarly to SVE, where the size of each @code{Z} register is directly related
+to the vector length (@code{VL} for short), the @acronym{SME} @code{ZA} matrix
+register's size is directly related to the streaming vector length
+(@code{SVL} for short). @xref{VL} @xref{SVL}
+
+The @code{ZA} matrix state can be either active or inactive, if it is not in
+use.
+
+@acronym{SME} also introduces a new execution mode called streaming
+@acronym{SVE} mode (streaming mode for short). When streaming mode is
+enabled, the program supports execution of @acronym{SVE2} instructions and the
+@acronym{SVE} registers will have vector length @code{SVL}. When streaming
+mode is disabled, the SVE registers have vector length @code{VL}.
+
+For more information about @acronym{SME} and @acronym{SVE}, please refer to
+official @url{https://developer.arm.com/documentation/ddi0487/latest,
+architecture documentation}.
+
+The following definitions are used throughout @value{GDBN}'s source code and
+in this document:
+
+@itemize
+
+@item
+@anchor{SVL}
+@cindex SVL
+@code{SVL}: The streaming vector length, in bytes. It defines the size of each
+dimension of the 2-dimensional square @code{ZA} matrix. The total size of
+@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
+
+When streaming mode is enabled, it defines the size of the @acronym{SVE}
+registers as well.
+
+@item
+@anchor{SVQ}
+@cindex SVQ
+@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@item
+@anchor{SVG}
+@cindex SVG
+@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@end itemize
+
+When @value{GDBN} is debugging the AArch64 architecture, if the Scalable Matrix
+Extension (@acronym{SME}) is present, then @value{GDBN} will make the @code{za}
+register available. @value{GDBN} will also make the @code{svg} register and
+@code{svcr} pseudo-register available.
+
+The @code{za} register is a 2-dimensional square @code{@var{SVL}x@var{SVL}}
+matrix of bytes. To simplify the representation and access to the @code{za}
+register in @value{GDBN}, it is defined as a vector of
+@code{@var{SVL}x@var{SVL}} bytes.
+
+If the user wants to index the @code{za} register as a matrix, it is possible
+to reference @code{za} as @code{za[@var{i}][@var{j}]}, where @var{i} is the
+row number and @var{j} is the column number.
+
+The @code{svg} register always contains the streaming vector granule
+(@code{SVG}) for the current thread. From @code{SVG} we can easily derive
+the @code{SVL} value.
+
+@anchor{aarch64 sme svcr}
+The @code{svcr} pseudo-register (streaming vector control register) is a status
+register that holds two state bits: @sc{sm} in bit 0 and @sc{za} in bit 1.
+
+If the @sc{sm} bit is 1, it means the current thread is in streaming
+mode, and the @acronym{SVE} registers will use @code{SVL} for their sizes. If
+the @sc{sm} bit is 0, the current thread is not in streaming mode, and the
+@acronym{SVE} registers will use @code{VG} for their sizes. @xref{VG}.
+
+If the @sc{za} bit is 1, it means the @code{ZA} state, and therefore the
+@code{za} register, is being used and has meaningful contents. If the
+@sc{za} bit is 0, the @code{ZA} state is unavailable and the contents of the
+@code{za} register are undefined.
+
+For convenience and simplicity, if the @sc{za} bit is 0, the @code{za}
+register and all of its pseudo-registers will read as zero.
+
+If @code{SVL} changes during the execution of a program, then the @code{za}
+register size and the bits in the @code{svcr} pseudo-register will be updated
+to reflect it.
+
+It is possible for users to change @code{SVL} during the execution of a
+program by modifying the @code{svg} register value.
+
+Whenever the @code{svg} register is modified with a new value, the
+following will be observed:
+
+@itemize
+
+@item The @sc{za} and @sc{sm} bits will be cleared in the @code{svcr}
+pseudo-register.
+
+@item The @code{za} register will have a new size and its state will be
+cleared, forcing its contents and the contents of all of its pseudo-registers
+back to zero.
+
+@item If the @sc{sm} bit was 1, the @acronym{SVE} registers will be reset to
+having their sizes based on @code{VL} as opposed to @code{SVL}. If the
+@sc{sm} bit was 0 prior to modifying the @code{svg} register, there will be no
+observable effect on the @acronym{SVE} registers.
+
+@end itemize
+
+The possible values for the @code{svg} register are 2, 4, 8, 16, 32. These
+numbers correspond to streaming vector length (@code{SVL}) values of 16
+bytes, 32 bytes, 64 bytes, 128 bytes and 256 bytes respectively.
+
+The minimum size of the @code{za} register is 16 x 16 (256) bytes, and the
+maximum size is 256 x 256 (65536) bytes. In streaming mode, with bit @sc{sm}
+set, the size of the @code{za} register is the size of all the SVE @code{z}
+registers combined.
+
+The @code{za} register can also be accessed using tiles and tile slices.
+
+Tile pseudo-registers are square, 2-dimensional sub-arrays of elements within
+the @code{za} register.
+
+There is a total of 31 @code{za} tile pseudo-registers. They are
+@code{za0b}, @code{za0h} through @code{za1h}, @code{zas0} through @code{zas3},
+@code{zad0} through @code{zad7} and @code{zaq0} through @code{zaq15}.
+
+Tile slice pseudo-registers are vectors of horizontally or vertically
+contiguous elements within the @code{za} register.
+
+The tile slice pseudo-registers have the following naming pattern:
+@code{za<@var{tile number}><@var{direction}><@var{qualifier}>
+<@var{slice number}>}.
+
+There are up to 16 tiles (0 ~ 15), the direction can be either @code{v}
+(vertical) or @code{h} (horizontal), the qualifiers can be @code{b} (byte),
+@code{h} (halfword), @code{s} (word), @code{d} (doubleword) and @code{q}
+(quadword) and there are up to 256 slices (0 ~ 255) depending on the value
+of @code{SVL}. The number of slices is the same as the value of @code{SVL}.
+
+The number of available tile slice pseudo-registers can be large. For a
+minimum @code{SVL} of 16 bytes, there are 5 (number of qualifiers) x
+2 (number of directions) x 16 (@code{SVL}) pseudo-registers. For the
+maximum @code{SVL} of 256 bytes, there are 5 x 2 x 256 pseudo-registers.
+
+When listing all the available registers, users will see the
+currently-available @code{za} pseudo-registers. Pseudo-registers that don't
+exist for a given @code{SVL} value will not be displayed.
+
+For more information on @acronym{SME} and its terminology, please refer to the
+@url{https://developer.arm.com/documentation/ddi0616/aa/,
+Arm Architecture Reference Manual Supplement}, The Scalable Matrix Extension
+(@acronym{SME}), for Armv9-A.
+
+Some features are still under development and rely on
+@url{https://github.com/ARM-software/acle/releases/latest, ACLE} and
+@url{https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst, ABI}
+definitions, so there are known limitations to the current @acronym{SME}
+support in @value{GDBN}.
+
+One such example is calling functions in the program being debugged by
+@value{GDBN}. Such calls are not @acronym{SME}-aware and thus don't take into
+account the @code{svcr} pseudo-register bits nor the @code{za} register
+contents. @xref{Calling}
+
+The @url{https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#the-za-lazy-saving-scheme,
+lazy saving scheme} involving the @code{tpidr2} register is not yet supported
+by @value{GDBN}, though the @code{tpidr2} register is known and supported
+by @value{GDBN}.
+
+Lastly, an important limitation for @code{gdbserver} is its inability to
+communicate @code{SVL} changes to @value{GDBN}. This means @code{gdbserver},
+even though it is capable of adjusting its internal caches to reflect a change
+in the value of @code{SVL} mid-execution, will operate with a potentially
+different @code{SVL} value compared to @value{GDBN}. This can lead to
+@value{GDBN} showing incorrect values for the @code{za} register and
+incorrect values for SVE registers (when in streaming mode).
+
+This is the same limitation we have for the @acronym{SVE} registers, and there
+are plans to address this limitation going forward.
+
@subsubsection AArch64 Pointer Authentication.
@cindex AArch64 Pointer Authentication.
@anchor{AArch64 PAC}
@@ -48071,6 +48289,37 @@ This restriction may be lifted in the future.
Extra registers are allowed in this feature, but they will not affect
@value{GDBN}.
+@subsubsection AArch64 SME registers feature
+
+The @samp{org.gnu.gdb.aarch64.sme} feature is optional. If present,
+it should contain registers @samp{za}, @samp{svg} and @samp{svcr}.
+@xref{AArch64 SME}
+
+@itemize @minus
+
+@item
+@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
+bytes. @xref{SVL}
+
+@item
+@samp{svg} is a 64-bit register containing the value of @code{SVG}. @xref{SVG}.
+
+@item
+@samp{svcr} is a 64-bit status pseudo-register with two valid bits. Bit 0
+(@sc{sm}) shows whether the streaming @acronym{SVE} mode is enabled or disabled.
+Bit 1 (@sc{za}) shows whether the @code{za} register state is active (in use) or
+not.
+@xref{aarch64 sme svcr}
+
+The rest of the unused bits of the @samp{svcr} pseudo-register is undefined
+and reserved. Such bits should not be used and may be defined by future
+extensions of the architecture.
+
+@end itemize
+
+Extra registers are allowed in this feature, but they will not affect
+@value{GDBN}.
+
@node ARC Features
@subsection ARC Features
@cindex target descriptions, ARC Features
--
2.25.1
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v3 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-17 17:19 ` [PATCH,v3 " Luis Machado
@ 2023-04-22 9:21 ` Eli Zaretskii
2023-04-26 15:00 ` Luis Machado
0 siblings, 1 reply; 38+ messages in thread
From: Eli Zaretskii @ 2023-04-22 9:21 UTC (permalink / raw)
To: Luis Machado; +Cc: gdb-patches
> From: Luis Machado <luis.machado@arm.com>
> Date: Mon, 17 Apr 2023 18:19:45 +0100
>
> Provide documentation for the SME feature and other information that
> should be useful for users that need to debug a SME-capable target.
> ---
> gdb/NEWS | 11 ++
> gdb/doc/gdb.texinfo | 249 ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 260 insertions(+)
Thanks.
> diff --git a/gdb/NEWS b/gdb/NEWS
> index 54b5da21245..e3ce7d7e881 100644
> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -3,6 +3,17 @@
>
> *** Changes since GDB 13
>
> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
> + length register SVG (streaming vector granule). GDB also supports tracking
> + ZA state across signal frames.
> +
> + Some features are still under development or are dependent on ABI specs that
> + are still in alpha stage. For example, manual function calls with ZA state
> + don't have any special handling, and tracking of SVG changes based on
> + DWARF information is still not implemented, but there are plans to do so in
> + the future.
> +
> * The AArch64 'org.gnu.gdb.aarch64.pauth' Pointer Authentication feature string
> has been deprecated in favor of the 'org.gnu.gdb.aarch64.pauth_v2' feature
> string.
This part is OK.
> +For SVE, the following definitions are used throughout @value{GDBN}'s source
> +code and in this document:
> +
> +@itemize
> +
> +@item
> +@anchor{VL}
> +@cindex VL
> +@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
> +register.
> +
> +@item
> +@anchor{VQ}
> +@cindex VQ
> +@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
> +
> +@item
> +@anchor{VG}
> +@cindex VG
> +@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
I thought we agreed to use @var{vl}, @var{vq}, etc., instead of
@code{VL} etc.? These are meta-syntactic parameters, they stand for
something else, not literally for themselves, so @var is more
appropriate.
Also, you place @cindex between @item and the text of the @item -- did
you verify that typing "i VQ" in an Info reader goes to the beginning
of the item's line? I think @cindex should be before @item.
> +Similarly to SVE, where the size of each @code{Z} register is directly related
> +to the vector length (@code{VL} for short), the @acronym{SME} @code{ZA} matrix
> +register's size is directly related to the streaming vector length
Elsewhere you use @code{za}, lower-case, for the register. Please be
consistent in the capitalization of the register names.
> +(@code{SVL} for short). @xref{VL} @xref{SVL}
^^
Two spaces there.
> +@item
> +@anchor{SVL}
> +@cindex SVL
> +@code{SVL}: The streaming vector length, in bytes. It defines the size of each
> +dimension of the 2-dimensional square @code{ZA} matrix. The total size of
> +@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
> +
> +When streaming mode is enabled, it defines the size of the @acronym{SVE}
> +registers as well.
> +
> +@item
> +@anchor{SVQ}
> +@cindex SVQ
> +@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
> +
> +@item
> +@anchor{SVG}
> +@cindex SVG
> +@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
Likewise here: I thought we agreed on using @var{svl} etc., not
@code{SVL}.
> +The @code{za} register is a 2-dimensional square @code{@var{SVL}x@var{SVL}}
And here you actually use @var (which is correct), but with an
upper-case argument, which is sub-optimal. The argument of @var
should be in lower-case.
> +@item
> +@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
^^^^^^^^^^^^^^^^^^^^^^^
This should use @var, not @code. Also, I'd remove the whitespace
around "x".
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v3 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-22 9:21 ` Eli Zaretskii
@ 2023-04-26 15:00 ` Luis Machado
2023-04-26 16:11 ` Eli Zaretskii
0 siblings, 1 reply; 38+ messages in thread
From: Luis Machado @ 2023-04-26 15:00 UTC (permalink / raw)
To: Eli Zaretskii; +Cc: gdb-patches
On 4/22/23 10:21, Eli Zaretskii wrote:
>> From: Luis Machado <luis.machado@arm.com>
>> Date: Mon, 17 Apr 2023 18:19:45 +0100
>>
>> Provide documentation for the SME feature and other information that
>> should be useful for users that need to debug a SME-capable target.
>> ---
>> gdb/NEWS | 11 ++
>> gdb/doc/gdb.texinfo | 249 ++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 260 insertions(+)
>
> Thanks.
>
>> diff --git a/gdb/NEWS b/gdb/NEWS
>> index 54b5da21245..e3ce7d7e881 100644
>> --- a/gdb/NEWS
>> +++ b/gdb/NEWS
>> @@ -3,6 +3,17 @@
>>
>> *** Changes since GDB 13
>>
>> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
>> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
>> + length register SVG (streaming vector granule). GDB also supports tracking
>> + ZA state across signal frames.
>> +
>> + Some features are still under development or are dependent on ABI specs that
>> + are still in alpha stage. For example, manual function calls with ZA state
>> + don't have any special handling, and tracking of SVG changes based on
>> + DWARF information is still not implemented, but there are plans to do so in
>> + the future.
>> +
>> * The AArch64 'org.gnu.gdb.aarch64.pauth' Pointer Authentication feature string
>> has been deprecated in favor of the 'org.gnu.gdb.aarch64.pauth_v2' feature
>> string.
>
> This part is OK.
>
>> +For SVE, the following definitions are used throughout @value{GDBN}'s source
>> +code and in this document:
>> +
>> +@itemize
>> +
>> +@item
>> +@anchor{VL}
>> +@cindex VL
>> +@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
>> +register.
>> +
>> +@item
>> +@anchor{VQ}
>> +@cindex VQ
>> +@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>> +
>> +@item
>> +@anchor{VG}
>> +@cindex VG
>> +@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>
> I thought we agreed to use @var{vl}, @var{vq}, etc., instead of
> @code{VL} etc.? These are meta-syntactic parameters, they stand for
> something else, not literally for themselves, so @var is more
> appropriate.
Ok. That wasn't completely clear to me. I've made the change now.
>
> Also, you place @cindex between @item and the text of the @item -- did
> you verify that typing "i VQ" in an Info reader goes to the beginning
> of the item's line? I think @cindex should be before @item.
You're right. Fixed and verified now.
>
>> +Similarly to SVE, where the size of each @code{Z} register is directly related
>> +to the vector length (@code{VL} for short), the @acronym{SME} @code{ZA} matrix
>> +register's size is directly related to the streaming vector length
>
> Elsewhere you use @code{za}, lower-case, for the register. Please be
> consistent in the capitalization of the register names.
>
All the uses of za should now be lower-case.
>> +(@code{SVL} for short). @xref{VL} @xref{SVL}
> ^^
> Two spaces there.
>
Fixed.
>> +@item
>> +@anchor{SVL}
>> +@cindex SVL
>> +@code{SVL}: The streaming vector length, in bytes. It defines the size of each
>> +dimension of the 2-dimensional square @code{ZA} matrix. The total size of
>> +@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
>> +
>> +When streaming mode is enabled, it defines the size of the @acronym{SVE}
>> +registers as well.
>> +
>> +@item
>> +@anchor{SVQ}
>> +@cindex SVQ
>> +@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>> +
>> +@item
>> +@anchor{SVG}
>> +@cindex SVG
>> +@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>
> Likewise here: I thought we agreed on using @var{svl} etc., not
> @code{SVL}.
>
Fixed now.
>> +The @code{za} register is a 2-dimensional square @code{@var{SVL}x@var{SVL}}
>
> And here you actually use @var (which is correct), but with an
> upper-case argument, which is sub-optimal. The argument of @var
> should be in lower-case.
>
Fixed.
>> +@item
>> +@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
> ^^^^^^^^^^^^^^^^^^^^^^^
> This should use @var, not @code. Also, I'd remove the whitespace
> around "x".
Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
block of characters like svlxsvl.
Using @math{x} doesn't look too nice. Suggestions?
>
> Reviewed-By: Eli Zaretskii <eliz@gnu.org>
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v3 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-26 15:00 ` Luis Machado
@ 2023-04-26 16:11 ` Eli Zaretskii
2023-04-27 8:35 ` Luis Machado
0 siblings, 1 reply; 38+ messages in thread
From: Eli Zaretskii @ 2023-04-26 16:11 UTC (permalink / raw)
To: Luis Machado; +Cc: gdb-patches
> Date: Wed, 26 Apr 2023 16:00:44 +0100
> Cc: gdb-patches@sourceware.org
> From: Luis Machado <luis.machado@arm.com>
>
> >> +@item
> >> +@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
> > ^^^^^^^^^^^^^^^^^^^^^^^
> > This should use @var, not @code. Also, I'd remove the whitespace
> > around "x".
>
> Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
> block of characters like svlxsvl.
That doesn't seem possible, since @var produces a different typeface:
slanted in the printed version and CAPS in the Info versions. Where
did you see svlxsvl?
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v3 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-26 16:11 ` Eli Zaretskii
@ 2023-04-27 8:35 ` Luis Machado
2023-04-27 9:10 ` Eli Zaretskii
0 siblings, 1 reply; 38+ messages in thread
From: Luis Machado @ 2023-04-27 8:35 UTC (permalink / raw)
To: Eli Zaretskii; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 1291 bytes --]
On 4/26/23 17:10, Eli Zaretskii wrote:
>> Date: Wed, 26 Apr 2023 16:00:44 +0100
>> Cc: gdb-patches@sourceware.org
>> From: Luis Machado <luis.machado@arm.com>
>>
>>>> +@item
>>>> +@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
>>> ^^^^^^^^^^^^^^^^^^^^^^^
>>> This should use @var, not @code. Also, I'd remove the whitespace
>>> around "x".
>>
>> Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
>> block of characters like svlxsvl.
>
> That doesn't seem possible, since @var produces a different typeface:
> slanted in the printed version and CAPS in the Info versions. Where
> did you see svlxsvl?
In the PDF. I mean, it is slanted with the use of @var{}, but not that noticeable.
See the attached pdf. I also attached the info file.
I noticed the info file capitalizes @var{}, which might not be ideal?
For instance, look at this paragraph (from the pdf):
"The za register is a 2-dimensional square svlxsvl matrix of bytes. To simplify the rep-
resentation and access to the za register in gdb, it is defined as a vector of svlxsvl bytes."
The first "svlxsvl" is using @var{}x@var{}. The second one is wrapped in @code{}, so @code{@var{}x@var{}}.
[-- Attachment #2: gdb.pdf --]
[-- Type: application/pdf, Size: 3013820 bytes --]
[-- Attachment #3: gdb.info --]
[-- Type: application/x-info, Size: 2706947 bytes --]
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v3 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-27 8:35 ` Luis Machado
@ 2023-04-27 9:10 ` Eli Zaretskii
2023-04-27 9:12 ` Luis Machado
0 siblings, 1 reply; 38+ messages in thread
From: Eli Zaretskii @ 2023-04-27 9:10 UTC (permalink / raw)
To: Luis Machado; +Cc: gdb-patches
> Date: Thu, 27 Apr 2023 09:35:15 +0100
> Cc: gdb-patches@sourceware.org
> From: Luis Machado <luis.machado@arm.com>
>
> >>> This should use @var, not @code. Also, I'd remove the whitespace
> >>> around "x".
> >>
> >> Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
> >> block of characters like svlxsvl.
> >
> > That doesn't seem possible, since @var produces a different typeface:
> > slanted in the printed version and CAPS in the Info versions. Where
> > did you see svlxsvl?
>
> In the PDF. I mean, it is slanted with the use of @var{}, but not that noticeable.
>
> See the attached pdf. I also attached the info file.
Then maybe use "@var{svl} by @var{svl}"?
> I noticed the info file capitalizes @var{}, which might not be ideal?
That cannot be helped. It isn't ideal, indeed, but given that Info
manuals must be displayed on plain-text terminals, there's not a lot
Texinfo can play with.
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH,v3 17/17] [gdb/docs] sme: Document SME registers and features
2023-04-27 9:10 ` Eli Zaretskii
@ 2023-04-27 9:12 ` Luis Machado
0 siblings, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-27 9:12 UTC (permalink / raw)
To: Eli Zaretskii; +Cc: gdb-patches
On 4/27/23 10:10, Eli Zaretskii wrote:
>> Date: Thu, 27 Apr 2023 09:35:15 +0100
>> Cc: gdb-patches@sourceware.org
>> From: Luis Machado <luis.machado@arm.com>
>>
>>>>> This should use @var, not @code. Also, I'd remove the whitespace
>>>>> around "x".
>>>>
>>>> Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
>>>> block of characters like svlxsvl.
>>>
>>> That doesn't seem possible, since @var produces a different typeface:
>>> slanted in the printed version and CAPS in the Info versions. Where
>>> did you see svlxsvl?
>>
>> In the PDF. I mean, it is slanted with the use of @var{}, but not that noticeable.
>>
>> See the attached pdf. I also attached the info file.
>
> Then maybe use "@var{svl} by @var{svl}"?
>
I'll do that then.
>> I noticed the info file capitalizes @var{}, which might not be ideal?
>
> That cannot be helped. It isn't ideal, indeed, but given that Info
> manuals must be displayed on plain-text terminals, there's not a lot
> Texinfo can play with.
Fair enough.
Thanks for the review.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux.
2023-04-11 4:26 [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
` (16 preceding siblings ...)
2023-04-11 4:26 ` [PATCH 17/17] [gdb/docs] sme: Document SME registers and features Luis Machado
@ 2023-04-11 15:50 ` John Baldwin
2023-04-12 8:47 ` Willgerodt, Felix
2023-04-12 9:12 ` Luis Machado
17 siblings, 2 replies; 38+ messages in thread
From: John Baldwin @ 2023-04-11 15:50 UTC (permalink / raw)
To: Luis Machado, gdb-patches; +Cc: Willgerodt, Felix
On 4/10/23 9:26 PM, Luis Machado via Gdb-patches wrote:
> The following series enables SME 1 (Scalable Matrix Extension) support for
> AArch64 gdb and gdbserver.
>
> SME expands on SVE by having a variable-sized matrix (ZA) of dimensions
> SVL x SVL bytes.
>
> The first few patches and some intermediate ones refactor the code and fix
> issues prior to enabling SME support, and thus could go in independently.
>
> I've kept them in the series as they are closely/logically related.
I briefly glanced at a few bits of the aarch64-specific parts I'm familiar
with and they all look fine to me.
One note is that I think the AMX patches from Intel (which deal with a
similar "tile area" split into variable-sized subregisters IIUC) ran into
some issues with wanting to update the tdesc to deal with the differing
subregisters since the layout of those can change at runtime. I'm not
sure if that applies to SME in the same way and if any of the issues
Felix ran into might apply to SME as well (and thus if there are common
solutions?) (I've cc'd Felix FYI)
> Ezra Sitorus (1):
> [binutils/aarch64] sme: Core file support
>
> Luis Machado (16):
> [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux
> [gdb/aarch64] refactor: Rename SVE-specific files
> [gdb/gdbserver] refactor: Simplify SVE interface to read/write
> registers
> [gdb/aarch64] sve: Fix return command when using V registers in a
> SVE-enabled target
> [gdb/aarch64] sme: Enable SME registers and pseudo-registers
> [gdbserver/aarch64] refactor: Adjust expedited registers dynamically
> [gdbserver/aarch64] sme: Add support for SME
> [gdb/aarch64] sve: Fix signal frame z/v register restore
> [gdb/aarch64] sme: Signal frame support
> [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes
> [gdb/aarch64] sme: Support TPIDR2 signal frame context
> [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping
> register state to core files
> [gdb/generic] corefile/bug: Fixup (gcore) core file target description
> reading order
> [gdb/aarch64] sme: Core file support for Linux
> [gdb/testsuite] sme: Add SVE/SME testcases
> [gdb/docs] sme: Document SME registers and features
>
> bfd/elf-bfd.h | 4 +
> bfd/elf.c | 58 +
> gdb/Makefile.in | 6 +-
> gdb/NEWS | 11 +
> gdb/aarch64-linux-nat.c | 179 ++--
> gdb/aarch64-linux-tdep.c | 951 ++++++++++++++---
> gdb/aarch64-tdep.c | 724 ++++++++++++-
> gdb/aarch64-tdep.h | 47 +
> gdb/arch/aarch64-scalable-linux.c | 55 +
> gdb/arch/aarch64-scalable-linux.h | 53 +
> gdb/arch/aarch64.c | 5 +
> gdb/arch/aarch64.h | 57 +-
> gdb/configure.nat | 2 +-
> gdb/configure.tgt | 1 +
> gdb/corelow.c | 24 +-
> gdb/doc/gdb.texinfo | 68 ++
> gdb/features/aarch64-sme.c | 63 ++
> gdb/linux-tdep.c | 18 +-
> gdb/nat/aarch64-scalable-linux-ptrace.c | 993 ++++++++++++++++++
> gdb/nat/aarch64-scalable-linux-ptrace.h | 156 +++
> ....h => aarch64-scalable-linux-sigcontext.h} | 73 +-
> gdb/nat/aarch64-sve-linux-ptrace.c | 392 -------
> gdb/nat/aarch64-sve-linux-ptrace.h | 72 --
> gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp | 18 +
> gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp | 18 +
> gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp | 18 +
> gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp | 18 +
> gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp | 18 +
> gdb/testsuite/gdb.arch/aarch64-sme-core.c | 361 +++++++
> .../gdb.arch/aarch64-sme-core.exp.tcl | 167 +++
> .../gdb.arch/aarch64-sme-regs-available-0.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-available-1.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-available-2.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-available-3.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-available-4.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-available.c | 184 ++++
> .../aarch64-sme-regs-available.exp.tcl | 194 ++++
> .../gdb.arch/aarch64-sme-regs-sigframe-0.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-sigframe-1.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-sigframe-2.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-sigframe-3.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-sigframe-4.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-sigframe.c | 368 +++++++
> .../aarch64-sme-regs-sigframe.exp.tcl | 156 +++
> .../aarch64-sme-regs-unavailable-0.exp | 18 +
> .../aarch64-sme-regs-unavailable-1.exp | 18 +
> .../aarch64-sme-regs-unavailable-2.exp | 18 +
> .../aarch64-sme-regs-unavailable-3.exp | 18 +
> .../aarch64-sme-regs-unavailable-4.exp | 18 +
> .../gdb.arch/aarch64-sme-regs-unavailable.c | 154 +++
> .../aarch64-sme-regs-unavailable.exp.tcl | 162 +++
> gdb/testsuite/gdb.arch/aarch64-sme-sanity.c | 249 +++++
> gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp | 72 ++
> gdb/testsuite/lib/aarch64.exp | 372 +++++++
> gdb/testsuite/lib/gdb.exp | 63 ++
> gdb/tramp-frame.c | 1 +
> gdb/tramp-frame.h | 12 +
> gdbserver/Makefile.in | 2 +-
> gdbserver/configure.srv | 3 +-
> gdbserver/linux-aarch64-low.cc | 100 +-
> gdbserver/linux-aarch64-tdesc.cc | 28 +-
> gdbserver/server.h | 2 +-
> 62 files changed, 6328 insertions(+), 694 deletions(-)
> create mode 100644 gdb/arch/aarch64-scalable-linux.c
> create mode 100644 gdb/arch/aarch64-scalable-linux.h
> create mode 100644 gdb/features/aarch64-sme.c
> create mode 100644 gdb/nat/aarch64-scalable-linux-ptrace.c
> create mode 100644 gdb/nat/aarch64-scalable-linux-ptrace.h
> rename gdb/nat/{aarch64-sve-linux-sigcontext.h => aarch64-scalable-linux-sigcontext.h} (78%)
> delete mode 100644 gdb/nat/aarch64-sve-linux-ptrace.c
> delete mode 100644 gdb/nat/aarch64-sve-linux-ptrace.h
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core.c
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-0.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-1.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-2.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-3.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-4.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available.c
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-0.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-1.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-2.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-3.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-4.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-0.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-1.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-2.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-3.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-4.exp
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.c
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-sanity.c
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp
> create mode 100644 gdb/testsuite/lib/aarch64.exp
>
--
John Baldwin
^ permalink raw reply [flat|nested] 38+ messages in thread* RE: [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux.
2023-04-11 15:50 ` [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux John Baldwin
@ 2023-04-12 8:47 ` Willgerodt, Felix
2023-04-12 9:12 ` Luis Machado
1 sibling, 0 replies; 38+ messages in thread
From: Willgerodt, Felix @ 2023-04-12 8:47 UTC (permalink / raw)
To: John Baldwin, Luis Machado, gdb-patches
> -----Original Message-----
> From: John Baldwin <jhb@FreeBSD.org>
> Sent: Dienstag, 11. April 2023 17:51
> To: Luis Machado <luis.machado@arm.com>; gdb-patches@sourceware.org
> Cc: Willgerodt, Felix <felix.willgerodt@intel.com>
> Subject: Re: [PATCH 00/17] SME support for AArch64 gdb/gdbserver on
> Linux.
>
> On 4/10/23 9:26 PM, Luis Machado via Gdb-patches wrote:
> > The following series enables SME 1 (Scalable Matrix Extension) support for
> > AArch64 gdb and gdbserver.
> >
> > SME expands on SVE by having a variable-sized matrix (ZA) of dimensions
> > SVL x SVL bytes.
> >
> > The first few patches and some intermediate ones refactor the code and
> fix
> > issues prior to enabling SME support, and thus could go in independently.
> >
> > I've kept them in the series as they are closely/logically related.
>
> I briefly glanced at a few bits of the aarch64-specific parts I'm familiar
> with and they all look fine to me.
>
> One note is that I think the AMX patches from Intel (which deal with a
> similar "tile area" split into variable-sized subregisters IIUC) ran into
> some issues with wanting to update the tdesc to deal with the differing
> subregisters since the layout of those can change at runtime. I'm not
> sure if that applies to SME in the same way and if any of the issues
> Felix ran into might apply to SME as well (and thus if there are common
> solutions?) (I've cc'd Felix FYI)
Hi John, Luis,
I didn't read the SME series in full detail and probably won't have the time to
do that for a while, sorry. I can only repeat my AMX problems.
My problem was related to the fact that I tried to make the AMX register
pseudo registers to do the dynamic resizing.
This doesn't work well with the regcache.
I am currently waiting on this series to land to continue:
https://sourceware.org/pipermail/gdb-patches/2023-January/196353.html
I am planning to do the tdesc update dynamically instead, forgoing
pseudo registers all together. But I haven't started implementing that.
We had an internal version that tried this, but in the end we scrapped that
because gdbserver doesn't support it (yet).
I think my main problem with pseudo registers is that regcache is initialized
with a certain size and types of registers. Even the pseudo registers.
For AMX we have 8 kB of register state. That is currently divided into 8 registers
of the same dimensions.
But that is actually configurable, and it could be that future platforms add a
configuration ("palette") that divides it into 4 registers of dimension "x * x". Or
another palette that divides this into 4 registers of dimension "y * z". Or another
palette that divides it into 16 registers. Switching configurations can be done
at runtime.
I was initially planning to just take the biggest dimension and the
biggest amount of names, and keep that up-to-date.
The actual problem I had in the end was discussed here:
https://sourceware.org/pipermail/gdb-patches/2022-August/191259.html
But the solution I proposed there isn't a good one.
It works by accident for now. It only touches the type, but not the actual
memory that is already reserved for the reg, which can become a problem.
I am not familiar with SME. I see that the SME series also added pseudo
registers and doesn't touch regcache.c. But I didn't look at the code in
detail. I am not familiar with the aarch64 target code. I don't know if Luis
found a way around the same problem or if it just doesn’t exist for SME.
Or if my AMX code just wasn't smart enough or done the right way.
Regards,
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de <http://www.intel.de>
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux.
2023-04-11 15:50 ` [PATCH 00/17] SME support for AArch64 gdb/gdbserver on Linux John Baldwin
2023-04-12 8:47 ` Willgerodt, Felix
@ 2023-04-12 9:12 ` Luis Machado
1 sibling, 0 replies; 38+ messages in thread
From: Luis Machado @ 2023-04-12 9:12 UTC (permalink / raw)
To: John Baldwin, gdb-patches; +Cc: Willgerodt, Felix
Hi John,
On 4/11/23 16:50, John Baldwin wrote:
> On 4/10/23 9:26 PM, Luis Machado via Gdb-patches wrote:
>> The following series enables SME 1 (Scalable Matrix Extension) support for
>> AArch64 gdb and gdbserver.
>>
>> SME expands on SVE by having a variable-sized matrix (ZA) of dimensions
>> SVL x SVL bytes.
>>
>> The first few patches and some intermediate ones refactor the code and fix
>> issues prior to enabling SME support, and thus could go in independently.
>>
>> I've kept them in the series as they are closely/logically related.
>
> I briefly glanced at a few bits of the aarch64-specific parts I'm familiar
> with and they all look fine to me.
Thanks for checking it.
>
> One note is that I think the AMX patches from Intel (which deal with a
> similar "tile area" split into variable-sized subregisters IIUC) ran into
> some issues with wanting to update the tdesc to deal with the differing
> subregisters since the layout of those can change at runtime. I'm not
> sure if that applies to SME in the same way and if any of the issues
> Felix ran into might apply to SME as well (and thus if there are common
> solutions?) (I've cc'd Felix FYI)
I did read Felix's reply, but I'm replying to this thread instead.
I'm not entirely familiar with the AMX spec, though from Felix's descriptions it sounds like there are similarities.
The limitation of gdbserver not being able to properly communicate changes to the vector length to GDB is a known one
for AArch64, as that has been the case since SVE support was put together. I know Thiago is working on it, and SME support
should be fairly simple to adjust to match that design. So I don't see that as a blocker.
For SME we have a new independent vector length (streaming vector length, SVL), so we handle that in the same way as
we handle SVE's vector length (VL). The added complexity comes from the fact we have a new mode called streaming mode.
Whenever that streaming mode is active, then the SVE vectors will use SVL rather than VL for their sizes.
With that said, the new matrix register (ZA) has quite a few subregisters (tiles and tile slices), which I modelled
as pseudo-registers. And yes, they change sizes based on SVL changes.
I addressed that situation by having a separate gdbarch for each VL/SVL set. That means each pseudo-register has its
type cached in the proper gdbarch, so we need to be careful to use the right gdbarch.
I can see there are a few areas of gdb where the code is not totally aware that we can have multiple tdesc's and
gdbarches.
One such example is the gdb core file target XML dump note. That only dumps the process-wide tdesc, but for AArch64
we really need to dump a tdesc for each tdesc.
There might be some corner cases here and there. While implementing SME support I did find some issues that I attempted
to address. For example, the aarch64-linux-specific signal return code having to find out the proper gdbarch as opposed
to just reusing the next frame's gdbarch, which is potentially wrong for SVE/SME.
>
>> Ezra Sitorus (1):
>> [binutils/aarch64] sme: Core file support
>>
>> Luis Machado (16):
>> [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux
>> [gdb/aarch64] refactor: Rename SVE-specific files
>> [gdb/gdbserver] refactor: Simplify SVE interface to read/write
>> registers
>> [gdb/aarch64] sve: Fix return command when using V registers in a
>> SVE-enabled target
>> [gdb/aarch64] sme: Enable SME registers and pseudo-registers
>> [gdbserver/aarch64] refactor: Adjust expedited registers dynamically
>> [gdbserver/aarch64] sme: Add support for SME
>> [gdb/aarch64] sve: Fix signal frame z/v register restore
>> [gdb/aarch64] sme: Signal frame support
>> [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes
>> [gdb/aarch64] sme: Support TPIDR2 signal frame context
>> [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping
>> register state to core files
>> [gdb/generic] corefile/bug: Fixup (gcore) core file target description
>> reading order
>> [gdb/aarch64] sme: Core file support for Linux
>> [gdb/testsuite] sme: Add SVE/SME testcases
>> [gdb/docs] sme: Document SME registers and features
>>
>> bfd/elf-bfd.h | 4 +
>> bfd/elf.c | 58 +
>> gdb/Makefile.in | 6 +-
>> gdb/NEWS | 11 +
>> gdb/aarch64-linux-nat.c | 179 ++--
>> gdb/aarch64-linux-tdep.c | 951 ++++++++++++++---
>> gdb/aarch64-tdep.c | 724 ++++++++++++-
>> gdb/aarch64-tdep.h | 47 +
>> gdb/arch/aarch64-scalable-linux.c | 55 +
>> gdb/arch/aarch64-scalable-linux.h | 53 +
>> gdb/arch/aarch64.c | 5 +
>> gdb/arch/aarch64.h | 57 +-
>> gdb/configure.nat | 2 +-
>> gdb/configure.tgt | 1 +
>> gdb/corelow.c | 24 +-
>> gdb/doc/gdb.texinfo | 68 ++
>> gdb/features/aarch64-sme.c | 63 ++
>> gdb/linux-tdep.c | 18 +-
>> gdb/nat/aarch64-scalable-linux-ptrace.c | 993 ++++++++++++++++++
>> gdb/nat/aarch64-scalable-linux-ptrace.h | 156 +++
>> ....h => aarch64-scalable-linux-sigcontext.h} | 73 +-
>> gdb/nat/aarch64-sve-linux-ptrace.c | 392 -------
>> gdb/nat/aarch64-sve-linux-ptrace.h | 72 --
>> gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp | 18 +
>> gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp | 18 +
>> gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp | 18 +
>> gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp | 18 +
>> gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp | 18 +
>> gdb/testsuite/gdb.arch/aarch64-sme-core.c | 361 +++++++
>> .../gdb.arch/aarch64-sme-core.exp.tcl | 167 +++
>> .../gdb.arch/aarch64-sme-regs-available-0.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-available-1.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-available-2.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-available-3.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-available-4.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-available.c | 184 ++++
>> .../aarch64-sme-regs-available.exp.tcl | 194 ++++
>> .../gdb.arch/aarch64-sme-regs-sigframe-0.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-sigframe-1.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-sigframe-2.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-sigframe-3.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-sigframe-4.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-sigframe.c | 368 +++++++
>> .../aarch64-sme-regs-sigframe.exp.tcl | 156 +++
>> .../aarch64-sme-regs-unavailable-0.exp | 18 +
>> .../aarch64-sme-regs-unavailable-1.exp | 18 +
>> .../aarch64-sme-regs-unavailable-2.exp | 18 +
>> .../aarch64-sme-regs-unavailable-3.exp | 18 +
>> .../aarch64-sme-regs-unavailable-4.exp | 18 +
>> .../gdb.arch/aarch64-sme-regs-unavailable.c | 154 +++
>> .../aarch64-sme-regs-unavailable.exp.tcl | 162 +++
>> gdb/testsuite/gdb.arch/aarch64-sme-sanity.c | 249 +++++
>> gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp | 72 ++
>> gdb/testsuite/lib/aarch64.exp | 372 +++++++
>> gdb/testsuite/lib/gdb.exp | 63 ++
>> gdb/tramp-frame.c | 1 +
>> gdb/tramp-frame.h | 12 +
>> gdbserver/Makefile.in | 2 +-
>> gdbserver/configure.srv | 3 +-
>> gdbserver/linux-aarch64-low.cc | 100 +-
>> gdbserver/linux-aarch64-tdesc.cc | 28 +-
>> gdbserver/server.h | 2 +-
>> 62 files changed, 6328 insertions(+), 694 deletions(-)
>> create mode 100644 gdb/arch/aarch64-scalable-linux.c
>> create mode 100644 gdb/arch/aarch64-scalable-linux.h
>> create mode 100644 gdb/features/aarch64-sme.c
>> create mode 100644 gdb/nat/aarch64-scalable-linux-ptrace.c
>> create mode 100644 gdb/nat/aarch64-scalable-linux-ptrace.h
>> rename gdb/nat/{aarch64-sve-linux-sigcontext.h => aarch64-scalable-linux-sigcontext.h} (78%)
>> delete mode 100644 gdb/nat/aarch64-sve-linux-ptrace.c
>> delete mode 100644 gdb/nat/aarch64-sve-linux-ptrace.h
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-0.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-1.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-2.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-3.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core-4.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core.c
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-0.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-1.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-2.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-3.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available-4.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available.c
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-0.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-1.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-2.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-3.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe-4.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-0.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-1.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-2.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-3.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable-4.exp
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.c
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-sanity.c
>> create mode 100644 gdb/testsuite/gdb.arch/aarch64-sme-sanity.exp
>> create mode 100644 gdb/testsuite/lib/aarch64.exp
>>
>
^ permalink raw reply [flat|nested] 38+ messages in thread