From: Luis Machado <luis.machado@arm.com>
To: <gdb-patches@sourceware.org>
Subject: [PATCH v3 08/16] [gdb/aarch64] sve: Fix signal frame z/v register restore
Date: Fri, 30 Jun 2023 14:46:08 +0100 [thread overview]
Message-ID: <20230630134616.1238105-9-luis.machado@arm.com> (raw)
In-Reply-To: <20230630134616.1238105-1-luis.machado@arm.com>
While doing some SME work, I ran into the situation where the Z register
contents restored from a signal frame are incorrect if the signal frame
only contains fpsimd state and no sve state.
This happens because we only restore the v register values in that case,
and don't do anything for the z registers.
Fix this by initializing the z registers to 0 and then copying over the
overlapping part of the v registers to the z registers.
While at it, refactor the code a bit to simplify it and make it smaller.
Regression-tested on aarch64-linux Ubuntu 22.04/20.04.
---
gdb/aarch64-linux-tdep.c | 108 +++++++++++++++++++++++----------------
1 file changed, 63 insertions(+), 45 deletions(-)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index b183a3c9a38..eecf5bf13bd 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -196,14 +196,13 @@ read_aarch64_ctx (CORE_ADDR ctx_addr, enum bfd_endian byte_order,
/* Given CACHE, use the trad_frame* functions to restore the FPSIMD
registers from a signal frame.
- VREG_NUM is the number of the V register being restored, OFFSET is the
- address containing the register value, BYTE_ORDER is the endianness and
- HAS_SVE tells us if we have a valid SVE context or not. */
+ FPSIMD_CONTEXT is the address of the signal frame context containing FPSIMD
+ data. */
static void
-aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs,
- int vreg_num, CORE_ADDR offset,
- enum bfd_endian byte_order, bool has_sve)
+aarch64_linux_restore_vregs (struct gdbarch *gdbarch,
+ struct trad_frame_cache *cache,
+ CORE_ADDR fpsimd_context)
{
/* WARNING: SIMD state is laid out in memory in target-endian format.
@@ -215,11 +214,22 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs,
2 - If the target is little endian, then SIMD state is little endian, so
no byteswap is needed. */
- if (byte_order == BFD_ENDIAN_BIG)
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ int num_regs = gdbarch_num_regs (gdbarch);
+ aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
+
+ for (int i = 0; i < 32; i++)
{
+ CORE_ADDR offset = (fpsimd_context + AARCH64_FPSIMD_V0_OFFSET
+ + (i * AARCH64_FPSIMD_VREG_SIZE));
+
gdb_byte buf[V_REGISTER_SIZE];
- if (target_read_memory (offset, buf, V_REGISTER_SIZE) != 0)
+ /* Read the contents of the V register. */
+ if (target_read_memory (offset, buf, V_REGISTER_SIZE))
+ error (_("Failed to read fpsimd register from signal context."));
+
+ if (byte_order == BFD_ENDIAN_BIG)
{
size_t size = V_REGISTER_SIZE/2;
@@ -234,50 +244,67 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs,
store_unsigned_integer (buf + size , size, BFD_ENDIAN_LITTLE, u64);
/* Now we can store the correct bytes for the V register. */
- trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + vreg_num,
+ trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + i,
{buf, V_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_Q0_REGNUM
- + vreg_num, {buf, Q_REGISTER_SIZE});
+ + i, {buf, Q_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_D0_REGNUM
- + vreg_num, {buf, D_REGISTER_SIZE});
+ + i, {buf, D_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_S0_REGNUM
- + vreg_num, {buf, S_REGISTER_SIZE});
+ + i, {buf, S_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_H0_REGNUM
- + vreg_num, {buf, H_REGISTER_SIZE});
+ + i, {buf, H_REGISTER_SIZE});
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_B0_REGNUM
- + vreg_num, {buf, B_REGISTER_SIZE});
+ + i, {buf, B_REGISTER_SIZE});
- if (has_sve)
+ if (tdep->has_sve ())
trad_frame_set_reg_value_bytes (cache,
num_regs + AARCH64_SVE_V0_REGNUM
- + vreg_num, {buf, V_REGISTER_SIZE});
+ + i, {buf, V_REGISTER_SIZE});
}
- return;
- }
+ else
+ {
+ /* Little endian, just point at the address containing the register
+ value. */
+ trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + i, offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + i,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + i,
+ offset);
- /* Little endian, just point at the address containing the register
- value. */
- trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + vreg_num, offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + vreg_num,
- offset);
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + vreg_num,
- offset);
-
- if (has_sve)
- trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM
- + vreg_num, offset);
+ if (tdep->has_sve ())
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM
+ + i, offset);
+ }
+ if (tdep->has_sve ())
+ {
+ /* If SVE is supported for this target, zero out the Z
+ registers then copy the first 16 bytes of each of the V
+ registers to the associated Z register. Otherwise the Z
+ registers will contain uninitialized data. */
+ std::vector<gdb_byte> z_buffer (tdep->vq * 16);
+
+ /* We have already handled the endianness swap above, so we don't need
+ to worry about it here. */
+ memcpy (z_buffer.data (), buf, V_REGISTER_SIZE);
+ trad_frame_set_reg_value_bytes (cache,
+ AARCH64_SVE_Z0_REGNUM + i,
+ {z_buffer.data (),
+ z_buffer.size ()});
+ }
+ }
}
/* Implement the "init" method of struct tramp_frame. */
@@ -432,16 +459,7 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self,
/* If there was no SVE section then set up the V registers. */
if (sve_regs == 0)
- {
- for (int i = 0; i < 32; i++)
- {
- CORE_ADDR offset = (fpsimd + AARCH64_FPSIMD_V0_OFFSET
- + (i * AARCH64_FPSIMD_VREG_SIZE));
-
- aarch64_linux_restore_vreg (this_cache, num_regs, i, offset,
- byte_order, tdep->has_sve ());
- }
- }
+ aarch64_linux_restore_vregs (gdbarch, this_cache, fpsimd);
}
trad_frame_set_id (this_cache, frame_id_build (sp, func));
--
2.25.1
next prev parent reply other threads:[~2023-06-30 13:46 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 13:46 [PATCH v3 00/16] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-06-30 13:46 ` [PATCH v3 01/16] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux Luis Machado
2023-07-24 15:53 ` Thiago Jung Bauermann
2023-07-24 16:26 ` Luis Machado
2023-06-30 13:46 ` [PATCH v3 02/16] [gdb/aarch64] refactor: Rename SVE-specific files Luis Machado
2023-06-30 13:46 ` [PATCH v3 03/16] [gdb/gdbserver] refactor: Simplify SVE interface to read/write registers Luis Machado
2023-07-24 16:19 ` Thiago Jung Bauermann
2023-07-25 9:28 ` Luis Machado
2023-06-30 13:46 ` [PATCH v3 04/16] [gdb/aarch64] sve: Fix return command when using V registers in a SVE-enabled target Luis Machado
2023-06-30 13:46 ` [PATCH v3 05/16] [gdb/aarch64] sme: Enable SME registers and pseudo-registers Luis Machado
2023-07-26 20:01 ` Thiago Jung Bauermann
2023-07-27 9:01 ` Luis Machado
2023-07-28 1:19 ` Thiago Jung Bauermann
2023-06-30 13:46 ` [PATCH v3 06/16] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically Luis Machado
2023-06-30 13:46 ` [PATCH v3 07/16] [gdbserver/aarch64] sme: Add support for SME Luis Machado
2023-07-27 19:41 ` Thiago Jung Bauermann
2023-06-30 13:46 ` Luis Machado [this message]
2023-07-27 21:52 ` [PATCH v3 08/16] [gdb/aarch64] sve: Fix signal frame z/v register restore Thiago Jung Bauermann
2023-07-31 12:22 ` Luis Machado
2023-06-30 13:46 ` [PATCH v3 09/16] [gdb/aarch64] sme: Signal frame support Luis Machado
2023-07-27 22:25 ` Thiago Jung Bauermann
2023-07-31 12:23 ` Luis Machado
2023-06-30 13:46 ` [PATCH v3 10/16] [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes Luis Machado
2023-07-28 1:01 ` Thiago Jung Bauermann
2023-07-31 12:27 ` Luis Machado
2023-06-30 13:46 ` [PATCH v3 11/16] [gdb/aarch64] sme: Support TPIDR2 signal frame context Luis Machado
2023-06-30 13:46 ` [PATCH v3 12/16] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Luis Machado
2023-06-30 13:46 ` [PATCH v3 13/16] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order Luis Machado
2023-07-28 3:12 ` Thiago Jung Bauermann
2023-07-31 11:38 ` Luis Machado
2023-09-05 8:28 ` Luis Machado
2023-06-30 13:46 ` [PATCH v3 14/16] [gdb/aarch64] sme: Core file support for Linux Luis Machado
2023-08-03 0:18 ` Thiago Jung Bauermann
2023-08-03 11:37 ` Luis Machado
2023-08-04 20:45 ` Thiago Jung Bauermann
2023-06-30 13:46 ` [PATCH v3 15/16] [gdb/testsuite] sme: Add SVE/SME testcases Luis Machado
2023-08-04 0:59 ` Thiago Jung Bauermann
2023-08-11 15:42 ` Luis Machado
2023-08-12 0:42 ` Thiago Jung Bauermann
2023-06-30 13:46 ` [PATCH v3 16/16] [gdb/docs] sme: Document SME registers and features Luis Machado
2023-07-01 8:58 ` Eli Zaretskii
2023-07-03 9:52 ` Luis Machado
2023-07-03 12:03 ` Eli Zaretskii
2023-07-03 12:06 ` Luis Machado
2023-07-17 11:40 ` [PING][PATCH v3 00/16] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-07-24 8:15 ` Luis Machado
2023-08-04 21:24 ` [PATCH " Thiago Jung Bauermann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230630134616.1238105-9-luis.machado@arm.com \
--to=luis.machado@arm.com \
--cc=gdb-patches@sourceware.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).