From: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
To: Luis Machado <luis.machado@arm.com>
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH v2 2/6] [gdbserver/aarch64] sme2: Enable SME2 support in gdbserver
Date: Sat, 26 Aug 2023 22:18:16 -0300 [thread overview]
Message-ID: <87jzthl1uv.fsf@linaro.org> (raw)
In-Reply-To: <20230822112144.1513268-3-luis.machado@arm.com>
Luis Machado <luis.machado@arm.com> writes:
> This patch teaches gdbserver about the SME2 and the ZT0 register.
>
> Since most of the code used by gdbserver for SME2 is shared with gdb, this
> is a rather small patch that reuses most of the code put in place for native
> AArch64 Linux.
>
> Validated under Fast Models.
> ---
> gdbserver/linux-aarch64-low.cc | 63 ++++++++++++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
>
> diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc
> index 95688480c3d..783053e359b 100644
> --- a/gdbserver/linux-aarch64-low.cc
> +++ b/gdbserver/linux-aarch64-low.cc
> @@ -811,6 +811,52 @@ aarch64_za_regs_copy_from_regcache (struct regcache *regcache, void *buf)
> memcpy (buf, za_state.data (), za_state.size ());
> }
>
> +/* Wrapper for aarch64_zt_regs_copy_to_reg_buf, to help copying NT_ARM_ZT
> + state from the thread (BUF) to the register cache. */
> +
> +static void
> +aarch64_zt_regs_copy_to_regcache (struct regcache *regcache,
> + ATTRIBUTE_UNUSED const void *buf)
> +{
> + /* BUF is unused here since we collect the data straight from a ptrace
> + request, therefore bypassing gdbserver's own call to ptrace. */
> + int tid = lwpid_of (current_thread);
> +
> + gdb::optional<int> zt_regnum
> + = find_regno_no_throw (regcache->tdesc, "zt0");
> +
> + gdb_assert (zt_regnum.has_value ());
If this code is changed to use find_regno(), this gdb_assert() becomes
unnecessary.
> +
> + /* Update the register cache. aarch64_zt_regs_copy_to_reg_buf handles
> + fetching the NT_ARM_ZT state from thread TID. */
> + aarch64_zt_regs_copy_to_reg_buf (tid, regcache, *zt_regnum);
> +}
> +
> +/* Wrapper for aarch64_zt_regs_copy_from_reg_buf, to help copying NT_ARM_ZT
> + state from the register cache to the thread (BUF). */
> +
> +static void
> +aarch64_zt_regs_copy_from_regcache (struct regcache *regcache, void *buf)
> +{
> + int tid = lwpid_of (current_thread);
> +
> + gdb::optional<int> zt_regnum
> + = find_regno_no_throw (regcache->tdesc, "za");
> +
> + gdb_assert (zt_regnum.has_value ());
Same comment about find_regno().
> +
> + /* Update the thread NT_ARM_ZT state. aarch64_zt_regs_copy_from_reg_buf
> + handles writing the ZT state back to thread TID. */
> + aarch64_zt_regs_copy_from_reg_buf (tid, regcache, *zt_regnum);
> +
> + /* We need to return the expected data in BUF, so copy whatever the kernel
> + already has to BUF. */
> +
> + /* Obtain a dump of NT_ARM_ZT from ptrace. */
> + gdb::byte_vector zt_state = aarch64_fetch_zt_regset (tid);
> + memcpy (buf, zt_state.data (), zt_state.size ());
> +}
> +
> /* Array containing all the possible register sets for AArch64/Linux. During
> architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
> validity and enabled/disabled accordingly.
> @@ -838,6 +884,11 @@ static struct regset_info aarch64_regsets[] =
> 0, EXTENDED_REGS,
> aarch64_za_regs_copy_from_regcache, aarch64_za_regs_copy_to_regcache
> },
> + /* Scalable Matrix Extension 2 (SME2) ZT registers. */
> + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_ZT,
> + 0, EXTENDED_REGS,
> + aarch64_zt_regs_copy_from_regcache, aarch64_zt_regs_copy_to_regcache
> + },
> /* PAC registers. */
> { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
> 0, OPTIONAL_REGS,
> @@ -909,6 +960,10 @@ aarch64_adjust_register_sets (const struct aarch64_features &features)
> if (features.svq > 0)
> regset->size = ZA_PT_SIZE (features.svq);
> break;
> + case NT_ARM_ZT:
> + if (features.sme2)
> + regset->size = 64;
Suggest using AARCH64_SME2_ZT0_SIZE here.
> + break;
> default:
> gdb_assert_not_reached ("Unknown register set found.");
> }
> @@ -947,6 +1002,14 @@ aarch64_target::low_arch_setup ()
> if (linux_get_hwcap2 (pid, 8) & HWCAP2_SME)
> features.svq = aarch64_za_get_svq (tid);
>
> + /* Scalable Matrix Extension 2 feature check. */
> + CORE_ADDR hwcap2 = linux_get_hwcap2 (pid, 8);
> + if ((hwcap2 & HWCAP2_SME2) || (hwcap2 & HWCAP2_SME2P1))
> + {
> + /* Make sure ptrace supports NT_ARM_ZT. */
> + features.sme2 = supports_zt_registers (tid);
> + }
> +
> current_process ()->tdesc = aarch64_linux_read_description (features);
>
> /* Adjust the register sets we should use for this particular set of
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
--
Thiago
next prev parent reply other threads:[~2023-08-27 1:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-22 11:21 [PATCH v2 0/6] SME2 support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-08-22 11:21 ` [PATCH v2 1/6] [gdb/aarch64] sme2: Enable SME2 for AArch64 gdb " Luis Machado
2023-08-27 1:16 ` Thiago Jung Bauermann
2023-08-30 12:53 ` Luis Machado
2023-08-22 11:21 ` [PATCH v2 2/6] [gdbserver/aarch64] sme2: Enable SME2 support in gdbserver Luis Machado
2023-08-27 1:18 ` Thiago Jung Bauermann [this message]
2023-08-30 12:54 ` Luis Machado
2023-08-22 11:21 ` [PATCH v2 3/6] [gdb/aarch64] sme2: signal frame support Luis Machado
2023-08-27 1:19 ` Thiago Jung Bauermann
2023-08-22 11:21 ` [PATCH v2 4/6] [gdb/aarch64] sme2: Core file support for ZT register set Luis Machado
2023-08-27 1:21 ` Thiago Jung Bauermann
2023-08-30 12:56 ` Luis Machado
2023-08-22 11:21 ` [PATCH v2 5/6] [gdb/testsuite] sme2: Extend SME tests to include SME2 Luis Machado
2023-08-27 1:23 ` Thiago Jung Bauermann
2023-08-30 12:56 ` Luis Machado
2023-08-22 11:21 ` [PATCH v2 6/6] [gdb/docs] sme2: Document SME2 registers and features Luis Machado
2023-08-22 11:34 ` Eli Zaretskii
2023-08-22 11:45 ` Luis Machado
2023-08-27 1:27 ` Thiago Jung Bauermann
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