From: Tom Tromey <tom@tromey.com>
To: Branislav Brzak <Branislav.Brzak@Syrmia.com>
Cc: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>,
Dragoslav Sicarov <Dragoslav.Sicarov@Syrmia.com>,
Djordje Todorovic <Djordje.Todorovic@syrmia.com>
Subject: Re: [PATCH 0/1] riscv: Ensure LE instruction fetching
Date: Tue, 20 Jun 2023 08:08:32 -0600 [thread overview]
Message-ID: <87o7la2plr.fsf@tromey.com> (raw)
In-Reply-To: <AM6PR03MB49844DF747369343C05C7D0E985CA@AM6PR03MB4984.eurprd03.prod.outlook.com> (Branislav Brzak's message of "Tue, 20 Jun 2023 11:47:30 +0000")
> Currently riscv gdb code looks at arch byte order
> when fetching instructions. This works when the
> target is LE, but on BE arch it will byte swap the
> instruction, while the riscv spec defines all
> instructions are LE encoded regardless of
> system memory endianess.
Thank you for the patch.
> @@ -1812,7 +1812,7 @@ ULONGEST
> riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
> CORE_ADDR addr, int *len)
> {
> - enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
> + enum bfd_endian byte_order = BFD_ENDIAN_LITTLE;
The variable is only used once, so you might as well remove it entirely
and replace it BFD_ENDIAN_LITTLE in the call.
A comment saying that instructions are always little-endian might be nice.
Tom
next prev parent reply other threads:[~2023-06-20 14:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-20 11:46 Branislav Brzak
2023-06-20 11:47 ` Branislav Brzak
2023-06-20 14:08 ` Tom Tromey [this message]
2023-06-20 14:21 ` Branislav Brzak
2023-06-20 16:42 ` Tom Tromey
2023-06-21 9:11 ` Branislav Brzak
2023-07-06 16:13 ` Tom Tromey
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