Re: [PATCH 0/1] riscv: Ensure LE instruction fetching

[Branislav Brzak <Branislav.Brzak@Syrmia.com>]

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Hi Tom,

Here is the patch with the changes you specified.

Regards,
Branislav

________________________________
From: Tom Tromey <tom@tromey.com>
Sent: Tuesday, June 20, 2023 4:08 PM
To: Branislav Brzak <Branislav.Brzak@Syrmia.com>
Cc: gdb-patches@sourceware.org <gdb-patches@sourceware.org>; Dragoslav Sicarov <Dragoslav.Sicarov@Syrmia.com>; Djordje Todorovic <Djordje.Todorovic@syrmia.com>
Subject: Re: [PATCH 0/1] riscv: Ensure LE instruction fetching

> Currently riscv gdb code looks at arch byte order
> when fetching instructions. This works when the
> target is LE, but on BE arch it will byte swap the
> instruction, while the riscv spec defines all
> instructions are LE encoded regardless of
> system memory endianess.

Thank you for the patch.

> @@ -1812,7 +1812,7 @@ ULONGEST
>  riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
>                               CORE_ADDR addr, int *len)
>  {
> -  enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
> +  enum bfd_endian byte_order = BFD_ENDIAN_LITTLE;

The variable is only used once, so you might as well remove it entirely
and replace it BFD_ENDIAN_LITTLE in the call.

A comment saying that instructions are always little-endian might be nice.

Tom

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From 368fd34e4736192f053de73b0f24a288b43bfd29 Mon Sep 17 00:00:00 2001
From: Branislav Brzak <branislav.brzak@syrmia.com>
Date: Tue, 20 Jun 2023 16:19:55 +0200
Subject: [PATCH] * riscv-tdep.c (riscv_insn::fetch_instruction): Always fetch 
 instructions as LE

---
 gdb/riscv-tdep.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 500279e1ae9..ae18eb64452 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1812,7 +1812,6 @@ ULONGEST
 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
 			       CORE_ADDR addr, int *len)
 {
-  enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
   gdb_byte buf[RISCV_MAX_INSN_LEN];
   int instlen, status;
 
@@ -1833,7 +1832,8 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
 	memory_error (TARGET_XFER_E_IO, addr + 2);
     }
 
-  return extract_unsigned_integer (buf, instlen, byte_order);
+  /* RISC-V Specification states instructions are always little endian */
+  return extract_unsigned_integer (buf, instlen, BFD_ENDIAN_LITTLE);
 }
 
 /* Fetch from target memory an instruction at PC and decode it.  This can
-- 
2.34.1