Re: [PATCH 0/1] riscv: Ensure LE instruction fetching

[Branislav Brzak <Branislav.Brzak@Syrmia.com>]

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________________________________
From: Branislav Brzak
Sent: Tuesday, June 20, 2023 1:46 PM
To: gdb-patches@sourceware.org <gdb-patches@sourceware.org>
Cc: Dragoslav Sicarov <Dragoslav.Sicarov@Syrmia.com>; Djordje Todorovic <Djordje.Todorovic@syrmia.com>
Subject: [PATCH 0/1] riscv: Ensure LE instruction fetching

Currently riscv gdb code looks at arch byte order
when fetching instructions. This works when the
target is LE, but on BE arch it will byte swap the
instruction, while the riscv spec defines all
instructions are LE encoded regardless of
system memory endianess.

Branislav Brzak (1):
gdb/riscv: Ensure LE instruction fetching

gdb/riscv-tdep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)


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From 391716c3138697a0b8a1836c1ffdb44b1b6b9da4 Mon Sep 17 00:00:00 2001
From: Branislav Brzak <branislav.brzak@syrmia.com>
Date: Tue, 20 Jun 2023 13:20:40 +0200
Subject: [PATCH] * riscv-tdep.c (riscv_insn::fetch_instruction): Always fetch
 instructions as LE

---
 gdb/riscv-tdep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 500279e1ae9..b4f98089937 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1812,7 +1812,7 @@ ULONGEST
 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
 			       CORE_ADDR addr, int *len)
 {
-  enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
+  enum bfd_endian byte_order = BFD_ENDIAN_LITTLE;
   gdb_byte buf[RISCV_MAX_INSN_LEN];
   int instlen, status;
 
-- 
2.34.1