From: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
To: Torbjorn SVENSSON <torbjorn.svensson@foss.st.com>
Cc: tom@tromey.com, brobecker@adacore.com, gdb-patches@sourceware.org
Subject: Re: [PATCH v3] gdb/arm: Handle lazy FPU register stacking
Date: Fri, 30 Sep 2022 02:55:14 +0000 [thread overview]
Message-ID: <87pmfdh8q5.fsf@linaro.org> (raw)
In-Reply-To: <cebfa8a9-f511-4acd-010c-3fc4a01ec8b0@foss.st.com>
Hello,
Torbjorn SVENSSON <torbjorn.svensson@foss.st.com> writes:
> Hello,
>
> On 2022-09-27 22:08, Thiago Jung Bauermann wrote:
>> Hello,
>> Torbjörn SVENSSON via Gdb-patches <gdb-patches@sourceware.org> writes:
>>
>>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>>> index 2810232fcb8..43ce1a45782 100644
>>> --- a/gdb/arm-tdep.c
>>> +++ b/gdb/arm-tdep.c
>>> @@ -68,6 +68,7 @@
>>> #endif
>>> static bool arm_debug;
>>> +static bool force_fpu_regs_from_stack = false;
>> I'm a bit concerned about having a global variable to indicate what is
>> (IIUC) a per-CPU state. Does this logic work with multi-processor
>> inferiors?
>> Instead of using a global variable, can arm_m_exception_cache use
>> “this_frame->level > 0” to decide whether to get the FPU registers from
>> the stack?
>>
>
> I share your concern, but haven't found any better way to achieve the required condition.
>
> The content of FPCCR shall only be considered for the first extended exception frame on
> the stack. As there are likely other kinds of frames on the stack, the level would not be
> enough to decide if stack or registers should be used.
>
> Do you know a way that this state can be saved per inferior?
You could create a subclass of private_inferior containing
force_fpu_regs_from_stack and store it in inferior->priv.
An example is the remote_inferior class used by the remote target.
It would still be inadequate for multi-core inferiors — I don't know how
each CPU is modelled by GDB in that case. But if that scenario isn't
currently required then perhaps we can cross that bridge when we get
there...
> On the other hand, I got the impression that the cache is purged when the inferior is
> switched, but this assumption might be wrong.
switch_to_inferior_no_thread calls reinit_frame_cache so you're right
IIUC. Even then, I think it's conceptually more correct to store this
state in a private_inferior struct/class.
--
Thiago
next prev parent reply other threads:[~2022-09-30 2:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 19:09 Torbjörn SVENSSON
2022-09-27 20:08 ` Thiago Jung Bauermann
2022-09-27 20:27 ` Torbjorn SVENSSON
2022-09-30 2:55 ` Thiago Jung Bauermann [this message]
2022-09-30 13:20 ` Luis Machado
2022-09-30 15:13 ` Pedro Alves
2022-09-30 15:26 ` Torbjorn SVENSSON
2022-09-30 15:52 ` Pedro Alves
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