From: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
To: "Torbjörn SVENSSON" <torbjorn.svensson@foss.st.com>
Cc: tom@tromey.com, brobecker@adacore.com, gdb-patches@sourceware.org
Subject: Re: [PATCH v3] gdb/arm: Handle lazy FPU register stacking
Date: Tue, 27 Sep 2022 20:08:42 +0000 [thread overview]
Message-ID: <87pmfgeg1h.fsf@linaro.org> (raw)
In-Reply-To: <20220927190944.201748-1-torbjorn.svensson@foss.st.com>
Hello,
Torbjörn SVENSSON via Gdb-patches <gdb-patches@sourceware.org> writes:
> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
> index 2810232fcb8..43ce1a45782 100644
> --- a/gdb/arm-tdep.c
> +++ b/gdb/arm-tdep.c
> @@ -68,6 +68,7 @@
> #endif
>
> static bool arm_debug;
> +static bool force_fpu_regs_from_stack = false;
I'm a bit concerned about having a global variable to indicate what is
(IIUC) a per-CPU state. Does this logic work with multi-processor
inferiors?
Instead of using a global variable, can arm_m_exception_cache use
“this_frame->level > 0” to decide whether to get the FPU registers from
the stack?
--
Thiago
next prev parent reply other threads:[~2022-09-27 20:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 19:09 Torbjörn SVENSSON
2022-09-27 20:08 ` Thiago Jung Bauermann [this message]
2022-09-27 20:27 ` Torbjorn SVENSSON
2022-09-30 2:55 ` Thiago Jung Bauermann
2022-09-30 13:20 ` Luis Machado
2022-09-30 15:13 ` Pedro Alves
2022-09-30 15:26 ` Torbjorn SVENSSON
2022-09-30 15:52 ` Pedro Alves
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