Re: [PATCH v3] gdb/arm: Handle lazy FPU register stacking

[Luis Machado <luis.machado@arm.com>]

On 9/30/22 03:55, Thiago Jung Bauermann via Gdb-patches wrote:
> 
> Hello,
> 
> Torbjorn SVENSSON <torbjorn.svensson@foss.st.com> writes:
> 
>> Hello,
>>
>> On 2022-09-27 22:08, Thiago Jung Bauermann wrote:
>>> Hello,
>>> Torbjörn SVENSSON via Gdb-patches <gdb-patches@sourceware.org> writes:
>>>
>>>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>>>> index 2810232fcb8..43ce1a45782 100644
>>>> --- a/gdb/arm-tdep.c
>>>> +++ b/gdb/arm-tdep.c
>>>> @@ -68,6 +68,7 @@
>>>>    #endif
>>>>      static bool arm_debug;
>>>> +static bool force_fpu_regs_from_stack = false;
>>> I'm a bit concerned about having a global variable to indicate what is
>>> (IIUC) a per-CPU state. Does this logic work with multi-processor
>>> inferiors?
>>> Instead of using a global variable, can arm_m_exception_cache use
>>> “this_frame->level > 0” to decide whether to get the FPU registers from
>>> the stack?
>>>
>>
>> I share your concern, but haven't found any better way to achieve the required condition.
>>
>> The content of FPCCR shall only be considered for the first extended exception frame on
>> the stack. As there are likely other kinds of frames on the stack, the level would not be
>> enough to decide if stack or registers should be used.
>>
>> Do you know a way that this state can be saved per inferior?
> 
> You could create a subclass of private_inferior containing
> force_fpu_regs_from_stack and store it in inferior->priv.
> 
> An example is the remote_inferior class used by the remote target.
> 
> It would still be inadequate for multi-core inferiors — I don't know how
> each CPU is modelled by GDB in that case. But if that scenario isn't
> currently required then perhaps we can cross that bridge when we get
> there...
> 

I think the per-inferior data is a nice touch. For multi-core, those are usually exposed as
multiple threads by debugging stubs. Then again ...

>> On the other hand, I got the impression that the cache is purged when the inferior is
>> switched, but this assumption might be wrong.
> 
> switch_to_inferior_no_thread calls reinit_frame_cache so you're right
> IIUC. Even then, I think it's conceptually more correct to store this
> state in a private_inferior struct/class.
> 

... the frame cache gets purged when switching threads as well. So per-inferior
data should work nicely in this case.

Ideally we'd have some shared state between all the different unwinders, but that seems a bit
more complicated than it needs to be for the current needs.