[PATCH 1/2] RISC-V: Add reference to Zve32*

[PATCH 1/2] RISC-V: Add reference to Zve32*

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Before actual xlen handling, this commit fixes its description to allow xlen
less than 16 (but 4 or greater), to support vector subset extensions for
embedded environment ('Zve32*').
---
 gdb/arch/riscv.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 54610ed6c16b..d5ea1a55b214 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -47,9 +47,10 @@ struct riscv_gdbarch_features
   int flen = 0;
 
   /* The size of the v-registers in bytes.  The value 0 indicates a target
-     with no vector registers.  The minimum value for a standard compliant
-     target should be 16, but GDB doesn't currently mind, and will accept
-     any vector size.  */
+     with no vector registers.  The minimum value for a 'V'-extension compliant
+     target should be 16 and 4 for an embedded subset compliant target (with
+     'Zve32*' extension), but GDB doesn't currently mind, and will accept any
+     vector size.  */
   int vlen = 0;
 
   /* When true this target is RV32E.  */

base-commit: cca56b22a33bc279db358adca68f704329e5f0a3
-- 
2.41.0

[PATCH 2/2] RISC-V: Reflect actual range of vlen for hashing

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Before actual xlen handling, it fixes the hashing function based on the
actual valid range of xlen (xlen == 0 or 4 <= xlen <= 65536 / 8).

To reflect all those values, extra 2 bits should be hashed.
---
 gdb/arch/riscv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index d5ea1a55b214..e1965da69ebb 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -90,7 +90,7 @@ struct riscv_gdbarch_features
 		       | (has_fcsr_reg ? 1 : 0) << 13
 		       | (xlen & 0x1f) << 5
 		       | (flen & 0x1f) << 0
-		       | (vlen & 0xfff) << 14);
+		       | (vlen & 0x3fff) << 14);
     return val;
   }
 };
-- 
2.41.0

Re: [PATCH 1/2] RISC-V: Add reference to Zve32*

[Andrew Burgess]

Tsukasa OI <research_trasio@irq.a4lg.com> writes:

> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Before actual xlen handling, this commit fixes its description to allow xlen
> less than 16 (but 4 or greater), to support vector subset extensions for
> embedded environment ('Zve32*').

I think you mean vlen instead of xlen in this commit message.

With that fixed this commit (1/2) is:

Approved-By: Andrew Burgess <aburgess@redhat.com>

Thanks,
Andrew


> ---
>  gdb/arch/riscv.h | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
> index 54610ed6c16b..d5ea1a55b214 100644
> --- a/gdb/arch/riscv.h
> +++ b/gdb/arch/riscv.h
> @@ -47,9 +47,10 @@ struct riscv_gdbarch_features
>    int flen = 0;
>  
>    /* The size of the v-registers in bytes.  The value 0 indicates a target
> -     with no vector registers.  The minimum value for a standard compliant
> -     target should be 16, but GDB doesn't currently mind, and will accept
> -     any vector size.  */
> +     with no vector registers.  The minimum value for a 'V'-extension compliant
> +     target should be 16 and 4 for an embedded subset compliant target (with
> +     'Zve32*' extension), but GDB doesn't currently mind, and will accept any
> +     vector size.  */
>    int vlen = 0;
>  
>    /* When true this target is RV32E.  */
>
> base-commit: cca56b22a33bc279db358adca68f704329e5f0a3
> -- 
> 2.41.0

Re: [PATCH 2/2] RISC-V: Reflect actual range of vlen for hashing

[Andrew Burgess]

Tsukasa OI <research_trasio@irq.a4lg.com> writes:

> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Before actual xlen handling, it fixes the hashing function based on the
> actual valid range of xlen (xlen == 0 or 4 <= xlen <= 65536 / 8).

Please reword the commit message as:

  Before actual vlen handling, fix the riscv_gdbarch_features hashing
  function based on the actual valid range of vlen.  In bytes, vlen is 0,
  or 4 <= xlen <= 8192.

With that done, this commit (2/2) is:

Approved-By: Andrew Burgess <aburgess@redhat.com>

Thanks,
Andrew

> To reflect all those values, extra 2 bits should be hashed.
> ---
>  gdb/arch/riscv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
> index d5ea1a55b214..e1965da69ebb 100644
> --- a/gdb/arch/riscv.h
> +++ b/gdb/arch/riscv.h
> @@ -90,7 +90,7 @@ struct riscv_gdbarch_features
>  		       | (has_fcsr_reg ? 1 : 0) << 13
>  		       | (xlen & 0x1f) << 5
>  		       | (flen & 0x1f) << 0
> -		       | (vlen & 0xfff) << 14);
> +		       | (vlen & 0x3fff) << 14);
>      return val;
>    }
>  };
> -- 
> 2.41.0

Re: [PATCH 2/2] RISC-V: Reflect actual range of vlen for hashing

[Tsukasa OI]

On 2023/08/11 21:49, Andrew Burgess wrote:
> Tsukasa OI <research_trasio@irq.a4lg.com> writes:
> 
>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>
>> Before actual xlen handling, it fixes the hashing function based on the
>> actual valid range of xlen (xlen == 0 or 4 <= xlen <= 65536 / 8).
> 
> Please reword the commit message as:
> 
>   Before actual vlen handling, fix the riscv_gdbarch_features hashing
>   function based on the actual valid range of vlen.  In bytes, vlen is 0,
>   or 4 <= xlen <= 8192.
> 
> With that done, this commit (2/2) is:
> 
> Approved-By: Andrew Burgess <aburgess@redhat.com>
> 
> Thanks,
> Andrew

Thanks and committed!  Not only pointing out my simple mistakes, I
appreciate your proofreading.

Thanks,
Tsukasa

> 
>> To reflect all those values, extra 2 bits should be hashed.
>> ---
>>  gdb/arch/riscv.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
>> index d5ea1a55b214..e1965da69ebb 100644
>> --- a/gdb/arch/riscv.h
>> +++ b/gdb/arch/riscv.h
>> @@ -90,7 +90,7 @@ struct riscv_gdbarch_features
>>  		       | (has_fcsr_reg ? 1 : 0) << 13
>>  		       | (xlen & 0x1f) << 5
>>  		       | (flen & 0x1f) << 0
>> -		       | (vlen & 0xfff) << 14);
>> +		       | (vlen & 0x3fff) << 14);
>>      return val;
>>    }
>>  };
>> -- 
>> 2.41.0
>