* Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers [not found] <20221206053947.821648-1-zengxiao@eswincomputing.com> @ 2022-12-06 6:59 ` Nelson Chu 2022-12-06 10:21 ` Andrew Burgess 0 siblings, 1 reply; 5+ messages in thread From: Nelson Chu @ 2022-12-06 6:59 UTC (permalink / raw) To: gdb-patches; +Cc: Andrew Burgess Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. Thanks Nelson ---------- Forwarded message --------- From: Xiao Zeng <zengxiao@eswincomputing.com> Date: Tue, Dec 6, 2022 at 1:39 PM Subject: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers To: <binutils@sourceware.org> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> According to the riscv psabi, the mapping relationship between the dwarf registers and the machine registers are as follows: DWARF Number | Register Name | Description 0 - 31 | x0 - x31 | Integer Registers 32 - 63 | f0 - f31 | Floating-point Registers * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping boundary register. --- gdb/riscv-tdep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 0a050b272ff..a298623b449 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) static int riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) { - if (reg < RISCV_DWARF_REGNUM_X31) + if (reg <= RISCV_DWARF_REGNUM_X31) return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); - else if (reg < RISCV_DWARF_REGNUM_F31) + else if (reg <= RISCV_DWARF_REGNUM_F31) return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) -- 2.34.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers 2022-12-06 6:59 ` Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers Nelson Chu @ 2022-12-06 10:21 ` Andrew Burgess 2022-12-07 1:45 ` Xiao Zeng 0 siblings, 1 reply; 5+ messages in thread From: Andrew Burgess @ 2022-12-06 10:21 UTC (permalink / raw) To: Nelson Chu, gdb-patches; +Cc: Xiao Zeng Nelson Chu <nelson@rivosinc.com> writes: > Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. > > Thanks > Nelson > > ---------- Forwarded message --------- > From: Xiao Zeng <zengxiao@eswincomputing.com> > Date: Tue, Dec 6, 2022 at 1:39 PM > Subject: [PATCH] RISC-V: Correction of machine registers mapping to > dwarf registers > To: <binutils@sourceware.org> > Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, > <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> > > > According to the riscv psabi, the mapping relationship between the > dwarf registers and the machine registers are as follows: > > DWARF Number | Register Name | Description > 0 - 31 | x0 - x31 | Integer Registers > 32 - 63 | f0 - f31 | Floating-point Registers > > * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping > boundary register. Thanks for catching this. I went ahead and merged this patch. Thanks, Andrew > --- > gdb/riscv-tdep.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index 0a050b272ff..a298623b449 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) > static int > riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) > { > - if (reg < RISCV_DWARF_REGNUM_X31) > + if (reg <= RISCV_DWARF_REGNUM_X31) > return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); > > - else if (reg < RISCV_DWARF_REGNUM_F31) > + else if (reg <= RISCV_DWARF_REGNUM_F31) > return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); > > else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) > -- > 2.34.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers 2022-12-06 10:21 ` Andrew Burgess @ 2022-12-07 1:45 ` Xiao Zeng 2022-12-07 1:50 ` Andrew Pinski 0 siblings, 1 reply; 5+ messages in thread From: Xiao Zeng @ 2022-12-07 1:45 UTC (permalink / raw) To: Andrew Burgess, Nelson Chu, gdb-patches On Tue, Dec 6, 2022 at 12:00:00 AM Andrew Burgess <aburgess@redhat.com> wrote: > >Nelson Chu <nelson@rivosinc.com> writes: > >> Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. >> I will mention the gdb patch in the correct mailing list next time，thanks Nelson. >> Thanks >> Nelson >> >> ---------- Forwarded message --------- >> From: Xiao Zeng <zengxiao@eswincomputing.com> >> Date: Tue, Dec 6, 2022 at 1:39 PM >> Subject: [PATCH] RISC-V: Correction of machine registers mapping to >> dwarf registers >> To: <binutils@sourceware.org> >> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, >> <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> >> >> >> According to the riscv psabi, the mapping relationship between the >> dwarf registers and the machine registers are as follows: >> >> DWARF Number | Register Name | Description >> 0 - 31 | x0 - x31 | Integer Registers >> 32 - 63 | f0 - f31 | Floating-point Registers >> >> * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping >> boundary register. > >Thanks for catching this. I went ahead and merged this patch. > >Thanks, >Andrew hi, Andrew I still don't know why gdb has a separate mailing list as a part of bintuils. Can you give me an explanation when you are free? Thanks Xiao > >> --- >> gdb/riscv-tdep.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c >> index 0a050b272ff..a298623b449 100644 >> --- a/gdb/riscv-tdep.c >> +++ b/gdb/riscv-tdep.c >> @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) >> static int >> riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) >> { >> - if (reg < RISCV_DWARF_REGNUM_X31) >> + if (reg <= RISCV_DWARF_REGNUM_X31) >> return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); >> >> - else if (reg < RISCV_DWARF_REGNUM_F31) >> + else if (reg <= RISCV_DWARF_REGNUM_F31) >> return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); >> >> else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) >> -- >> 2.34.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers 2022-12-07 1:45 ` Xiao Zeng @ 2022-12-07 1:50 ` Andrew Pinski 2022-12-07 2:00 ` Xiao Zeng 0 siblings, 1 reply; 5+ messages in thread From: Andrew Pinski @ 2022-12-07 1:50 UTC (permalink / raw) To: Xiao Zeng; +Cc: Andrew Burgess, Nelson Chu, gdb-patches On Tue, Dec 6, 2022 at 5:46 PM Xiao Zeng <zengxiao@eswincomputing.com> wrote: > > On Tue, Dec 6, 2022 at 12:00:00 AM Andrew Burgess <aburgess@redhat.com> wrote: > > > >Nelson Chu <nelson@rivosinc.com> writes: > > > >> Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. > >> > > I will mention the gdb patch in the correct mailing list next time，thanks Nelson. > > >> Thanks > >> Nelson > >> > >> ---------- Forwarded message --------- > >> From: Xiao Zeng <zengxiao@eswincomputing.com> > >> Date: Tue, Dec 6, 2022 at 1:39 PM > >> Subject: [PATCH] RISC-V: Correction of machine registers mapping to > >> dwarf registers > >> To: <binutils@sourceware.org> > >> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, > >> <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> > >> > >> > >> According to the riscv psabi, the mapping relationship between the > >> dwarf registers and the machine registers are as follows: > >> > >> DWARF Number | Register Name | Description > >> 0 - 31 | x0 - x31 | Integer Registers > >> 32 - 63 | f0 - f31 | Floating-point Registers > >> > >> * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping > >> boundary register. > > > >Thanks for catching this. I went ahead and merged this patch. > > > >Thanks, > >Andrew > > hi, Andrew > I still don't know why gdb has a separate mailing list as a part of bintuils. > Can you give me an explanation when you are free? Because technically they are separate projects with their own release schedules. Just happens they share the same repositories; mostly because BFD is common between the two. Thanks, Andrew > > Thanks > Xiao > > > > >> --- > >> gdb/riscv-tdep.c | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > >> index 0a050b272ff..a298623b449 100644 > >> --- a/gdb/riscv-tdep.c > >> +++ b/gdb/riscv-tdep.c > >> @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) > >> static int > >> riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) > >> { > >> - if (reg < RISCV_DWARF_REGNUM_X31) > >> + if (reg <= RISCV_DWARF_REGNUM_X31) > >> return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); > >> > >> - else if (reg < RISCV_DWARF_REGNUM_F31) > >> + else if (reg <= RISCV_DWARF_REGNUM_F31) > >> return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); > >> > >> else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) > >> -- > >> 2.34.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers 2022-12-07 1:50 ` Andrew Pinski @ 2022-12-07 2:00 ` Xiao Zeng 0 siblings, 0 replies; 5+ messages in thread From: Xiao Zeng @ 2022-12-07 2:00 UTC (permalink / raw) To: Andrew Pinski; +Cc: Andrew Burgess, Nelson Chu, gdb-patches On Wed, Dec 7, 2022 at 09:50:00 AM Andrew Pinski <pinskia@gmail.com> wrote: > >On Tue, Dec 6, 2022 at 5:46 PM Xiao Zeng <zengxiao@eswincomputing.com> wrote: >> >> On Tue, Dec 6, 2022 at 12:00:00 AM Andrew Burgess <aburgess@redhat.com> wrote: >> > >> >Nelson Chu <nelson@rivosinc.com> writes: >> > >> >> Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. >> >> >> >> I will mention the gdb patch in the correct mailing list next time，thanks Nelson. >> >> >> Thanks >> >> Nelson >> >> >> >> ---------- Forwarded message --------- >> >> From: Xiao Zeng <zengxiao@eswincomputing.com> >> >> Date: Tue, Dec 6, 2022 at 1:39 PM >> >> Subject: [PATCH] RISC-V: Correction of machine registers mapping to >> >> dwarf registers >> >> To: <binutils@sourceware.org> >> >> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, >> >> <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> >> >> >> >> >> >> According to the riscv psabi, the mapping relationship between the >> >> dwarf registers and the machine registers are as follows: >> >> >> >> DWARF Number | Register Name | Description >> >> 0 - 31 | x0 - x31 | Integer Registers >> >> 32 - 63 | f0 - f31 | Floating-point Registers >> >> >> >> * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping >> >> boundary register. >> > >> >Thanks for catching this. I went ahead and merged this patch. >> > >> >Thanks, >> >Andrew >> >> hi, Andrew >> I still don't know why gdb has a separate mailing list as a part of bintuils. >> Can you give me an explanation when you are free? > >Because technically they are separate projects with their own release >schedules. Just happens they share the same repositories; mostly >because BFD is common between the two. > >Thanks, >Andrew I see, thanks Andrew. Thanks Xiao > >> >> Thanks >> Xiao >> >> > >> >> --- >> >> gdb/riscv-tdep.c | 4 ++-- >> >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> >> >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c >> >> index 0a050b272ff..a298623b449 100644 >> >> --- a/gdb/riscv-tdep.c >> >> +++ b/gdb/riscv-tdep.c >> >> @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) >> >> static int >> >> riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) >> >> { >> >> - if (reg < RISCV_DWARF_REGNUM_X31) >> >> + if (reg <= RISCV_DWARF_REGNUM_X31) >> >> return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); >> >> >> >> - else if (reg < RISCV_DWARF_REGNUM_F31) >> >> + else if (reg <= RISCV_DWARF_REGNUM_F31) >> >> return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); >> >> >> >> else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) >> >> -- >> >> 2.34.1 >> >> ^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <20221206053947.821648-1-zengxiao@eswincomputing.com>
2022-12-06 6:59 ` Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers Nelson Chu
2022-12-06 10:21 ` Andrew Burgess
2022-12-07 1:45 ` Xiao Zeng
2022-12-07 1:50 ` Andrew Pinski
2022-12-07 2:00 ` Xiao Zeng
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