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From: "Metzger, Markus T" <markus.t.metzger@intel.com>
To: Simon Marchi <simark@simark.ca>,
	Shahab Vahedi <shahab.vahedi@gmail.com>,
	 Luis Machado <luis.machado@linaro.org>
Cc: "gdb@sourceware.org" <gdb@sourceware.org>,
	Shahab Vahedi <shahab@synopsys.com>
Subject: RE: Why enforcing sw_breakpoint_from_kind() implementation in GDBserver targets
Date: Mon, 15 Jun 2020 08:54:47 +0000	[thread overview]
Message-ID: <DM5PR11MB1690C83D9D3314AC5A7D952BDE9C0@DM5PR11MB1690.namprd11.prod.outlook.com> (raw)
In-Reply-To: <335e5978-4893-b355-69cd-98a101f8dd2e@simark.ca>

> >>> The ARC GDB client inserts the breakpoint by writing to memory (the
> >>> legacy way). With your explanations, I plan to add the Z0 packet
> >>> support to it.  Nevertheless, should it be still necessary to have
> >>> "sw_breakpoint_from_kind" in GDBserver as a mandatory method?
> >
> > Simon, I thought about this a little. Are we aiming for deprecating
> > the old way? Then I guess that's the way to go.
> 
> If all the gdbserver targets we support do support Z0, then yes I think
> we could consider doing that.  How would we do it?  Make insert_point
> and remove_point virtual pure to force sub-classes to implement them
> with something meaningful?
> 
> Note that this would only concern GDBserver, other server implementations
> of the remote protocol are free to support Z0 or not.  But we could decide
> that all GDBserver ports have to support it.

The Intel Graphics architecture uses breakpoint bits inside instructions.  There
is no single breakpoint opcode as there is INT3 on IA, for example.

The breakpoint can be ignored one time, which allows stepping over breakpoints
without having to  remove them.  This obviously only works if the breakpoint bit
in the original instruction is set and the instruction is not replaced with a fixed
breakpoint pattern.

I've been looking into z packets and insert/remove_point () target methods.
Since struct raw_breakpoint is opaque, it would not allow me to store a shadow
copy - unless I extended mem-break.cc to do that for me.

I ended up using the gdbarch methods.

Regards,
Markus.

Intel Deutschland GmbH
Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Christin Eisenschmid, Gary Kershaw
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

  reply	other threads:[~2020-06-15  8:54 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-10 17:47 Shahab Vahedi
2020-06-11  3:05 ` Simon Marchi
2020-06-11  9:40   ` Shahab Vahedi
2020-06-11 10:35     ` Luis Machado
2020-06-11 11:00       ` Shahab Vahedi
2020-06-11 11:44         ` Shahab Vahedi
2020-06-12 11:04           ` Aktemur, Tankut Baris
2020-06-15 10:39             ` Shahab Vahedi
2020-06-16 13:15               ` Aktemur, Tankut Baris
2020-06-17 21:31                 ` Shahab Vahedi
2020-06-17 22:20                   ` Luis Machado
2020-06-11 14:51         ` Simon Marchi
2020-06-15  8:54           ` Metzger, Markus T [this message]
2020-06-17  0:40             ` Maciej W. Rozycki
2020-06-18  8:11               ` Metzger, Markus T
2020-06-18  9:13                 ` Maciej W. Rozycki
2020-06-18 10:29                   ` Metzger, Markus T
2020-06-18 11:03                     ` Maciej W. Rozycki
2020-06-18 11:11                       ` Metzger, Markus T
2020-06-11 21:21 ` Martin Simmons

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