[Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le

["bruno at clisp dot org" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=30988

--- Comment #3 from Bruno Haible <bruno at clisp dot org> ---
(In reply to Adhemerval Zanella from comment #2)
> Indeed, this seems to be an unexpected side-effect of how we implement the
> GNU extension feenableexcept

There's no better way, IMO, to implement feenableexcept. The problem
really comes from the hardware.

> Maybe something like:
> 
> diff --git a/sysdeps/powerpc/fpu/fesetexcept.c
> b/sysdeps/powerpc/fpu/fesetexcept.c
> index 609a148a95..e5396daf44 100644
> --- a/sysdeps/powerpc/fpu/fesetexcept.c
> +++ b/sysdeps/powerpc/fpu/fesetexcept.c
> @@ -29,6 +29,10 @@ fesetexcept (int excepts)
>          /* Turn FE_INVALID into FE_INVALID_SOFTWARE.  */
>          | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
>             & FE_INVALID_SOFTWARE));
> +
> +  if (u.l & FPSCR_ENABLES_MASK)
> +    return -1;
> +
>    if (n.l != u.l)
>      {
>        fesetenv_register (n.fenv);

This patch has the drawback of failing even in some situations that it could
handle. For example, if trapping on FE_DIVBYZERO is enabled and someone calls
fesetexcept (FE_INVALID), there is no reason to fail. I would therefore suggest
this patch instead:

diff --git a/sysdeps/powerpc/fpu/fesetexcept.c
b/sysdeps/powerpc/fpu/fesetexcept.c
index 609a148a95..5137df7ba1 100644
--- a/sysdeps/powerpc/fpu/fesetexcept.c
+++ b/sysdeps/powerpc/fpu/fesetexcept.c
@@ -31,6 +31,13 @@ fesetexcept (int excepts)
            & FE_INVALID_SOFTWARE));
   if (n.l != u.l)
     {
+      if (n.l & (exceptions >> FPSCR_EXCEPT_TO_ENABLE_SHIFT))
+        {
+          /* Setting the exception flags may trigger a trap.
+             ISO C 23 § 7.6.4.4 does not allow it.  */
+          return 1;
+        }
+
       fesetenv_register (n.fenv);

       /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. 
*/

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