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* [glibc/arm/morello/main] TODO(uapi): cheri: start: restrict auxv capability permissions
@ 2022-10-26 15:20 Szabolcs Nagy
0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-10-26 15:20 UTC (permalink / raw)
To: glibc-cvs
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=487d4e0adb5a90cf0ac9a2d6716a472bc78ffb58
commit 487d4e0adb5a90cf0ac9a2d6716a472bc78ffb58
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Fri Oct 21 09:52:47 2022 +0100
TODO(uapi): cheri: start: restrict auxv capability permissions
TODO: not needed with full pcuabi
Diff:
---
elf/dl-support.c | 2 ++
elf/rtld.c | 2 ++
sysdeps/aarch64/morello/dl-machine.h | 2 ++
sysdeps/aarch64/morello/start.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/elf/dl-support.c b/elf/dl-support.c
index ffc1d8d01b..f2f0bdbaf4 100644
--- a/elf/dl-support.c
+++ b/elf/dl-support.c
@@ -258,7 +258,9 @@ _dl_aux_init (ElfW(auxv_t) *av)
# ifdef __CHERI_PURE_CAPABILITY__
_dl_main_map.l_map_start = auxv_values[AT_CHERI_EXEC_RX_CAP];
+ _dl_main_map.l_map_start = __builtin_cheri_perms_and (_dl_main_map.l_map_start, CAP_PERM_MASK_RX);
_dl_main_map.l_rw_start = auxv_values[AT_CHERI_EXEC_RW_CAP];
+ _dl_main_map.l_rw_start = __builtin_cheri_perms_and (_dl_main_map.l_rw_start, CAP_PERM_MASK_RW);
# endif
}
#endif
diff --git a/elf/rtld.c b/elf/rtld.c
index 41ffb297e5..7eeb5c174b 100644
--- a/elf/rtld.c
+++ b/elf/rtld.c
@@ -1724,9 +1724,11 @@ dl_main (const ElfW(Phdr) *phdr,
{
case AT_CHERI_EXEC_RX_CAP:
main_map->l_map_start = av->a_un.a_val;
+ main_map->l_map_start = __builtin_cheri_perms_and (main_map->l_map_start, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
main_map->l_rw_start = av->a_un.a_val;
+ main_map->l_rw_start = __builtin_cheri_perms_and (main_map->l_rw_start, CAP_PERM_MASK_RW);
break;
}
#endif
diff --git a/sysdeps/aarch64/morello/dl-machine.h b/sysdeps/aarch64/morello/dl-machine.h
index 0f681b1925..7da7c5bfc0 100644
--- a/sysdeps/aarch64/morello/dl-machine.h
+++ b/sysdeps/aarch64/morello/dl-machine.h
@@ -152,6 +152,8 @@ elf_machine_rtld_base_setup (struct link_map *map, void *args)
cap_rw = cap_exe_rw;
ldso_base = cap_rx; /* Assume load segments start at vaddr 0. */
}
+ cap_rx = __builtin_cheri_perms_and (cap_rx, CAP_PERM_MASK_RX);
+ cap_rw = __builtin_cheri_perms_and (cap_rw, CAP_PERM_MASK_RW);
map->l_addr = ldso_base;
map->l_map_start = cap_rx;
map->l_rw_start = cap_rw;
diff --git a/sysdeps/aarch64/morello/start.c b/sysdeps/aarch64/morello/start.c
index de7aeab4c9..5d413ae78e 100644
--- a/sysdeps/aarch64/morello/start.c
+++ b/sysdeps/aarch64/morello/start.c
@@ -124,9 +124,11 @@ get_caps (uintptr_t *cap_rx, uintptr_t *cap_rw, const uintptr_t *auxv)
return;
case AT_CHERI_EXEC_RX_CAP:
*cap_rx = auxv[1];
+ *cap_rx = __builtin_cheri_perms_and (*cap_rx, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
*cap_rw = auxv[1];
+ *cap_rw = __builtin_cheri_perms_and (*cap_rw, CAP_PERM_MASK_RW);
break;
}
auxv += 2;
^ permalink raw reply [flat|nested] 4+ messages in thread
* [glibc/arm/morello/main] TODO(uapi): cheri: start: restrict auxv capability permissions
@ 2022-11-23 14:49 Szabolcs Nagy
0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-11-23 14:49 UTC (permalink / raw)
To: glibc-cvs
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=4deaee41ce96e7666613ccffcc2499d6f2a8ae98
commit 4deaee41ce96e7666613ccffcc2499d6f2a8ae98
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Fri Oct 21 09:52:47 2022 +0100
TODO(uapi): cheri: start: restrict auxv capability permissions
TODO: not needed with full pcuabi
Diff:
---
elf/dl-support.c | 2 ++
elf/rtld.c | 2 ++
sysdeps/aarch64/morello/dl-machine.h | 2 ++
sysdeps/aarch64/morello/start.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/elf/dl-support.c b/elf/dl-support.c
index ffc1d8d01b..f2f0bdbaf4 100644
--- a/elf/dl-support.c
+++ b/elf/dl-support.c
@@ -258,7 +258,9 @@ _dl_aux_init (ElfW(auxv_t) *av)
# ifdef __CHERI_PURE_CAPABILITY__
_dl_main_map.l_map_start = auxv_values[AT_CHERI_EXEC_RX_CAP];
+ _dl_main_map.l_map_start = __builtin_cheri_perms_and (_dl_main_map.l_map_start, CAP_PERM_MASK_RX);
_dl_main_map.l_rw_start = auxv_values[AT_CHERI_EXEC_RW_CAP];
+ _dl_main_map.l_rw_start = __builtin_cheri_perms_and (_dl_main_map.l_rw_start, CAP_PERM_MASK_RW);
# endif
}
#endif
diff --git a/elf/rtld.c b/elf/rtld.c
index 41ffb297e5..7eeb5c174b 100644
--- a/elf/rtld.c
+++ b/elf/rtld.c
@@ -1724,9 +1724,11 @@ dl_main (const ElfW(Phdr) *phdr,
{
case AT_CHERI_EXEC_RX_CAP:
main_map->l_map_start = av->a_un.a_val;
+ main_map->l_map_start = __builtin_cheri_perms_and (main_map->l_map_start, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
main_map->l_rw_start = av->a_un.a_val;
+ main_map->l_rw_start = __builtin_cheri_perms_and (main_map->l_rw_start, CAP_PERM_MASK_RW);
break;
}
#endif
diff --git a/sysdeps/aarch64/morello/dl-machine.h b/sysdeps/aarch64/morello/dl-machine.h
index 0f681b1925..7da7c5bfc0 100644
--- a/sysdeps/aarch64/morello/dl-machine.h
+++ b/sysdeps/aarch64/morello/dl-machine.h
@@ -152,6 +152,8 @@ elf_machine_rtld_base_setup (struct link_map *map, void *args)
cap_rw = cap_exe_rw;
ldso_base = cap_rx; /* Assume load segments start at vaddr 0. */
}
+ cap_rx = __builtin_cheri_perms_and (cap_rx, CAP_PERM_MASK_RX);
+ cap_rw = __builtin_cheri_perms_and (cap_rw, CAP_PERM_MASK_RW);
map->l_addr = ldso_base;
map->l_map_start = cap_rx;
map->l_rw_start = cap_rw;
diff --git a/sysdeps/aarch64/morello/start.c b/sysdeps/aarch64/morello/start.c
index de7aeab4c9..5d413ae78e 100644
--- a/sysdeps/aarch64/morello/start.c
+++ b/sysdeps/aarch64/morello/start.c
@@ -124,9 +124,11 @@ get_caps (uintptr_t *cap_rx, uintptr_t *cap_rw, const uintptr_t *auxv)
return;
case AT_CHERI_EXEC_RX_CAP:
*cap_rx = auxv[1];
+ *cap_rx = __builtin_cheri_perms_and (*cap_rx, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
*cap_rw = auxv[1];
+ *cap_rw = __builtin_cheri_perms_and (*cap_rw, CAP_PERM_MASK_RW);
break;
}
auxv += 2;
^ permalink raw reply [flat|nested] 4+ messages in thread
* [glibc/arm/morello/main] TODO(uapi): cheri: start: restrict auxv capability permissions
@ 2022-10-27 13:59 Szabolcs Nagy
0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-10-27 13:59 UTC (permalink / raw)
To: glibc-cvs
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=5a4c66e5b37e3ce78d8cfc3b9229d9d73a6bab39
commit 5a4c66e5b37e3ce78d8cfc3b9229d9d73a6bab39
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Fri Oct 21 09:52:47 2022 +0100
TODO(uapi): cheri: start: restrict auxv capability permissions
TODO: not needed with full pcuabi
Diff:
---
elf/dl-support.c | 2 ++
elf/rtld.c | 2 ++
sysdeps/aarch64/morello/dl-machine.h | 2 ++
sysdeps/aarch64/morello/start.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/elf/dl-support.c b/elf/dl-support.c
index ffc1d8d01b..f2f0bdbaf4 100644
--- a/elf/dl-support.c
+++ b/elf/dl-support.c
@@ -258,7 +258,9 @@ _dl_aux_init (ElfW(auxv_t) *av)
# ifdef __CHERI_PURE_CAPABILITY__
_dl_main_map.l_map_start = auxv_values[AT_CHERI_EXEC_RX_CAP];
+ _dl_main_map.l_map_start = __builtin_cheri_perms_and (_dl_main_map.l_map_start, CAP_PERM_MASK_RX);
_dl_main_map.l_rw_start = auxv_values[AT_CHERI_EXEC_RW_CAP];
+ _dl_main_map.l_rw_start = __builtin_cheri_perms_and (_dl_main_map.l_rw_start, CAP_PERM_MASK_RW);
# endif
}
#endif
diff --git a/elf/rtld.c b/elf/rtld.c
index 41ffb297e5..7eeb5c174b 100644
--- a/elf/rtld.c
+++ b/elf/rtld.c
@@ -1724,9 +1724,11 @@ dl_main (const ElfW(Phdr) *phdr,
{
case AT_CHERI_EXEC_RX_CAP:
main_map->l_map_start = av->a_un.a_val;
+ main_map->l_map_start = __builtin_cheri_perms_and (main_map->l_map_start, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
main_map->l_rw_start = av->a_un.a_val;
+ main_map->l_rw_start = __builtin_cheri_perms_and (main_map->l_rw_start, CAP_PERM_MASK_RW);
break;
}
#endif
diff --git a/sysdeps/aarch64/morello/dl-machine.h b/sysdeps/aarch64/morello/dl-machine.h
index 0f681b1925..7da7c5bfc0 100644
--- a/sysdeps/aarch64/morello/dl-machine.h
+++ b/sysdeps/aarch64/morello/dl-machine.h
@@ -152,6 +152,8 @@ elf_machine_rtld_base_setup (struct link_map *map, void *args)
cap_rw = cap_exe_rw;
ldso_base = cap_rx; /* Assume load segments start at vaddr 0. */
}
+ cap_rx = __builtin_cheri_perms_and (cap_rx, CAP_PERM_MASK_RX);
+ cap_rw = __builtin_cheri_perms_and (cap_rw, CAP_PERM_MASK_RW);
map->l_addr = ldso_base;
map->l_map_start = cap_rx;
map->l_rw_start = cap_rw;
diff --git a/sysdeps/aarch64/morello/start.c b/sysdeps/aarch64/morello/start.c
index de7aeab4c9..5d413ae78e 100644
--- a/sysdeps/aarch64/morello/start.c
+++ b/sysdeps/aarch64/morello/start.c
@@ -124,9 +124,11 @@ get_caps (uintptr_t *cap_rx, uintptr_t *cap_rw, const uintptr_t *auxv)
return;
case AT_CHERI_EXEC_RX_CAP:
*cap_rx = auxv[1];
+ *cap_rx = __builtin_cheri_perms_and (*cap_rx, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
*cap_rw = auxv[1];
+ *cap_rw = __builtin_cheri_perms_and (*cap_rw, CAP_PERM_MASK_RW);
break;
}
auxv += 2;
^ permalink raw reply [flat|nested] 4+ messages in thread
* [glibc/arm/morello/main] TODO(uapi): cheri: start: restrict auxv capability permissions
@ 2022-10-26 14:49 Szabolcs Nagy
0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-10-26 14:49 UTC (permalink / raw)
To: glibc-cvs
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=e8d0e61aa2392f852c02725eb9af9b2f4139d076
commit e8d0e61aa2392f852c02725eb9af9b2f4139d076
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Fri Oct 21 09:52:47 2022 +0100
TODO(uapi): cheri: start: restrict auxv capability permissions
TODO: not needed with full pcuabi
Diff:
---
elf/dl-support.c | 2 ++
elf/rtld.c | 2 ++
sysdeps/aarch64/morello/dl-machine.h | 2 ++
sysdeps/aarch64/morello/start.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/elf/dl-support.c b/elf/dl-support.c
index ffc1d8d01b..f2f0bdbaf4 100644
--- a/elf/dl-support.c
+++ b/elf/dl-support.c
@@ -258,7 +258,9 @@ _dl_aux_init (ElfW(auxv_t) *av)
# ifdef __CHERI_PURE_CAPABILITY__
_dl_main_map.l_map_start = auxv_values[AT_CHERI_EXEC_RX_CAP];
+ _dl_main_map.l_map_start = __builtin_cheri_perms_and (_dl_main_map.l_map_start, CAP_PERM_MASK_RX);
_dl_main_map.l_rw_start = auxv_values[AT_CHERI_EXEC_RW_CAP];
+ _dl_main_map.l_rw_start = __builtin_cheri_perms_and (_dl_main_map.l_rw_start, CAP_PERM_MASK_RW);
# endif
}
#endif
diff --git a/elf/rtld.c b/elf/rtld.c
index 753211772c..daff17a9e1 100644
--- a/elf/rtld.c
+++ b/elf/rtld.c
@@ -1724,9 +1724,11 @@ dl_main (const ElfW(Phdr) *phdr,
{
case AT_CHERI_EXEC_RX_CAP:
main_map->l_map_start = av->a_un.a_val;
+ main_map->l_map_start = __builtin_cheri_perms_and (main_map->l_map_start, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
main_map->l_rw_start = av->a_un.a_val;
+ main_map->l_rw_start = __builtin_cheri_perms_and (main_map->l_rw_start, CAP_PERM_MASK_RW);
break;
}
#endif
diff --git a/sysdeps/aarch64/morello/dl-machine.h b/sysdeps/aarch64/morello/dl-machine.h
index 0f681b1925..7da7c5bfc0 100644
--- a/sysdeps/aarch64/morello/dl-machine.h
+++ b/sysdeps/aarch64/morello/dl-machine.h
@@ -152,6 +152,8 @@ elf_machine_rtld_base_setup (struct link_map *map, void *args)
cap_rw = cap_exe_rw;
ldso_base = cap_rx; /* Assume load segments start at vaddr 0. */
}
+ cap_rx = __builtin_cheri_perms_and (cap_rx, CAP_PERM_MASK_RX);
+ cap_rw = __builtin_cheri_perms_and (cap_rw, CAP_PERM_MASK_RW);
map->l_addr = ldso_base;
map->l_map_start = cap_rx;
map->l_rw_start = cap_rw;
diff --git a/sysdeps/aarch64/morello/start.c b/sysdeps/aarch64/morello/start.c
index de7aeab4c9..5d413ae78e 100644
--- a/sysdeps/aarch64/morello/start.c
+++ b/sysdeps/aarch64/morello/start.c
@@ -124,9 +124,11 @@ get_caps (uintptr_t *cap_rx, uintptr_t *cap_rw, const uintptr_t *auxv)
return;
case AT_CHERI_EXEC_RX_CAP:
*cap_rx = auxv[1];
+ *cap_rx = __builtin_cheri_perms_and (*cap_rx, CAP_PERM_MASK_RX);
break;
case AT_CHERI_EXEC_RW_CAP:
*cap_rw = auxv[1];
+ *cap_rw = __builtin_cheri_perms_and (*cap_rw, CAP_PERM_MASK_RW);
break;
}
auxv += 2;
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-11-23 14:49 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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