From: Jeff Law <jlaw@ventanamicro.com>
To: Richard Henderson <richard.henderson@linaro.org>,
Vineet Gupta <vineetg@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>
Cc: "Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Vincent Chen" <vincent.chen@sifive.com>,
"Florian Weimer" <fweimer@redhat.com>,
"Rich Felker" <dalias@libc.org>,
"Andrew Waterman" <andrew@sifive.com>,
"Palmer Dabbelt" <palmer@rivosinc.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
davidlt@rivosinc.com, "Arnd Bergmann" <arnd@arndb.de>,
"Björn Töpel" <bjorn@kernel.org>,
"Szabolcs Nagy" <szabolcs.nagy@arm.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Aaron Durbin" <adurbin@rivosinc.com>,
"Andrew de los Reyes" <adlr@rivosinc.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"GNU C Library" <libc-alpha@sourceware.org>
Subject: Re: Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break)
Date: Tue, 10 Jan 2023 22:07:39 -0700 [thread overview]
Message-ID: <6d13e63f-69b3-6e48-b811-bbfcf3ffb3af@ventanamicro.com> (raw)
In-Reply-To: <8be4d673-f435-429e-9a61-bb49e7820529@linaro.org>
On 1/10/23 21:57, Richard Henderson wrote:
> On 1/10/23 20:28, Jeff Law wrote:
>>
>>
>> On 1/10/23 18:22, Richard Henderson wrote:
>>> On 1/10/23 10:07, Vineet Gupta wrote:
>>>> Yes bulk of glibc might not have vector code, but those V ifunc
>>>> routines do and IMO this information needs to be recorded somewhere
>>>> in the elf. Case in point being the current issue with how to enable
>>>> V unit. Community wants a per-process enable, using an explicit
>>>> prctl from userspace (since RV doesn't have fault-on-first use
>>>> hardware mechanism unlike some of the other arches). But how does
>>>> the glibc loader know to invoke prctl. We can't just rely on user
>>>> env GLIBC_TUNABLE etc since that might not be accurate. It needs
>>>> somethign concrete which IMO can come from elf attributes. If not,
>>>> do you have suggestions on how to solve this issue ?
>>>
>>> Why not just fault on first use to enable? That's vastly less
>>> complicated than trying to plumb anything through elf resulting in a
>>> prctl.
>> Well, the answer is in Vineet's paragraph -- the hardware apparently
>> doesn't have fault-on-first-use which is mighty unfortunate.
>
> Nonsense -- sstatus.vs stores {off, initial, clean, dirty} state, just
> like fpu.
> Now treat the vector unit just like fpu lazy migration.
Then let's do something sensible. Manually enabling via prctl seems
silly if we have fault on first use.
jeff
next prev parent reply other threads:[~2023-01-11 5:07 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 1:41 [RFC patch 0/5] RISC-V: Add vector ISA support Vincent Chen
2021-09-13 1:41 ` [RFC patch 1/5] RISC-V: Remove riscv-specific sigcontext.h Vincent Chen
2021-09-13 1:41 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Vincent Chen
2021-09-13 13:44 ` Florian Weimer
2021-09-13 13:52 ` Rich Felker
2021-09-16 8:02 ` Vincent Chen
2021-09-16 8:14 ` Florian Weimer
2021-09-18 3:04 ` Vincent Chen
2022-12-09 3:39 ` RISCV kernel struct sigcontext expansion for V regs and potential glibc ABI break (was Re: [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion.) Vineet Gupta
2022-12-09 4:03 ` Vineet Gupta
2022-12-20 20:05 ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Vineet Gupta
2022-12-21 15:53 ` Vincent Chen
2022-12-21 19:45 ` Vineet Gupta
2022-12-21 19:52 ` Vineet Gupta
2022-12-22 3:37 ` Vincent Chen
2022-12-22 19:25 ` Vineet Gupta
2022-12-23 2:27 ` Vincent Chen
2022-12-23 19:42 ` Vineet Gupta
2022-12-22 5:32 ` Richard Henderson
2022-12-22 18:33 ` Andy Chiu
2022-12-22 20:27 ` Vineet Gupta
2022-12-28 10:53 ` Andy Chiu
2023-01-03 19:17 ` Vineet Gupta
2023-01-04 16:34 ` Andy Chiu
2023-01-04 20:46 ` Vineet Gupta
2023-01-04 21:29 ` Philipp Tomsich
2023-01-04 21:37 ` Andrew Waterman
2023-01-04 22:43 ` Vineet Gupta
2023-01-09 13:33 ` Kito Cheng
2023-01-09 19:16 ` Vineet Gupta
2023-01-10 13:21 ` Kito Cheng
2023-01-10 18:07 ` Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break) Vineet Gupta
2023-01-11 1:22 ` Richard Henderson
2023-01-11 4:28 ` Jeff Law
2023-01-11 4:57 ` Richard Henderson
2023-01-11 5:07 ` Jeff Law [this message]
2023-01-11 6:00 ` Andy Chiu
2023-01-11 6:20 ` Jeff Law
2023-01-11 9:28 ` Andy Chiu
2023-01-11 12:13 ` Andy Chiu
2023-01-23 12:17 ` Conor Dooley
2023-01-23 13:29 ` Andy Chiu
2023-01-11 5:05 ` Anup Patel
2023-01-11 5:23 ` Richard Henderson
2022-12-22 22:33 ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Richard Henderson
2022-12-22 23:47 ` Conor Dooley
2022-12-22 23:58 ` Vineet Gupta
2022-12-22 20:30 ` Vineet Gupta
2022-12-22 21:38 ` Andrew Waterman
2022-12-22 1:50 ` Vincent Chen
2022-12-22 5:34 ` Richard Henderson
2021-09-16 23:56 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Ben Woodard
2021-09-18 3:15 ` Vincent Chen
2021-09-20 16:41 ` DJ Delorie
2021-09-20 17:10 ` Florian Weimer
2021-10-01 1:43 ` Vincent Chen
2021-10-01 12:08 ` Adhemerval Zanella
2021-09-17 17:03 ` Rich Felker
2021-09-18 3:19 ` Vincent Chen
2021-09-13 1:41 ` [RFC patch 3/5] RISC-V: Save and restore VCSR when doing user context switch Vincent Chen
2021-09-14 23:48 ` Joseph Myers
2021-09-15 0:13 ` Andrew Waterman
2021-09-16 9:20 ` Vincent Chen
2021-10-01 13:04 ` Adhemerval Zanella
2021-09-13 1:41 ` [RFC patch 4/5] RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers Vincent Chen
2021-09-13 13:51 ` Rich Felker
2021-09-16 9:25 ` Vincent Chen
2021-09-13 1:41 ` [RFC 5/5] RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment Vincent Chen
2021-09-14 23:43 ` Joseph Myers
2021-09-15 10:42 ` Florian Weimer
2021-09-15 14:31 ` H.J. Lu
2021-09-16 10:21 ` Vincent Chen
2021-09-13 19:11 ` [RFC patch 0/5] RISC-V: Add vector ISA support Vineet Gupta
2021-09-15 19:37 ` Jim Wilson
2021-11-09 19:21 ` Darius Rad
2021-11-09 19:30 ` Andrew Waterman
2021-11-09 22:03 ` Darius Rad
2021-11-09 22:18 ` Andrew Waterman
2021-11-10 11:39 ` Darius Rad
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