Re: [RFC patch 0/5] RISC-V: Add vector ISA support

[Darius Rad <darius@bluespec.com>]

On Tue, Nov 09, 2021 at 11:30:49AM -0800, Andrew Waterman wrote:
> On Tue, Nov 9, 2021 at 11:21 AM Darius Rad <darius@bluespec.com> wrote:
> >
> > On Mon, Sep 13, 2021 at 09:41:13AM +0800, Vincent Chen wrote:
> > > This patchset adds required ports to support RISC-V Vector (RVV) extension.
> > >
> > > Since the length of the vector register in RVV (the theoretical maximum
> > > is 2^XLEN-1 bits) is variable, a huge and flexible space is needed to back
> > > up all vector registers in the signal context. This patchset expands the
> > > default SIGSTKSZ, MINSIGSTKSZ, and PTHREAD_STACK_MIN to ensure the stack
> > > size is enough for the normal case (VLENB <= 128 bytes). Linux kernel also
> > > places the exact minimum signal stack size in AT_MINSIGSTKSZ entry of the
> > > auxiliary vector to inform user, so user still can know the sutible minimum
> > > signal stack size by sysconf (_SC_MINSIGSTKSZ) if the VLENB is greater
> > > than 128 bytes.
> > >
> > > In addition, according to the specification, the VCSR that combines VXRM and
> > > VXSAT has thread storage duration, so this patchset adds the required user
> > > context operation for it.
> > >
> > > Finally, the RISC-V glibc customized sigcontext.h has been removed in this
> > > patchset. to reduce the synchronization work when new extension support is
> > > introduced to the Linux environment. However, it may bring some backward
> > > incompatible issues. Therefore, I sent an RFC patch
> > > (https://sourceware.org/pipermail/libc-alpha/2020-June/115549.html)
> > > to discuss this modification before this patchset. As I mentioned in the
> > > RFC patch thread, I used OpenEmbeded to evaluate the impact. During the
> > > tests, I didn't get any compiler errors. Therefore, I infer that this
> > > modification may not cause server backward incompatible issues at this
> > > moment.
> > >
> > > 1. The RISC-V V-extension draft v1.0 can be found in
> > > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
> > > 2. The associated kernel implementation can be found in
> > > http://lists.infradead.org/pipermail/linux-riscv/2021-September/008249.html
> > > 3. QEMU with RISC-V V-extension support can be found in
> > > https://github.com/sifive/qemu/tree/rvv-1.0
> > >
> >
> > For the record on libc-alpha, I object to these changes.  In particular,
> > the lack of a user space API for the corresponding Linux support.  More
> > discussion on linux-riscv:
> >
> > https://lists.infradead.org/pipermail/linux-riscv/2021-September/thread.html#8361
> 
> I do not agree with that analysis.  The vector extension scales down
> to having potentially very little state (512 bytes on RV64) and we
> expect typical applications-processor implementations to land in the
> 512 - 2048-byte range.  This matches AVX, not AMX.  Furthermore, we
> want all implementations to take advantage of vectorized C
> string/memory functions without having to explicitly opt in.  Not
> doing this would put RISC-V at a significant competitive disadvantage
> vs. other architectures with SIMD units.
> 

The vector extension also scales up to 256 kiB, which, for comparison sake,
is considerably more than AMX.

There are those that believe AVX should have had some sort of user space
control [1], as well.

[1] https://lore.kernel.org/lkml/87k0ntazyn.ffs@nanos.tec.linutronix.de/

I don't see how having user space control either prevents glibc from using
vector by default when it is available or how it puts RISC-V at a
significant competitive disadvantage.