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From: Vincent Chen <vincent.chen@sifive.com>
To: Florian Weimer <fweimer@redhat.com>
Cc: DJ Delorie via Libc-alpha <libc-alpha@sourceware.org>,
	DJ Delorie <dj@redhat.com>
Subject: Re: [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion.
Date: Fri, 1 Oct 2021 09:43:31 +0800	[thread overview]
Message-ID: <CABvJ_xidBTsH+f281=hQ8e2Bvs5_6=0VtnznvLguP8=vSA8fEg@mail.gmail.com> (raw)
In-Reply-To: <87o88nyxz8.fsf@oldenburg.str.redhat.com>

On Tue, Sep 21, 2021 at 1:10 AM Florian Weimer <fweimer@redhat.com> wrote:
>
> * DJ Delorie via Libc-alpha:
>
> > Vincent Chen <vincent.chen@sifive.com> writes:
> >> I am not familiar with the mechanism of LD_AUDIT, so I actually do not
> >> know if this modification may have any effect on LD_AUDIT. If
> >> possible, could you briefly introduce the issues for me? Thank you
> >> very much.
> >
> > In general, when function foo() calls DSO function bar(), and bar() is
> > in an object that needs to be loaded from disk, the loader needs to save
> > foo()'s context, do a bunch of work, restore the context, and call
> > bar().
> >
> > The LD_AUDIT feature adds a lot more "do a bunch of work" both on the
> > foo->bar call, and on the bar->foo return, typically calling some third
> > party functions to process the audit messages.
> >
> > However, if the "do a bunch of work" changes registers that aren't saved
> > in the context, and aren't agreed on as "call clobbered" and thus
> > changeable, problems happen.  If foo() expects a register to be
> > preserved across the call to bar(), and the loader and audit functions
> > don't know that and clobber it, foo() breaks.
>
> One point of clarification:
>
> The issue is with register usage for passing argument and return values.
> It's more or less unrelated to whether registers are callee-saved or
> caller-saved.  So you need special LD_AUDIT support as soon it's
> possible to pass vector arguments and return values in registers (as
> opposed to memory).
>
> Thanks,
> Florian
>
Thank DJ Delorie and Florian very much for the detailed explanation
and clarification. It is really helpful for me to understand this
problem I have not noticed. Currently, I have some findings. If my
understanding is wrong, please correct me. Thank you.

The ABI for using vector registers to pass arguments and return value
is under discussion and close to ratification. As far as I know, the
riscv Glibc resolver will have a similar issue to this LD_AUDIT
problem after this new ABI is used. Hsiangkai Wang has sent a patch,
https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html,
to deal with this issue in GLIBC resolver. This patch adds a new tag,
STO_RISCV_VARIANT_CC, to indicate whether the function uses this new
ABI or not. During the relocation process, if STO_RISCV_VARIANT_CC is
set in the st_other field of the symbol being processed, the delayed
binding mechanism will be disabled. It can avoid saving vector
registers before entering the resolver function.

The LD_AUDIT problem is similar to this because we need to prevent the
auditing function from clobbering the vector registers that store the
argument to pass to the audited symbol. Therefore, I think this patch
can resolve the LD_AUDIT issue as well.

  reply	other threads:[~2021-10-01  1:43 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-13  1:41 [RFC patch 0/5] RISC-V: Add vector ISA support Vincent Chen
2021-09-13  1:41 ` [RFC patch 1/5] RISC-V: Remove riscv-specific sigcontext.h Vincent Chen
2021-09-13  1:41 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Vincent Chen
2021-09-13 13:44   ` Florian Weimer
2021-09-13 13:52     ` Rich Felker
2021-09-16  8:02       ` Vincent Chen
2021-09-16  8:14         ` Florian Weimer
2021-09-18  3:04           ` Vincent Chen
2022-12-09  3:39             ` RISCV kernel struct sigcontext expansion for V regs and potential glibc ABI break (was Re: [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion.) Vineet Gupta
2022-12-09  4:03               ` Vineet Gupta
2022-12-20 20:05               ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Vineet Gupta
2022-12-21 15:53                 ` Vincent Chen
2022-12-21 19:45                   ` Vineet Gupta
2022-12-21 19:52                     ` Vineet Gupta
2022-12-22  3:37                       ` Vincent Chen
2022-12-22 19:25                         ` Vineet Gupta
2022-12-23  2:27                           ` Vincent Chen
2022-12-23 19:42                             ` Vineet Gupta
2022-12-22  5:32                       ` Richard Henderson
2022-12-22 18:33                         ` Andy Chiu
2022-12-22 20:27                           ` Vineet Gupta
2022-12-28 10:53                             ` Andy Chiu
2023-01-03 19:17                               ` Vineet Gupta
2023-01-04 16:34                                 ` Andy Chiu
2023-01-04 20:46                                   ` Vineet Gupta
2023-01-04 21:29                                     ` Philipp Tomsich
2023-01-04 21:37                                       ` Andrew Waterman
2023-01-04 22:43                                       ` Vineet Gupta
2023-01-09 13:33                                         ` Kito Cheng
2023-01-09 19:16                                           ` Vineet Gupta
2023-01-10 13:21                                             ` Kito Cheng
2023-01-10 18:07                                               ` Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break) Vineet Gupta
2023-01-11  1:22                                                 ` Richard Henderson
2023-01-11  4:28                                                   ` Jeff Law
2023-01-11  4:57                                                     ` Richard Henderson
2023-01-11  5:07                                                       ` Jeff Law
2023-01-11  6:00                                                         ` Andy Chiu
2023-01-11  6:20                                                           ` Jeff Law
2023-01-11  9:28                                                             ` Andy Chiu
2023-01-11 12:13                                                               ` Andy Chiu
2023-01-23 12:17                                                                 ` Conor Dooley
2023-01-23 13:29                                                                   ` Andy Chiu
2023-01-11  5:05                                                   ` Anup Patel
2023-01-11  5:23                                                   ` Richard Henderson
2022-12-22 22:33                           ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Richard Henderson
2022-12-22 23:47                           ` Conor Dooley
2022-12-22 23:58                             ` Vineet Gupta
2022-12-22 20:30                         ` Vineet Gupta
2022-12-22 21:38                           ` Andrew Waterman
2022-12-22  1:50                     ` Vincent Chen
2022-12-22  5:34                     ` Richard Henderson
2021-09-16 23:56         ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Ben Woodard
2021-09-18  3:15           ` Vincent Chen
2021-09-20 16:41             ` DJ Delorie
2021-09-20 17:10               ` Florian Weimer
2021-10-01  1:43                 ` Vincent Chen [this message]
2021-10-01 12:08                   ` Adhemerval Zanella
2021-09-17 17:03         ` Rich Felker
2021-09-18  3:19           ` Vincent Chen
2021-09-13  1:41 ` [RFC patch 3/5] RISC-V: Save and restore VCSR when doing user context switch Vincent Chen
2021-09-14 23:48   ` Joseph Myers
2021-09-15  0:13     ` Andrew Waterman
2021-09-16  9:20       ` Vincent Chen
2021-10-01 13:04   ` Adhemerval Zanella
2021-09-13  1:41 ` [RFC patch 4/5] RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers Vincent Chen
2021-09-13 13:51   ` Rich Felker
2021-09-16  9:25     ` Vincent Chen
2021-09-13  1:41 ` [RFC 5/5] RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment Vincent Chen
2021-09-14 23:43   ` Joseph Myers
2021-09-15 10:42     ` Florian Weimer
2021-09-15 14:31       ` H.J. Lu
2021-09-16 10:21         ` Vincent Chen
2021-09-13 19:11 ` [RFC patch 0/5] RISC-V: Add vector ISA support Vineet Gupta
2021-09-15 19:37   ` Jim Wilson
2021-11-09 19:21 ` Darius Rad
2021-11-09 19:30   ` Andrew Waterman
2021-11-09 22:03     ` Darius Rad
2021-11-09 22:18       ` Andrew Waterman
2021-11-10 11:39         ` Darius Rad

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