* [PATCH] riscv: Add macros for FPUCW in fpu_control.h
@ 2023-02-11 17:49 Shiqi Zhang
2023-02-11 20:21 ` Andreas Schwab
0 siblings, 1 reply; 3+ messages in thread
From: Shiqi Zhang @ 2023-02-11 17:49 UTC (permalink / raw)
To: libc-alpha; +Cc: Shiqi Zhang
Add macros for rounding modes and accrued exception flags in order to
make controlling FPCSR easier for users.
Reference: RISC-V Unprivileged Spec v20191213, Section 11.2, Table 11.1 & 11.2
---
I'm implementing RISC-V support for netlib/f2c, and found that
there is no definitions for FPCSR flag bits in glibc when writing codes
for FPU exception controls. So I checked them in RISC-V specs and
defined the accrued exception flags and rounding mode flags in this
patch, making it easier for other users to control FPU status.
Also, I think these macros should be documented somewhere but I'm
not sure where should I doc them. I'll appreciate it if you could give
some suggestions.
For copyrights, this patch is covered by an existing copyright
assignment of ISCAS/ISRC so I'm assuming that there shouldn't be a
signed-off-by line in commit message.
sysdeps/riscv/fpu_control.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/sysdeps/riscv/fpu_control.h b/sysdeps/riscv/fpu_control.h
index c33798c6bb..5c883be4fe 100644
--- a/sysdeps/riscv/fpu_control.h
+++ b/sysdeps/riscv/fpu_control.h
@@ -36,6 +36,21 @@ extern fpu_control_t __fpu_control;
# define _FPU_DEFAULT 0
# define _FPU_IEEE _FPU_DEFAULT
+/* FPU rounding modes */
+# define _FPU_RM_RNE (0 << 5)
+# define _FPU_RM_RTZ (1 << 5)
+# define _FPU_RM_RDN (2 << 5)
+# define _FPU_RM_RUP (3 << 5)
+# define _FPU_RM_RMM (4 << 5)
+# define _FPU_RM_DYN (7 << 5)
+
+/* FPU accrued exception flags */
+# define _FPU_EXCEPT_NV (1 << 0)
+# define _FPU_EXCEPT_NZ (1 << 1)
+# define _FPU_EXCEPT_OF (1 << 2)
+# define _FPU_EXCEPT_UF (1 << 3)
+# define _FPU_EXCEPT_NX (1 << 4)
+
/* Type of the control word. */
typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
--
2.39.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: Add macros for FPUCW in fpu_control.h
2023-02-11 17:49 [PATCH] riscv: Add macros for FPUCW in fpu_control.h Shiqi Zhang
@ 2023-02-11 20:21 ` Andreas Schwab
2023-02-12 6:29 ` Shiqi Zhang
0 siblings, 1 reply; 3+ messages in thread
From: Andreas Schwab @ 2023-02-11 20:21 UTC (permalink / raw)
To: Shiqi Zhang; +Cc: libc-alpha
On Feb 12 2023, Shiqi Zhang wrote:
> +# define _FPU_RM_DYN (7 << 5)
That is only valid in an insn encoding, not in the fcsr register.
> +/* FPU accrued exception flags */
> +# define _FPU_EXCEPT_NV (1 << 0)
> +# define _FPU_EXCEPT_NZ (1 << 1)
> +# define _FPU_EXCEPT_OF (1 << 2)
> +# define _FPU_EXCEPT_UF (1 << 3)
> +# define _FPU_EXCEPT_NX (1 << 4)
You got them backwards.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: Add macros for FPUCW in fpu_control.h
2023-02-11 20:21 ` Andreas Schwab
@ 2023-02-12 6:29 ` Shiqi Zhang
0 siblings, 0 replies; 3+ messages in thread
From: Shiqi Zhang @ 2023-02-12 6:29 UTC (permalink / raw)
To: Andreas Schwab; +Cc: libc-alpha
>> +# define _FPU_RM_DYN (7 << 5)
> That is only valid in an insn encoding, not in the fcsr register.
Thank you very much for the tip!
>> +/* FPU accrued exception flags */
>> +# define _FPU_EXCEPT_NV (1 << 0)
>> +# define _FPU_EXCEPT_NZ (1 << 1)
>> +# define _FPU_EXCEPT_OF (1 << 2)
>> +# define _FPU_EXCEPT_UF (1 << 3)
>> +# define _FPU_EXCEPT_NX (1 << 4)
> You got them backwards.
Sorry for my carelessness. I mistakenly assumed that flags in table 11.2
was listed from lower to higher bits. Will send a v2 soon.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-02-11 17:49 [PATCH] riscv: Add macros for FPUCW in fpu_control.h Shiqi Zhang
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