* [PATCH] x86: Disable RTM on Skylake [BZ #27398]
@ 2021-03-27 18:34 H.J. Lu
2021-03-27 19:15 ` Florian Weimer
0 siblings, 1 reply; 8+ messages in thread
From: H.J. Lu @ 2021-03-27 18:34 UTC (permalink / raw)
To: libc-alpha; +Cc: Florian Weimer, Siddhesh Poyarekar
Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM
feature.
---
sysdeps/x86/cpu-features.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index d7248cbb45..3641a48407 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features)
with stepping >= 4) to avoid TSX on kernels that weren't
updated with the latest microcode package (which disables
broken feature by default). */
+ case 0x8e:
+ case 0x9e:
+ /* Disable RTM explicitly on Skylake since CPUID may report
+ RTM feature incorrectly [BZ #27398]. */
CPU_FEATURE_UNSET (cpu_features, RTM);
break;
}
--
2.30.2
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]
2021-03-27 18:34 [PATCH] x86: Disable RTM on Skylake [BZ #27398] H.J. Lu
@ 2021-03-27 19:15 ` Florian Weimer
2021-03-27 19:57 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Florian Weimer @ 2021-03-27 19:15 UTC (permalink / raw)
To: H.J. Lu via Libc-alpha; +Cc: H.J. Lu, Siddhesh Poyarekar
* H. J. Lu via Libc-alpha:
> Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM
> feature.
> ---
> sysdeps/x86/cpu-features.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index d7248cbb45..3641a48407 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features)
> with stepping >= 4) to avoid TSX on kernels that weren't
> updated with the latest microcode package (which disables
> broken feature by default). */
> + case 0x8e:
> + case 0x9e:
> + /* Disable RTM explicitly on Skylake since CPUID may report
> + RTM feature incorrectly [BZ #27398]. */
> CPU_FEATURE_UNSET (cpu_features, RTM);
> break;
> }
Won't this affect the server parts as well? I'm not sure if that's
what our users want.
We need to report the kernel bug properly, it got stalled because we
initially suspected it might be a security bug.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]
2021-03-27 19:15 ` Florian Weimer
@ 2021-03-27 19:57 ` H.J. Lu
2021-03-27 20:02 ` Florian Weimer
0 siblings, 1 reply; 8+ messages in thread
From: H.J. Lu @ 2021-03-27 19:57 UTC (permalink / raw)
To: Florian Weimer; +Cc: H.J. Lu via Libc-alpha, Siddhesh Poyarekar
On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote:
>
> * H. J. Lu via Libc-alpha:
>
> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM
> > feature.
> > ---
> > sysdeps/x86/cpu-features.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > index d7248cbb45..3641a48407 100644
> > --- a/sysdeps/x86/cpu-features.c
> > +++ b/sysdeps/x86/cpu-features.c
> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features)
> > with stepping >= 4) to avoid TSX on kernels that weren't
> > updated with the latest microcode package (which disables
> > broken feature by default). */
> > + case 0x8e:
> > + case 0x9e:
> > + /* Disable RTM explicitly on Skylake since CPUID may report
> > + RTM feature incorrectly [BZ #27398]. */
> > CPU_FEATURE_UNSET (cpu_features, RTM);
> > break;
> > }
>
> Won't this affect the server parts as well? I'm not sure if that's
> what our users want.
No since Xeon has a different model number (0x55).
> We need to report the kernel bug properly, it got stalled because we
> initially suspected it might be a security bug.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]
2021-03-27 19:57 ` H.J. Lu
@ 2021-03-27 20:02 ` Florian Weimer
2021-03-27 20:13 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Florian Weimer @ 2021-03-27 20:02 UTC (permalink / raw)
To: H.J. Lu; +Cc: H.J. Lu via Libc-alpha, Siddhesh Poyarekar
* H. J. Lu:
> On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote:
>>
>> * H. J. Lu via Libc-alpha:
>>
>> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM
>> > feature.
>> > ---
>> > sysdeps/x86/cpu-features.c | 4 ++++
>> > 1 file changed, 4 insertions(+)
>> >
>> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
>> > index d7248cbb45..3641a48407 100644
>> > --- a/sysdeps/x86/cpu-features.c
>> > +++ b/sysdeps/x86/cpu-features.c
>> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features)
>> > with stepping >= 4) to avoid TSX on kernels that weren't
>> > updated with the latest microcode package (which disables
>> > broken feature by default). */
>> > + case 0x8e:
>> > + case 0x9e:
>> > + /* Disable RTM explicitly on Skylake since CPUID may report
>> > + RTM feature incorrectly [BZ #27398]. */
>> > CPU_FEATURE_UNSET (cpu_features, RTM);
>> > break;
>> > }
>>
>> Won't this affect the server parts as well? I'm not sure if that's
>> what our users want.
>
> No since Xeon has a different model number (0x55).
Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]
2021-03-27 20:02 ` Florian Weimer
@ 2021-03-27 20:13 ` H.J. Lu
2021-03-27 20:16 ` Florian Weimer
2021-03-27 20:16 ` H.J. Lu
0 siblings, 2 replies; 8+ messages in thread
From: H.J. Lu @ 2021-03-27 20:13 UTC (permalink / raw)
To: Florian Weimer; +Cc: H.J. Lu via Libc-alpha, Siddhesh Poyarekar
On Sat, Mar 27, 2021 at 1:02 PM Florian Weimer <fw@deneb.enyo.de> wrote:
>
> * H. J. Lu:
>
> > On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote:
> >>
> >> * H. J. Lu via Libc-alpha:
> >>
> >> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM
> >> > feature.
> >> > ---
> >> > sysdeps/x86/cpu-features.c | 4 ++++
> >> > 1 file changed, 4 insertions(+)
> >> >
> >> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> >> > index d7248cbb45..3641a48407 100644
> >> > --- a/sysdeps/x86/cpu-features.c
> >> > +++ b/sysdeps/x86/cpu-features.c
> >> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features)
> >> > with stepping >= 4) to avoid TSX on kernels that weren't
> >> > updated with the latest microcode package (which disables
> >> > broken feature by default). */
> >> > + case 0x8e:
> >> > + case 0x9e:
> >> > + /* Disable RTM explicitly on Skylake since CPUID may report
> >> > + RTM feature incorrectly [BZ #27398]. */
> >> > CPU_FEATURE_UNSET (cpu_features, RTM);
> >> > break;
> >> > }
> >>
> >> Won't this affect the server parts as well? I'm not sure if that's
> >> what our users want.
> >
> > No since Xeon has a different model number (0x55).
>
> Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too.
Does it have RTM?
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]
2021-03-27 20:13 ` H.J. Lu
@ 2021-03-27 20:16 ` Florian Weimer
2021-03-27 20:16 ` H.J. Lu
2021-03-27 20:16 ` H.J. Lu
1 sibling, 1 reply; 8+ messages in thread
From: Florian Weimer @ 2021-03-27 20:16 UTC (permalink / raw)
To: H.J. Lu; +Cc: H.J. Lu via Libc-alpha, Siddhesh Poyarekar
* H. J. Lu:
>> Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too.
>
> Does it have RTM?
Yes, it does.
Maybe we should try to track down Siddhesh's bug instead?
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]
2021-03-27 20:16 ` Florian Weimer
@ 2021-03-27 20:16 ` H.J. Lu
0 siblings, 0 replies; 8+ messages in thread
From: H.J. Lu @ 2021-03-27 20:16 UTC (permalink / raw)
To: Florian Weimer; +Cc: H.J. Lu via Libc-alpha, Siddhesh Poyarekar
On Sat, Mar 27, 2021 at 1:16 PM Florian Weimer <fw@deneb.enyo.de> wrote:
>
> * H. J. Lu:
>
> >> Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too.
> >
> > Does it have RTM?
>
> Yes, it does.
>
> Maybe we should try to track down Siddhesh's bug instead?
Yes.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]
2021-03-27 20:13 ` H.J. Lu
2021-03-27 20:16 ` Florian Weimer
@ 2021-03-27 20:16 ` H.J. Lu
1 sibling, 0 replies; 8+ messages in thread
From: H.J. Lu @ 2021-03-27 20:16 UTC (permalink / raw)
To: Florian Weimer; +Cc: H.J. Lu via Libc-alpha, Siddhesh Poyarekar
On Sat, Mar 27, 2021 at 1:13 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Sat, Mar 27, 2021 at 1:02 PM Florian Weimer <fw@deneb.enyo.de> wrote:
> >
> > * H. J. Lu:
> >
> > > On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote:
> > >>
> > >> * H. J. Lu via Libc-alpha:
> > >>
> > >> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM
> > >> > feature.
> > >> > ---
> > >> > sysdeps/x86/cpu-features.c | 4 ++++
> > >> > 1 file changed, 4 insertions(+)
> > >> >
> > >> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > >> > index d7248cbb45..3641a48407 100644
> > >> > --- a/sysdeps/x86/cpu-features.c
> > >> > +++ b/sysdeps/x86/cpu-features.c
> > >> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features)
> > >> > with stepping >= 4) to avoid TSX on kernels that weren't
> > >> > updated with the latest microcode package (which disables
> > >> > broken feature by default). */
> > >> > + case 0x8e:
> > >> > + case 0x9e:
> > >> > + /* Disable RTM explicitly on Skylake since CPUID may report
> > >> > + RTM feature incorrectly [BZ #27398]. */
> > >> > CPU_FEATURE_UNSET (cpu_features, RTM);
> > >> > break;
> > >> > }
> > >>
> > >> Won't this affect the server parts as well? I'm not sure if that's
> > >> what our users want.
> > >
> > > No since Xeon has a different model number (0x55).
> >
> > Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too.
>
> Does it have RTM?
It does have TSX:
https://ark.intel.com/content/www/us/en/ark/products/97469/intel-xeon-processor-e3-1240-v6-8m-cache-3-70-ghz.html
Then my patch won't work.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-03-27 20:17 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2021-03-27 18:34 [PATCH] x86: Disable RTM on Skylake [BZ #27398] H.J. Lu
2021-03-27 19:15 ` Florian Weimer
2021-03-27 19:57 ` H.J. Lu
2021-03-27 20:02 ` Florian Weimer
2021-03-27 20:13 ` H.J. Lu
2021-03-27 20:16 ` Florian Weimer
2021-03-27 20:16 ` H.J. Lu
2021-03-27 20:16 ` H.J. Lu
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