Re: [PATCH] Unify pthread_spin_[try]lock implementations.

[Chris Metcalf <cmetcalf@tilera.com>]

On 7/25/2012 2:13 PM, Roland McGrath wrote:
> Here I think the reasonable thing to do is:
>
> /* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
>    to the number of plain reads that it's optimal to spin on between uses
>    of atomic_compare_and_exchange_val_acq.  If spinning forever is optimal
>    then use -1.  If no plain reads here would ever be optimal, use 0.  */
> #ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
> # warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
> # define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
> #endif
>
> Then ARM et al can do:
>
> /* Machine-dependent rationale about the selection of this value.  */
> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
> #include <nptl/pthread_spin_lock.c>
>
> while Teil will use -1.

The tile architecture is unlikely to use this generic version no matter
what; see http://sourceware.org/ml/libc-ports/2012-07/msg00030.html for the
details, but the primary point is that in a mesh-based architecture it's a
bad idea to ever end up in a situation where all the cores can be spinning
issues loads or cmpxchg as fast as they can, so some kind of backoff is
necessary.

-- 
Chris Metcalf, Tilera Corp.
http://www.tilera.com