From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Jingtao Cai <caijingtao@huawei.com>, Bo Dong <dongbo4@huawei.com>,
<binutils@sourceware.org>
Subject: Re: [PATCH RESEND v2] Aarch64: Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}
Date: Thu, 10 Mar 2022 20:24:26 +0800 [thread overview]
Message-ID: <07dba12f-d9f9-ea92-cdea-2f084d4d1116@hisilicon.com> (raw)
In-Reply-To: <983f339f-aed8-7250-4e99-c9e77ea25b28@suse.com>
Hi,
On 2022/3/10 19:50, Jan Beulich wrote:
> On 10.03.2022 12:33, Shaokun Zhang wrote:
>> On 2022/3/10 18:38, Jan Beulich wrote:
>>> On 10.03.2022 10:38, Shaokun Zhang wrote:
>>>> Hi Jan,
>>>
>>> Despite this, ...
>>>
>>>> On 2022/3/2 15:36, Shaokun Zhang wrote:
>>>>> On 2022/2/21 21:13, Jan Beulich wrote:
>>>>>> On 16.02.2022 01:53, Shaokun Zhang wrote:
>>>>>>> --- a/gas/testsuite/gas/aarch64/sve-movprfx_23.d
>>>>>>> +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.d
>>>>>>> @@ -9,29 +9,29 @@ Disassembly of section .*:
>>>>>>>
>>>>>>> 0+ <.*>:
>>>>>>> [^:]+: 04512461 movprfx z1.h, p1/m, z3.h
>>>>>>> -[^:]+: 256c8021 incp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
>>>>>>> +[^:]+: 256c8021 incp z1.h, p1.h // note: merging predicate expected due to preceding `movprfx' at operand 2
>>>>>>
>>>>>> I have a more general question here: Couldn't the spec make optional the
>>>>>> use of all the same size specifiers when there are multiple, same element
>>>>>> size operands? One such suffix of course needs to be there to disambiguate
>>>>>
>>>>> We are not from ARM SPEC group and don't know the exact considerations for
>>>>> the forbidden omitting suffix. We guess people will have different answers from
>>>>> different points of view.
>>>>>
>>>>> >From our point of view, a suffix makes the assembly more consistent with the
>>>>> scalar versions of `incp`, e.g. `incp x1, p2.b`. And the predicate register acts more
>>>>> like a vector register within this instruction, with suffix, the addend for each element
>>>>> is clear once reading the assembly string.
>>>>>
>>>>> Not sure that anyone from ARM in the mail-list can give more hints or thoughts.
>>>>>
>>>>
>>>> No any more comments from Arm guys.
>>>>
>>>> Is it ok for trunk?
>>>
>>> ... I assume you understand that I'm not in the position to give you the
>>> wanted "okay"?
>>
>> Apologies that I don't follow it completely, do you mean that does it need
>> someone to agree and take it? Or we need more comments?
>
> Well, as for any patch a maintainer of the code needs to give you their okay.
>
Oh, Got it, I will loop the AARCH64 maintainers.
Thanks Jan.
> Jan
>
> .
>
next prev parent reply other threads:[~2022-03-10 12:24 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 0:53 Shaokun Zhang
2022-02-21 13:13 ` Jan Beulich
2022-03-02 7:36 ` Shaokun Zhang
2022-03-10 9:38 ` Shaokun Zhang
2022-03-10 10:38 ` Jan Beulich
2022-03-10 11:33 ` Shaokun Zhang
2022-03-10 11:50 ` Jan Beulich
2022-03-10 12:24 ` Shaokun Zhang [this message]
2022-03-10 12:27 ` Shaokun Zhang
2022-09-12 8:17 ` Richard Sandiford
2022-09-12 8:27 ` Jan Beulich
2022-09-12 9:38 ` Richard Sandiford
2022-09-28 2:19 ` dongbo (E)
2022-09-30 14:54 ` Richard Sandiford
2022-10-09 1:31 ` dongbo (E)
2022-10-10 10:25 ` Richard Sandiford
2022-10-11 2:19 ` dongbo (E)
2022-10-17 9:33 ` Richard Sandiford
2022-10-18 5:57 ` dongbo (E)
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