* [PATCH 0/1] RISC-V: RISC-V: Move standard hints before all instructions @ 2022-10-08 4:31 Tsukasa OI 2022-10-08 4:31 ` [PATCH 1/1] " Tsukasa OI 0 siblings, 1 reply; 3+ messages in thread From: Tsukasa OI @ 2022-10-08 4:31 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils Hello, GitHub tracker: <https://github.com/a4lg/binutils-gdb/wiki/riscv_opcode_tidying_hints_1> This is another small tidying patchset. Because of the scanning process of the RISC-V disassembler, all standard hints must be placed before corresponding instruction. In the past, "prefetch.[irw]" (from 'Zicbop') hints are placed just before ORI and "pause" (from 'Zihintpause') is placed just before FENCE. It's not bad but will force the developer to "taint" basic instructions section. Considering upcoming 'Zihintntl' standard hints will be a bit more complex than the current hints (some can be a part of either "ADD" or "C.ADD") and the disassembler is fine as long as a hint instruction is placed before the base instruction (no need them to be adjacent), I think moving all standard hints before all real instructions might improve the readability and won't disrupt the indentation of basic instructions anymore. Thanks, Tsukasa Tsukasa OI (1): RISC-V: Move standard hints before all instructions opcodes/riscv-opc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) base-commit: 4cbfd0daabd68516651ee37a19d0e24ca4789ea3 -- 2.34.1 ^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/1] RISC-V: Move standard hints before all instructions 2022-10-08 4:31 [PATCH 0/1] RISC-V: RISC-V: Move standard hints before all instructions Tsukasa OI @ 2022-10-08 4:31 ` Tsukasa OI 2022-10-14 1:37 ` Nelson Chu 0 siblings, 1 reply; 3+ messages in thread From: Tsukasa OI @ 2022-10-08 4:31 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils Because all standard hints must be placed before corresponding instruction for the disassembler, they may taint basic RVI instruction section. This commit moves all standard hints before all basic RVI instructions to improve maintainability. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Move all standard hints before all standard instructions. --- opcodes/riscv-opc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 11bb87d7eaa..4827aad9351 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -298,6 +298,14 @@ match_th_load_pair(const struct riscv_opcode *op, const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ + +/* Standard hints. */ +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, +{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, + +/* Basic RVI instructions and aliases. */ {"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS }, {"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW|(CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ {"ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, @@ -417,9 +425,6 @@ const struct riscv_opcode riscv_opcodes[] = {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, -{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, -{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, -{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, {"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, @@ -446,7 +451,6 @@ const struct riscv_opcode riscv_opcodes[] = {"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, -{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "",MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, {"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] RISC-V: Move standard hints before all instructions 2022-10-08 4:31 ` [PATCH 1/1] " Tsukasa OI @ 2022-10-14 1:37 ` Nelson Chu 0 siblings, 0 replies; 3+ messages in thread From: Nelson Chu @ 2022-10-14 1:37 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils On Sat, Oct 8, 2022 at 12:32 PM Tsukasa OI via Binutils <binutils@sourceware.org> wrote: > > Because all standard hints must be placed before corresponding instruction > for the disassembler, they may taint basic RVI instruction section. > > This commit moves all standard hints before all basic RVI instructions > to improve maintainability. OK, improving maintainability makes sense and the reason is enough to me, please commit. Thanks Nelson > opcodes/ChangeLog: > > * riscv-opc.c (riscv_opcodes): Move all standard hints before all > standard instructions. > --- > opcodes/riscv-opc.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 11bb87d7eaa..4827aad9351 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -298,6 +298,14 @@ match_th_load_pair(const struct riscv_opcode *op, > const struct riscv_opcode riscv_opcodes[] = > { > /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ > + > +/* Standard hints. */ > +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > +{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, > + > +/* Basic RVI instructions and aliases. */ > {"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS }, > {"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW|(CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ > {"ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, > @@ -417,9 +425,6 @@ const struct riscv_opcode riscv_opcodes[] = > {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, > {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, > {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, > -{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > -{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > -{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > {"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, > {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, > {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, > @@ -446,7 +451,6 @@ const struct riscv_opcode riscv_opcodes[] = > {"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, > {"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, > {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, > -{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "",MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, > {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, > {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, > {"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 }, > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-10-14 1:37 UTC | newest] Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-10-08 4:31 [PATCH 0/1] RISC-V: RISC-V: Move standard hints before all instructions Tsukasa OI 2022-10-08 4:31 ` [PATCH 1/1] " Tsukasa OI 2022-10-14 1:37 ` Nelson Chu
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