From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 2/3] RISC-V: Fix RV32 disassembler address computation
Date: Fri, 29 Jul 2022 22:10:35 +0900 [thread overview]
Message-ID: <1afdbfe4db2229d4dbbef857a49769827aac617d.1659100228.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1659100228.git.research_trasio@irq.a4lg.com>
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this bug (including PR29342) by fitting an address into a 32-bit value
on RV32.
gas/ChangeLog:
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
opcodes/ChangeLog:
* riscv-dis.c (maybe_print_address): Clarify the role of the `wide'
argument and rename to `is_addiw'. Fit the address into 32-bit on
RV32. (print_insn_args): Reflect bool type of `is_addiw'.
---
gas/testsuite/gas/riscv/lla32.d | 2 +-
opcodes/riscv-dis.c | 24 ++++++++++++++----------
2 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
index 9d875629064..8e9324c1c96 100644
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -14,6 +14,6 @@ Disassembly of section .text:
10: 00001537 lui a0,0x1
14: fff50513 addi a0,a0,-1 # fff <d>
18: 80000537 lui a0,0x80000
- 1c: fff50513 addi a0,a0,-1 # 7fffffff <h\+0x80000000>
+ 1c: fff50513 addi a0,a0,-1 # 7fffffff <e>
20: 00000513 li a0,0
24: fff00513 li a0,-1
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 31a7e0975d2..83438db5fe3 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -171,7 +171,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
static void
maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
- int wide)
+ bool is_addiw)
{
if (pd->hi_addr[base_reg] != (bfd_vma)-1)
{
@@ -186,9 +186,13 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
return;
pd->to_print_addr = true;
- /* Sign-extend a 32-bit value to a 64-bit value. */
- if (wide)
+ /* On ADDIW, Sign-extend a 32-bit value to a 64-bit value. */
+ if (is_addiw)
pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
+
+ /* Fit into a 32-bit value on RV32. */
+ if (xlen == 32)
+ pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
}
/* Print insn arguments for 32/64-bit code. */
@@ -238,10 +242,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
case 'o':
case 'j':
if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
- maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
+ maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), false);
if (info->mach == bfd_mach_riscv64
&& ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
- maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
+ maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), true);
print (info->stream, dis_style_immediate, "%d",
(int)EXTRACT_CITYPE_IMM (l));
break;
@@ -401,7 +405,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
case 'b':
case 's':
if ((l & MASK_JALR) == MATCH_JALR)
- maybe_print_address (pd, rs1, 0, 0);
+ maybe_print_address (pd, rs1, 0, false);
print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
break;
@@ -431,21 +435,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
break;
case 'o':
- maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
/* Fall through. */
case 'j':
if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
|| (l & MASK_JALR) == MATCH_JALR)
- maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
if (info->mach == bfd_mach_riscv64
&& ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
- maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), true);
print (info->stream, dis_style_immediate, "%d",
(int)EXTRACT_ITYPE_IMM (l));
break;
case 'q':
- maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0);
+ maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), false);
print (info->stream, dis_style_address_offset, "%d",
(int)EXTRACT_STYPE_IMM (l));
break;
--
2.34.1
next prev parent reply other threads:[~2022-07-29 13:11 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-29 13:10 [PATCH 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-07-29 13:10 ` Tsukasa OI [this message]
2022-07-29 13:10 ` [PATCH 3/3] RISC-V: Add address printer tests " Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 3/4] RISC-V: Break early if RISCV_GP_SYMBOL is found Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-08 18:31 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler H. Peter Anvin
2022-08-08 19:46 ` Palmer Dabbelt
2022-08-09 3:39 ` [PATCH v3 0/4] " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 0/5] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 1/5] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-24 11:22 ` Nelson Chu
2022-08-24 11:22 ` Nelson Chu
2022-08-24 12:06 ` Tsukasa OI
2022-08-25 5:07 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 2/5] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-24 11:35 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 3/5] RISC-V: Fix JALR target " Tsukasa OI
2022-08-24 11:36 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 4/5] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 11:42 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 5/5] RISC-V: Add address printer tests with ADDIW Tsukasa OI
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1afdbfe4db2229d4dbbef857a49769827aac617d.1659100228.git.research_trasio@irq.a4lg.com \
--to=research_trasio@irq.a4lg.com \
--cc=binutils@sourceware.org \
--cc=hpa@zytor.com \
--cc=kito.cheng@sifive.com \
--cc=nelson.chu@sifive.com \
--cc=palmer@dabbelt.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).