From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 0/4] RISC-V: Fix address printer on the disassembler
Date: Tue, 2 Aug 2022 14:54:17 +0900 [thread overview]
Message-ID: <cover.1659419591.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1659100228.git.research_trasio@irq.a4lg.com>
Hello,
This patchset contains a fix to PR29342.
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_dis_fix_addr>
Original Issue as reported by H. Peter Anvin:
<https://sourceware.org/bugzilla/show_bug.cgi?id=29342>
[Changes: v1 -> v2]
- Also allow `gp'-base symbol (__global_pointer$) to be the highest address
- Add minor optimization (break early if multiple __global_pointer$ is found)
- Rebase and minor copyediting
[Performance Analysis (Summary)]
This patch alone degrades the disassembler performance a bit (usually about 1%
but around 4% on binary files) but I found my next batch of the disassembler
optimization patchset somehow shadows this. In fact, Binutils with my
optimization patchset 1 and Binutils with my optimization patchset 1 plus this
patchset has pretty much the same performance.
[Cover Letter from v1]
First of all, this bug is caused by address computation of maybe_print_address
on disassembling RV32 programs.
Let me show the pseudocode of `maybe_print_address':
if (high part of the register [for address sequence] is set)
{
pd->print_addr = (high part) + offset; // (1)
unset high part (as used);
}
else if (base register == `gp' && __global_pointer$ is available)
pd->print_addr = __global_pointer$ + offset; // (2)
else if (base register == `tp' || base register == `zero')
pd->print_addr = offset; // (3)
// Sign-extend a 32-bit value to 64-bit
if (instruction is ADDIW or C.ADDIW)
pd->print_addr = (bfd_vma)(int32_t)pd->print_addr;
In here, it implicitly sign-extends an `int'-typed variable `offset' to generate
an address. (3) is the direct cause of PR29342 but other locations have
similar issue.
On an example provided by Peter, IOREG_FOO has an address value of 0xffffff00.
However, due to incorrect sign-extension, the disassembler considers that the
`sw' instruction operates on an incorrect address 0xffffffff_ffffff00 EVEN ON
RV32. This affects symbol lookup. So, we have to mask (and zero-extend) the
address on RV32 to get correct address 0xffffff00.
Also, the background provided by Peter gives us a context: highest address space
may be important for some systems/programs. So, not only fixing PR29342, I
decided to make the address -1 (originally reserved as a non-printing address)
printable by separating (a) the address to print and (b) whether the address
should be printed. This isn't zero-overhead but close to.
This patchset:
1. fits an address into a 32-bit value on RV32 (resolves PR29342)
2. makes the highest address printable
(0xffffffff can be printed as a real symbol)
3. clarifies the meaning of the `wide' argument
(`is_addiw' fits the context).
It also has new testcases and a testcase modification (it seems lla32.d is
affected by this patchset but not harmful so that modifying the testcase
lla32.d seemed better).
Thanks,
Tsukasa
Tsukasa OI (4):
RISC-V: Print highest address on disassembler
RISC-V: Fix RV32 disassembler address computation
RISC-V: Break early if RISCV_GP_SYMBOL is found
RISC-V: Add address printer tests on disassembler
gas/testsuite/gas/riscv/dis-addr-1-32.d | 29 ++++++++++
gas/testsuite/gas/riscv/dis-addr-1-64.d | 33 ++++++++++++
gas/testsuite/gas/riscv/dis-addr-1.s | 70 +++++++++++++++++++++++++
gas/testsuite/gas/riscv/dis-addr-2-32.d | 12 +++++
gas/testsuite/gas/riscv/dis-addr-2-64.d | 12 +++++
gas/testsuite/gas/riscv/dis-addr-2.s | 15 ++++++
gas/testsuite/gas/riscv/lla32.d | 2 +-
opcodes/riscv-dis.c | 47 +++++++++++------
8 files changed, 203 insertions(+), 17 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/dis-addr-1-32.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-1-64.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-1.s
create mode 100644 gas/testsuite/gas/riscv/dis-addr-2-32.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-2-64.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-2.s
base-commit: f493c2174ef99a43c0a5d89179122f857955d738
--
2.34.1
next prev parent reply other threads:[~2022-08-02 5:54 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-29 13:10 [PATCH 0/3] " Tsukasa OI
2022-07-29 13:10 ` [PATCH 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-07-29 13:10 ` [PATCH 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-02 5:54 ` Tsukasa OI [this message]
2022-08-02 5:54 ` [PATCH v2 1/4] RISC-V: Print highest address " Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 3/4] RISC-V: Break early if RISCV_GP_SYMBOL is found Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-08 18:31 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler H. Peter Anvin
2022-08-08 19:46 ` Palmer Dabbelt
2022-08-09 3:39 ` [PATCH v3 0/4] " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 0/5] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 1/5] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-24 11:22 ` Nelson Chu
2022-08-24 11:22 ` Nelson Chu
2022-08-24 12:06 ` Tsukasa OI
2022-08-25 5:07 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 2/5] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-24 11:35 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 3/5] RISC-V: Fix JALR target " Tsukasa OI
2022-08-24 11:36 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 4/5] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 11:42 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 5/5] RISC-V: Add address printer tests with ADDIW Tsukasa OI
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